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| (R) FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET DESCRIPTION: IDT54/74FCT273 IDT54/74FCT273A IDT54/74FCT273C Integrated Device Technology, Inc. FEATURES: * * * * * * * * * * * * * IDT54/74FCT273 equivalent to FASTTM speed; IDT54/74FCT273A 45% faster than FAST IDT54/74FCT273C 55% faster than FAST Equivalent to FAST output drive over full temperature and voltage supply extremes IOL = 48mA (commercial) and 32mA (military) CMOS power levels (1mW typ. static) TTL input and output level compatible CMOS output level compatible Substantially lower input current levels than FAST (5A max.) Octal D flip-flop with Master Reset JEDEC standard pinout for DIP and LCC Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B The IDT54/74FCT273/A/C are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273/A/C have eight edge-triggered D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. MR FUNCTIONAL BLOCK DIAGRAM D0 CP D CP RD MR O0 O1 O2 O3 O4 O5 O6 O7 2558 drw 01 D1 D2 D3 D4 D5 D6 D7 Q D CP Q RD D CP Q RD D CP Q RD D CP Q RD D CP Q RD D CP Q RD D CP Q RD PIN CONFIGURATIONS D0 O0 MR Vcc O7 32 4 5 6 7 8 1 20 19 18 17 16 15 14 9 10 11 12 13 O3 GND CP O4 D4 MR O0 D0 D1 O1 O2 D2 D3 O3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 P20-1 D20-1 SO20-2 & E20-1 17 16 15 14 13 12 11 Vcc O7 D7 D6 O6 O5 D5 D4 O4 CP INDEX D1 O1 O2 D2 D3 L20-2 D7 D6 O6 O5 D5 2558 drw 02 DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a registered trademark of National Semiconductor Co. MILITARY AND COMMERCIAL TEMPERATURE RANGES (c)1992 Integrated Device Technology, Inc. MAY 1992 DSC-4609/2 7.10 1 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Names DN Description Data Input Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs 2558 tbl 05 FUNCTION TABLE Operating Mode Reset (Clear) Load "1" Load "0" MR CP ON MR L H H Inputs CP X DN X h l Outputs ON L H L NOTES: 2558 tbl 06 H = HIGH voltage level steady-state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don't care = LOW-to-HIGH clock transition ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM (2) CAPACITANCE (TA = +25C, f = 1.0MHz) Unit V Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions Typ. Max. VIN = 0V VOUT = 0V 6 8 10 12 Unit pF pF Rating Terminal Voltage with Respect to GND Commercial -0.5 to +7.0 Military -0.5 to +7.0 VTERM(3) Terminal Voltage with Respect to GND TA TBIAS TSTG PT IOUT Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current -0.5 to VCC -0.5 to VCC V NOTE: 2558 tbl 02 1. This parameter is guaranteed by characterization data and not tested. 0 to +70 -55 to +125 -55 to +125 0.5 120 -55 to +125 -65 to +135 -65 to +150 0.5 120 C C C W mA NOTES: 2558 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 7.10 2 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol VIH VIL IIH IIL VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Vcc = Min., IN = -18mA Vcc = Max.(3), VO = GND Vcc = 3V, VIN = VLC or VHC, IOH = -32A Vcc = Min. VIN = VIH or VIL VOL Output LOW Voltage IOH = -300A IOH = -12mA MIL. IOH = -15mA COM'L. Vcc = 3V, VIN = VLC or VHC, IOL = 300A Vcc = Min. VIN = VIH or VIL IOL = 300A IOL = 32mA MIL. IOL = 48mA COM'L. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND Min. 2.0 -- -- -- -- -- -- -60 VHC VHC 2.4 2.4 -- -- -- -- Typ.(2) -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 -1.2 -- -- -- -- -- VLC VLC(4) 0.5 0.5 2558 tbl 03 Unit V V A V mA V V NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 7.10 3 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC - 0.2V Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) Vcc = Max. VIN VHC; VIN VLC Vcc = Max. VIN = 3.4V(3) Vcc = Max. Outputs Open = VCC One Input Toggling 50% Duty Cycle VIN VHC VIN VLC Min. -- -- -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2.0 0.25 Unit mA mA mA/MHz MR IC Total Power Supply Current(6) Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND -- 1.7 4.0 mA MR -- 2.2 6.0 Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle = VCC Eight Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND -- 4.0 7.8(5) MR -- 6.2 16.8(5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 2558 tbl 04 7.10 4 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT54/74FCT273 Com'l. Symbol tPLH tPHL tPHL tSU tH tW tW tREM Parameter Propagation Delay Clock to Output Propagation Delay to Output Condition CL = 50 pF RL = 500 (1) IDT54/74FCT273A Com'l. (2) IDT54/74FCT273C Com'l. Min. (2) Mil. (2) Mil. (2) Mil. (2) Min. (2) Max. Min. Max. Min. Max. Min. Max. Max. Min. Max. Unit 2.0 2.0 3.0 2.0 7.0 7.0 4.0 13.0 13.0 -- -- -- -- -- 2.0 2.0 3.5 2.0 7.0 7.0 5.0 15.0 15.0 -- -- -- -- -- 2.0 2.0 2.0 1.5 6.0 6.0 2.0 7.2 7.2 -- -- -- -- -- 2.0 2.0 2.0 1.5 6.0 6.0 2.5 8.3 8.3 -- -- -- -- -- 2.0 2.0 2.0 1.5 6.0 6.0 2.0 5.8 6.1 -- -- -- -- -- 2.0 2.0 2.0 1.5 6.0 6.0 2.5 6.5 6.8 -- -- -- -- -- ns ns ns ns ns ns ns 2558 tbl 07 MR Set-up Time HIGH or LOW Data to CP Hold Time HIGH or LOW Data to CP Clock Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time to CP MR NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 7.10 5 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 V OUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: 2558 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. SET-UP, HOLD AND RELEASE TIMES DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM 3V 1.5V 0V 3V 1.5V 0V tH 3V 1.5V 0V 3V 1.5V 0V PULSE WIDTH LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V 1.5V t SU tH PROPAGATION DELAY 3V 1.5V tPLH OUTPUT t PLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V t PHL 0V VOH 1.5V VOL ENABLE AND DISABLE TIMES ENABLE CONTROL INPUT t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V t PHZ 0.3V 1.5V 0V V OH 0V t PLZ DISABLE 3V 1.5V 0V 3.5V V OL SAME PHASE INPUT TRANSITION NOTES 2558 drw 04 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns; tR 2.5ns. 7.10 6 IDT54/74FCT273/A/C FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT X Device Type X Package X Process Temperature Range Blank B P D SO L E 273 273A 273C 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Octal D Flip-Flop w/Clear Fast Octal D Flip-Flop w/Clear Super Fast Octal D Flip-Flop w/Clear -55C to +125C 0C to +70C 2558 drw 03 7.10 7 |
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