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13-3087; Rev 0; 1/04
KIT ATION EVALU ABLE AVAIL
Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
General Description
Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The MAX8555/MAX8555A are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The MAX8555/MAX8555A are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to (VCS+ + 5V). During startup, the MAX8555/MAX8555A monitor the voltage drop across the external MOSFETs. Once VCS+ approaches or exceeds the bus voltage (VCS-), the MOSFETs are turned on. The MAX8555/MAX8555A feature a dual-purpose TIMER input. A single external resistor from TIMER to ground sets the turn-on speed of the external MOSFETs. Optionally, the TIMER input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs' R DS(ON) , reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns. Both devices come in space-saving 10-pin MAX or TDFN packages and are specified over the extended -40C to +85C temperature range.
Features
Simple, Integrated, and Inexpensive MOSFET Controllers ORing FET Drive for 0.5V to 3.3V Eliminate ORing Diode Power Dissipation Provide N+1 Redundant Supply Capability for Highly Reliable Systems Isolate Failed Short-Circuit Supply from Output BUS Respond to Reverse Short-Circuit Current in 200ns Adjustable Blank Time Programmable Soft-Start Logic Enable Input Adjustable Overvoltage and Undervoltage Trip Points Fault-Indicator Output Space-Saving Packages
MAX8555/MAX8555A
Ordering Information
PART MAX8555ETB MAX8555EUB MAX8555AETB MAX8555AEUB TEMP RANGE -40C to 85C -40C to 85C -40C to 85C -40C to 85C PINPACKAGE 10 TDFN 3mm x 3mm* 10 MAX 10 TDFN 3mm x 3mm* 10 MAX TOP MARK ACC 8555EUB ADD 8555AEUB
Applications
Point-of-Load Supplies Power-Supply Modules Servers Telecom Power Supplies Rectifiers Redundant Power Supplies in High-Availability Systems
*Exposed paddle
Pin Configurations
TOP VIEW
GATE 1 GND VL VDD UVP 2 3 4 5
10 CS+ 9 CSOVP FAULT TIMER
GATE GND VL VDD UVP
1 2 3 4 5
10 CS+
MAX8555/ MAX8555A
8 7 6
MAX8555/ MAX8555A
9 CS8 OVP 7 FAULT 6 TIMER
Typical Operating Circuit appears at end of data sheet.
MAX
TDFN
________________________________________________________________ Maxim Integrated Products
1
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
ABSOLUTE MAXIMUM RATINGS
GATE to GND .........................................................-0.3V to +12V FAULT, VL to GND ...................................................-0.3V to +6V OVP, UVP, TIMER, CS+, CS- to GND .......-0.3V to +(VVL + 0.3V) VDD to GND..................................................(VVL - 0.3V) to +18V Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW 10-Pin TDFN (derate 24.4mW/C above +70C) .......1951mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.25V, RFAULT = 50k, CVDD = CGATE = CVL = 0.01F, TA = 0C to +85C, unless otherwise noted.)
PARAMETER VDD SUPPLY VDD Input Voltage VDD Supply Current VDD Shutdown Current VDD Overvoltage Internal Threshold VL SUPPLY VL Input Voltage VL Supply Current VL Current in Shutdown Mode VL Output Voltage VL Undervoltage Lockout CS INPUTS CS+, CS- Input Current Offset Input Current (CS+, CS-) CS+/CS- Input Range CS Isolation CHARGE-PUMP VOLTAGE GATE Voltage, VGATE Measured from GATE to CS+ RTIMER = 20k Charge-Pump Switching Frequency RTIMER = 125k RTIMER = open VTIMER = 1.5V VDD = 8V to 13.25V VDD = VVL = 5V 5.0 5.25 187 450 500 550 kHz 5.5 V VTIMER = 2.5V, VCS = 3.0V VCS = 3.0V, Figure 4 (Note 1) VCS+ = +3V, VCS- = 0V, ICSVCS- = +3V, VCS+ = 0V, ICS+ -250 0.5 -0.5 -0.5 5.2 +250 VVL - 0.5 A nA V A VDD = VVL VDD = VVL = 5V, VTIMER = 2.5V TIMER = GND, VDD = VVL = 5V VDD = 8V to 13.25V, IVL = 0A VL = VDD, rising threshold VL = VDD, falling threshold 3.80 2.78 2.68 3.0 1.8 1.6 4.1 2.82 2.75 5.5 3.0 3.0 4.45 2.90 2.82 V mA mA V V VTIMER = 2.5V VL unconnected VL = VDD 8.00 3.0 2.0 0.04 14.0 13.3 14.4 13.8 13.25 5.5 3.3 0.2 3.0 15.0 14.5 V mA mA V CONDITIONS MIN TYP MAX UNITS
VL unconnected, VTIMER = 2.5V, VDD = 13.25V VDD = VVL = 5V, VTIMER = 2.5V VTIMER = 0V, VDD = 13.25V Rising threshold Falling threshold
2
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.25V, RFAULT = 50k, CVDD = CGATE = CVL = 0.01F, TA = 0C to +85C, unless otherwise noted.)
PARAMETER TIMER TIMER Voltage TIMER Maximum Source Current TIMER High Input Current TIMER Maximum Frequency Select Voltage Input Range TIMER Logic High, VIH TIMER Logic Low, VIL FAULT Fault Output Low Voltage Fault Sink Current Fault Leakage Current GATE Gate-On Threshold Measured from CS- to CS+ VGATE = VCS+ = 2.5V Gate-Drive Current VGATE = VCS+ = 2.5V, VDD = VVL = 3V VGATE = VCS+ = 2.5V, VDD = VVL = 5V Gate Shutdown Delay Gate Discharge Current GATE Fall Time CURRENT SENSE Reverse-Current Threshold Startup IREV Blank Time Forward-Current Threshold Measured from CS- to CS+ TIMER = unconnected Measured from CS+ to CS6 MAX8555 MAX8555A 34 16 40 20 4.1 10 14 46 24 mV ms mV (Note 2) VGATE = VCS+= +5V Gate voltage fall from FAULT to VGATE = VCS+, R1 = 2, Figure 3 or Figure 4 MAX8555 MAX8555A RTIMER = open RTIMER = 25k RTIMER = open RTIMER = 25k RTIMER = open RTIMER = 25k VTIMER falling IREV fault 80 35 17 8 100 50 25 12 15 7.5 30 15 100 60 1000 0.2 200 150 ns mA s 120 65 33 16 A mV IFAULT = 10mA V FAULT = 0.4V V FAULT = 5.5V, TA = +25C 15 1 0.2 V mA A VTIMER = 1.0V VTIMER = 1.5V (Note 1) Charge pump enabled Charge pump disabled 1.5 1.0 0.5 1.22 85 1.25 100 10 1.28 115 15 VVL V A A V V V CONDITIONS MIN TYP MAX UNITS
MAX8555/MAX8555A
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.25V, RFAULT = 50k, CVDD = CGATE = CVL = 0.01F, TA = 0C to +85C, unless otherwise noted.)
PARAMETER OVERVOLTAGE PROTECTION OVP Fault Threshold, VOVP OVP Bias Current UNDERVOLTAGE PROTECTION UVP Fault Threshold, VUVP UVP Bias Current UVP rising UVP falling TA = +25C TA = +85C 0.003 0.488 0.5 0.4 0.1 0.512 V A OVP rising OVP falling TA = +25C TA = +85C 0.021 0.49 0.5 0.4 0.1 0.51 V A CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.25V, RFAULT = 50k, CVDD = CGATE = CVL = 0.01F, TA = -40C to +85C, unless otherwise noted.) (Note 3)
PARAMETER VDD SUPPLY VDD Input Voltage VDD Supply Current VDD Shutdown Current VDD Overvoltage Internal Threshold VL SUPPLY VL Input Voltage VL Supply Current VL Current in Shutdown Mode VL Output Voltage VL Undervoltage Lockout CS INPUTS Offset Input Current (CS+, CS-) CS+/CS- Input Range CHARGE-PUMP VOLTAGE GATE Voltage, VGATE Measured from GATE to CS+ VDD = 8V to 13.25V VDD = VVL = 5V 5.0 5.5 V VCS = 3.0V, Figure 4 (Note 1) -250 0.5 +250 VVL - 0.5 nA V VDD = VVL VDD = VVL = 5V, VTIMER = 2.5V TIMER = GND, VDD = VVL= 5V VDD = 8V to 13.25V, IVL = 0A VL = VDD, rising threshold VL = VDD, falling threshold 3.80 2.78 2.68 3.0 5.5 3.0 3.0 4.45 2.90 2.82 V mA mA V V VTIMER = 2.5V VL unconnected VL = VDD 8.00 3.0 13.25 5.5 3.3 0.2 3.0 14.0 13.3 15.0 14.5 V mA mA V CONDITIONS MIN TYP MAX UNITS
VL unconnected, VTIMER = 2.5V, VDD = 13.25V VDD = VVL = 5V, VTIMER = 2.5V VTIMER = 0V, VDD = 13.25V Rising threshold Falling threshold
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.25V, RFAULT = 50k, CVDD = CGATE = CVL = 0.01F, TA = -40C to +85C, unless otherwise noted.) (Note 3)
PARAMETER TIMER TIMER Voltage TIMER Maximum Source Current TIMER High Input Current TIMER Maximum Frequency Select Voltage Input Range TIMER Logic High, VIH TIMER Logic Low, VIL FAULT Fault Output Low Voltage Fault Sink Current GATE Gate-On Threshold Gate-Drive Current Gate Shutdown Delay CURRENT SENSE Reverse-Current Threshold Forward-Current Threshold OVERVOLTAGE PROTECTION OVP Fault Threshold, VOVP UNDERVOLTAGE PROTECTION UVP Fault Threshold, VUVP UVP rising 0.488 0.512 V OVP rising 0.49 0.51 V Measured from CS- to CS+ Measured from CS+ to CSMAX8555 MAX8555A 34 16 6 46 24 14 mV mV Measured from CS- to CS+ VGATE = VCS+ = 2.5V MAX8555 MAX8555A RTIMER = open RTIMER = 25k VTIMER falling IREV fault 80 35 17 8 120 65 33 16 200 150 mV A ns IFAULT = 10mA V FAULT = 0.4V 15 0.2 V mA VTIMER = 1.0V VTIMER = 1.5V (Note 1) Charge pump enabled Charge pump disabled 1.5 1.1 0.5 1.22 85 1.28 115 15 VVL V A A V V V CONDITIONS MIN TYP MAX UNITS
MAX8555/MAX8555A
Note 1: Guaranteed by design. Not production tested. Note 2: Gate shutdown delay is measured from reverse-current fault to the start of gate-voltage falling or from TIMER to the start of gate-voltage falling. Note 3: Specifications to -40C are guaranteed by design and not production tested.
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Typical Operating Characteristics
(VDD = 12V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.4V, RFAULT = 50k to output bus, CVDD = CGATE = CVL = 0.01F, TA = +25C, R1 = 2 in Figure 3, MAX8555A, unless otherwise noted.)
GATE-CHARGE CURRENT vs. TIMER RESISTOR (VDD = 12V)
MAX8555/55A toc01
GATE-CHARGE CURRENT vs. TIMER RESISTOR (VDD = VVL = 3V)
16 GATE-CHARGE CURRENT (A) 14 12 10 8 6 4 2 0 TA = +25C TA = -40C TA = +85C
MAX8555/55A toc02
VDD CURRENT vs. TEMPERATURE
MAX8555/55A toc03
25 20 GATE CURRENT (A)
TA = +85C
18
3.0 2.5 VDD CURRENT (mA) 2.0 1.5 1.0 0.5 0 VDD = 13.25V -40 -20 0 20 40 60 80 TIMER = OPEN
TA = -40C 15 10 5 0 -5 10 100 TIMER RESISTOR (k) TA = +25C
TIMER = GND
-2 1000 10 100 TIMER RESISTOR (k) 1000
TEMPERATURE (C)
REVERSE-CURRENT THRESHOLD vs. TEMPERATURE
MAX8555/55A toc04
OVP AND UVP LEAKAGE CURRENT vs. TEMPERATURE
45.0 40.0 LEAKAGE CURRENT (nA) 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0 UVP -40 -20 0 20 40 60 80 OVP
MAX8555/55A toc05
30.0 REVERSE-CURRENT THRESHOLD (mV) 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
50.0
TEMPERATURE (C)
POWER-UP WAVEFORMS BUS VOLTAGE HIGH IMPEDANCE
MAX8555/55A toc06
POWER-UP WAVEFORMS BUS VOLTAGE IS LIVE
MAX8555/55A toc07
1V/div VCS+ 5V/div VGATE VCS1V/div
VGATE
5V/div
VCS+
1V/div
VCS-
1V/div 500mA/div
1A/div IMOSFET 1ms/div
IMOSFET
2ms/div
6
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
Typical Operating Characteristics (continued)
(VDD = 12V, VCS+ = 1.5V, RTIMER = 25k, VUVP = 1V, VOVP = 0.4V, RFAULT = 50k to output bus, CVDD = CGATE = CVL = 0.01F, TA = +25C, R1 = 2 in Figure 3, MAX8555A, unless otherwise noted.)
POWER-UP AND DOWN WAVEFORMS USING TIMER
MAX8555/55A toc08
MAX8555/MAX8555A
REVERSE-CURRENT SHUTDOWN WAVEFORMS
MAX8555/55A toc09
VTIMER
2V/div
VGATE
5V/div
5V/div VGATE
VFAULT
1V/div
VCSIMOSFET
100mV/div 0A -2A
IMOSFET
1A/div
5ms/div
200ns/div
UVP SHUTDOWN WAVEFORMS
MAX8555/55A toc10
OVP SHUTDOWN WAVEFORMS
MAX8555/55A toc11
VFAULT
2V/div VOVP
2V/div
VGATE VCSAC-COUPLED VUVP
5V/div VCSAC-COUPLED 100mV/div 2V/div VGATE VFAULT 100mV/div 5V/div 1V/div
200ns/div
200ns/div
POWER-SUPPLY OUTPUT SHORT-CIRCUIT SHUTDOWN WAVEFORMS
MAX8555/55A toc12
VDD FAULT SHUTDOWN WAVEFORMS
MAX8555/55A toc13
5V/div VGATE1 VCS1V/div
VCS+ VCSAC-COUPLED
1V/div
VGATE VDD
5V/div
100mV/div
10V/div 1V/div
IMOSFET2
200mA/div
VFAULT
200ns/div
1s/div
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Pin Description
PIN 1 2 3 4 5 NAME GATE GND VL VDD UVP FUNCTION Gate-Drive Output. Nominal GATE load is a 0.01F capacitor to ground. Gate is discharged to GND in shutdown. Ground Low-Voltage Optional Input Power. Leave disconnected when VDD = 8V to 13.25V, or connect VDD to VL when VDD = 3V to 5.5V. Bypass VL to GND with a 0.01F capacitor. Power-Supply Input. Connect to an 8V to 13.25V supply or connect to VL when using a 3V to 5.5V supply. Bypass VDD with a 0.01F capacitor to ground. Undervoltage-Protection Input. Connect UVP to the center of a resistor-divider from CS+ to GND. Connect UVP to VL to disable the undervoltage protection. Timer Input. Connect a resistor from TIMER to GND to select the charge-pump operating frequency. Drive TIMER low (< 0.5V) to disable the gate drive. Drive TIMER high (above 1.5V) for charge-pump operation at 550kHz. Open-Drain Fault Output. FAULT is high impedance during normal operation and is pulled to GND when a fault condition occurs. Connect a pullup resistor of 10k or higher value (50k typ) to a voltage rail of 5.5V or lower. Overvoltage-Protection Input. Connect OVP to the center of a resistor-divider from the output bus to GND. Connect OVP to GND to disable the overvoltage protection. Current-Sensing Input. Connect CS- to the positive side of the system bus. Bypass with a 1000pF capacitor to GND. Current-Sensing Input. Connect CS+ to the positive side of the input power. Bypass with a 1000pF capacitor to GND.
6
TIMER
7
FAULT
8 9 10
OVP CSCS+
8
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
GATE
CS+
CS-
VL
CHARGE PUMP
100mV (50mV)
40mV (20mV)
10mV
CLK SHUTDOWN VL VOLTAGE SHARE REVERSE CURRENT FAULT CONTROL LOGIC FORWARD CURRENT OVERVOLTAGE INTERNAL OVERVOLTAGE EXTERNAL UNDERVOLTAGE 14.5V OVP
0.5V
IOSC TIMER 1.25V REF
ENABLE VL UVP
VL REGULATOR
0.4V
MAX8555/ (MAX8555A)
VDD GND VL
Figure 1. MAX8555/MAX8555A Functional Diagram
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
State Diagram
VCC > VCCOK ALL TRANSITIONS ARE ASYNCHRONOUS CSCS- + 10mV CS- - 40mV/20mV CS- - 100mV/50mV VSHARE LATCH SET CS+ TIMER > 1V IFORWARD IREVERSE 4.1ms STANDBY: CPMP: OFF GATE: LOW
WAIT FOR VSHARE
CS- - CS+ > 0.1V
VSHARE = ((CS-) - CS+) < 0.1V/0.05V IFORWARD = ((CS+) - CS-) > 0.01V IREVERSE = ((CS-) -CS+ ) > 40mV/20mV UVP FAULT UVP FAULT SHUTDOWN GATE FAULT NOT LATCHED UVP-OK
CS- - CS+ < 0.1V VCC OR TIMER CYCLED
ON: SET VSHARE LATCH, CHARGE PUMP ON
OVP OK AND IREVERSE DURING FIRST 4.1ms
IFORWARD and OVP Fault
FAULT SHUTDOWN GATE FAULT LATCHED
UVP = OK IREVERSE CONDITION DETECTED AFTER 4.1ms BLANK TIME VDD OR TIMER CYCLED FAULT SHUTDOWN GATE: FAULT LATCHED
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
General Description
Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The MAX8555/MAX8555A are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The MAX8555/MAX8555A are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to VCS+ + 5V. During startup, the MAX8555/MAX8555A monitor the voltage drop across the external MOSFETs. Once VCS+ approaches or exceeds the bus voltage (V CS-), the MOSFETs are turned on. The MAX8555/MAX8555A feature a dual-purpose TIMER input. A single external resistor from TIMER to ground sets the turn-on speed of the external MOSFETs. Optionally, the TIMER input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs' RDS(ON) , reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns.
TIMER
GATE is the output of the internal charge pump that drives the external MOSFETS. During startup, the voltage at GATE ramps up according to the charge-pump frequency. At 250kHz, the GATE drive current for the MAX8555/MAX8555A is 12A. Increasing the chargepump frequency increases the GATE drive current. To change charge-pump frequency, change the value of RTIMER. See the Selecting the TIMER Resistor section.
MAX8555/MAX8555A
CS+, CSThe voltage drop across the external MOSFETs is measured between the CS+ and CS- inputs. CS+ connects to the positive side of the input voltage. CS- connects to the positive side of the system bus. The MAX8555/ MAX8555A use the voltage drop across CS+ and CS- to determine operating mode. I FORWARD is defined as VCS+ - VCS- and must be greater than 0.01V (typ) to properly detect an overvoltage fault condition. IREVERSE is defined as VCS- - VCS+ and must be greater than 0.02V (MAX8555A) or 0.04V (MAX8555) (typ) for a reverse-current fault. The I FORWARD and I REVERSE thresholds can be effectively increased by placing an external divider such as R8 and R9 as shown in Figure 4. The values shown increase the thresholds by 50%. When R8 and R9 are used, also add R10 (a parallel combination of R8 and R9) to eliminate any input offset errors caused by impedance differences and input-bias-current differences.
Fault Conditions
The MAX8555/MAX8555A have an open-drain FAULT output that signals overvoltage, undervoltage, or reverse-current fault conditions. During a fault condition, FAULT is pulled to GND, the charge pump shuts down, and GATE discharges to CS- in 200ns (typ). See Table 1 for fault modes. Undervoltage Fault The MAX8555/MAX8555A turn off the external MOSFETs if VUVP falls below the UVP threshold (0.4V). Connect UVP to the center of a resistor-divider from the input supply to GND. Once VUVP rises above the UVP rising threshold (0.5V), FAULT clears and GATE is driven high. FAULT is not latched. Connect UVP to VL to disable the undervoltage-protection feature. Overvoltage Fault The MAX8555/MAX8555A are protected from overvoltage conditions using an adjustable overvoltage-protection input. A resistor-divider from the output bus to GND with OVP connected to the center tap sets the overvoltage threshold. When VOVP exceeds the OVP threshold (0.5V) and the device is in the I FORWARD condition
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VDD
V DD is the power-supply input for the MAX8555/ MAX8555A and the input to the internal preregulator. Bypass VDD to GND with a 0.01F capacitor. The input supply range for V DD is 8V to 13.25V. The internal charge pump is disabled for input voltages above 14.4V (typ). For 3V to 5.5V input voltages, connect VDD to VL.
VL
VL is the regulated power supply for the MAX8555/MAX8555A. The MAX8555/MAX8555A monitor VL at all times. During startup the device turns on when VL rises above VL OK (2.82V typ). After V VL exceeds VL OK and V CS+ is typically greater than (VCS- - 100mV), the charge pump turns on and drives GATE high, turning on the external MOSFETs. For operation from 3V to 5.5V input supplies, connect VL to VDD.
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Table 1. Fault Modes
FAULT MODE VL UVLO UVP Undervoltage Protection OVP Overvoltage Protection Reverse-Current Protection VDD Internal Overvoltage Protection VL < VLOK VUVP < 0.4V VOVP > 0.5V VCS+ > VCS- + 0.01V VCS+ < VCS- - 0.04V (0.02V for MAX8555A) and GATE is on for > 2048 charge-pump cycles VDD > 14.5V CONDITIONS GATE LOW LOW LOW LOW LOW FAULT High Impedance LOW LOW LOW LOW LATCHING NO NO YES YES NO
SYSTEM BUS R5 2.87k R2A 47k R2B 6.04k FAULT R2A 47k R2B 6.04k FAULT
R6 1k 150pF
Reverse-Current Fault The MAX8555/MAX8555A provide a reverse-current fault-protection feature that turns off the oring MOSFET when a reverse-current fault condition is detected. Once a reverse-current fault condition is detected, the MAX8555/MAX8555A discharge GATE to GND and latch FAULT low. Toggle VDD, VL, or TIMER to reset the IC. The reverse-current-protection feature is blanked for 2048 charge-pump cycles at startup.
150pF
Selecting the TIMER Resistor
Connect a resistor from TIMER to GND to set the internal charge pump's frequency of operation. Determine the TIMER resistor with the following equation:
OVP
OVP
R TIMER =
Figure 2. OVP Connection when Multiple MAX8555s Are Used
1.25V 100A - f 5kHz / A
(defined as V CS+ > V CS- + 0.01V), the MAX8555/ MAX8555A discharge GATE to GND and FAULT is latched low. If the IFORWARD condition is not detected, OVP is disabled. In redundant systems, when one input supply approaches its OVP threshold, some of the other input supplies may be pulled up with it, thereby tripping those OVP comparators with a slightly lower set point. The I FORWARD condition for the pulled-up supplies may not be detected until the first supply is shut down. An alternate application schematic for FAULT and OVP is shown in Figure 2. The FAULT output of the first channel, which has both OVP and IFORWARD conditions, temporarily reduces the common OVP signal by 125mV. This ensures that only the input supply, which is causing the overvoltage condition, is turned off in a redundant power-system application. Exceeding the OVP threshold causes the MAX8555/ MAX8555A to be latched off. Toggle VDD or TIMER to reset the IC. Connect OVP to GND to disable the overvoltage-protection feature.
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Drive TIMER above 1.5V for the maximum chargepump frequency (550kHz). Drive TIMER below 0.5V to disable the charge pump and shut down the MAX8555/ MAX8555A.
Selecting the GATE Capacitor and GATE Resistor
The charge pump uses an internal monolithic transfer capacitor to charge the external MOSFET gates. Normally, the external MOSFET's gate capacitance is sufficient to serve as a reservoir capacitor. To slow down turn-on times further, add a small capacitor between GATE and GND. Adding a small resistor between GATE and the gate of the Oring MOSFET reduces the high-frequency ringing due to gate trace inductance. However, the resistor increases the turn-off time.
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Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Applications Information
+VO Q1 OUT+ Q2 OUTPUT: 1.5V/20A -VO OUTPUT BUS R6 10k +VO OUTPUT: 1.5V/20A R10 665 C1 0.01F R1 2 C3 1000pF R5 15k R2 51k R6 10k OUTPUT BUS -VO
C1 1000pF R3 5k INPUT SUPPLY C4 0.01F
R1 2 GATE CS-
C3 1000pF R5 15k R2 51k
12V CS+ VL VDD UVP TIMER
FAULT
MAX8555/ MAX8555A
GND
OVP
R4 10k
C2 0.01F
R7 24.9k
OUT-
Figure 3. Application Circuit for 12V IC Supply Voltage
R8 1k
R9 2k Q1 Q2
OUT+
C4 1000pF R3 5k
INPUT SUPPLY
5V
CS+ VL VDD UVP TIMER
GATE
CS-
FAULT
MAX8555/ MAX8555A
GND
OVP
R4 10k
C2 0.01F
R7 24.9k
OUT-
Figure 4. Application Circuit for 5V IC Supply Voltage ______________________________________________________________________________________ 13
Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Set the UVP Fault Threshold
Use a resistor-divider from the input supply to GND with the center tap connected to UVP to set the undervoltage threshold. Use a 10k resistor from UVP to GND (R4 in Figure 4) and calculate R3 as follows: V R3 = R4 UV - 1 VUVP where VUV is the desired undervoltage trip point and VUVP is the UVP reference threshold (0.4V typ). Connect UVP to VL to disable the undervoltage-protection feature. Using Two MOSFETs Two MOSFETs must be used for overvoltage protection. When using two external MOSFETs, the monitored voltage equation becomes: VDSTOTAL = RDS(ON)1 x ILOAD + RDS(ON)2 x ILOAD Using One MOSFET A single MOSFET can be used if the overvoltage-protection function is not needed. Connect CS+ to the source of the MOSFET and CS- to the drain of the MOSFET.
Calculating GATE Current
The charge-pump output current is proportional to both oscillator frequency and VVL. There is also a small internal load of approximately 6M. The GATE current for a given VVL and RTIMER is calculated as: (V - 0.8) 12, 500 IGATE 24.12 x L x 1 - - 0.4 A 3.4 R TIMER
Set the OVP Fault Threshold
For a single-supply application, use a resistor-divider from the output bus to GND with the center tap connected to OVP to set the overvoltage threshold. Use a 10k resistor from OVP to GND (R6 in Figure 4) and calculate R5 as follows: V R5 = R6 OV - 1 VOVP where VOV is the desired overvoltage threshold and VOVP is the OVP reference threshold (0.5V typ). Connect OVP to GND to disable the overvoltage-protection feature. For (n + 1) applications, the required circuit values are: R6 = 1k V R5 = R6 x OV - 1 VOVP R2A = 47k R2B = 2 x R5 where the resistors are as shown in Figure 2.
Layout Guidelines
It is important to keep all traces as short as possible and to maximize the high-current trace dimensions to reduce the effect of undesirable parasitic inductance. The MOSFET dissipates a fair amount of heat due to the high currents involved, especially during an overcurrent condition. To dissipate the heat generated by the MOSFET, make the power traces very wide with a large amount of copper area and place the MAX8555 as close as possible to the drain of the external MOSFET. A more efficient way to achieve good power dissipation on a surface-mount package is to lay out two copper pads directly under the MOSFET package on both sides of the board. Use enlarged copper mounting pads on the top side of the board. Use a ground plane to minimize impedance and inductance. In addition to the usual high-power considerations, here are three tips to prevent false faults: 1) Kelvin connect CS+ and CS- to the external MOSFET and route the two traces in parallel, as close as possible, back to the IC. 2) Bypass VDD with a 0.01F capacitor to ground and bypass CS+ and CS- with a 1000pF capacitor to ground. 3) Make the traces connected to UVP and OVP as short as possible. Refer to the MAX8555/MAX8555A evaluation kit for an example of good PC board layout.
MOSFET Selection
The MAX8555/MAX8555A drive N-channel MOSFETs. The most important specification of the MOSFETs is RDS(ON). As load current flows through the external MOSFET, VDS is generated from source to drain due to the MOSFET's on-resistance, RDS(ON). The MAX8555/ MAX8555A monitor VDS of the MOSFETs at all times to determine the state of the monitored power supply. Selecting a MOSFET with a low RDS(ON) allows more current to flow through the MOSFETs before the MAX8555/MAX8555A detect reverse-current (IREVERSE) and forward-current (IFORWARD) conditions.
14
______________________________________________________________________________________
Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Typical Operating Circuit
+VO OUTPUT: 1.5V AT 20A OUT+ -VO OUTPUT BUS
INPUT SUPPLY
8V TO 13.25V
GATE CS+ VDD UVP VL TIMER
CS-
FAULT
MAX8555/ MAX8555A
GND
OVP
OUT-
Chip Information
TRANSISTOR COUNT: 2309 PROCESS: BiCMOS
______________________________________________________________________________________
15
Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
1 2
L D A A2
PIN 1 ID
D2
1
N
1
b
PIN 1 INDEX AREA
C0.35 [(N/2)-1] x e REF. e
E
DETAIL A
E2
A1
k
C L
C L
L e A e
L
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0137
D
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.500.10 1.500.10 1.500.10 E2 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.400.05 0.300.05 0.250.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0137
D
2 2
16
______________________________________________________________________________________
Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX8555/MAX8555A
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 D1 0.116 0.120 0.114 0.118 D2 0.116 E1 0.120 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b D1 A1
E2 c E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
10LUMAX.EPS

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