View MAX5940BESA_830498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2991; Rev 0; 10/03
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
General Description
The MAX5940A/MAX5940B provide complete interface function for a powered device (PD) to comply with the IEEE 802.3af standard in a power-over-ethernet system. MAX5940A/MAX5940B provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature power-mode undervoltage lockout (UVLO) with wide hysteresis, and power-good outputs. An integrated MOSFET provides PD isolation during detection and classification. The MAX5940A/MAX5940B guarantee a leakage current offset of less than 10A during the detection phase. A programmable current limit prevents high inrush current during power-on. The device features power-mode UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5940A provides an active-high (PGOOD) opendrain output and a fixed UVLO threshold. The MAX5940B provides both active-high (PGOOD) and active-low (PGOOD) outputs and has an adjustable UVLO threshold with the default value compliant to the 802.3af standard. The MAX5940A/MAX5940B are designed to work with or without an external diode bridge. The MAX5940A/MAX5940B are available in 8-pin SO packages and are rated over the extended temperature range of -40C to +85C.
Features
o Fully Integrated IEEE 802.3af-Compliant PD Interface o PD Detection and Programmable Classification Signatures o Less than 10A Leakage Current Offset During Detection o Integrated MOSFET For Isolation and Inrush Current Limiting o Gate Output Allows External Control of the Internal Isolation MOSFET o Programmable Inrush Current Control o Programmable Undervoltage Lockout (MAX5940B Only) o Wide UVLO Hysteresis Accommodates TwistedPair Cable Voltage Drop o PGOOD/PGOOD Outputs to Enable Downstream DC-DC Converters o -40C to +85C Operating Temperature Range
MAX5940A/MAX5940B
Ordering Information
PART MAX5940AESA MAX5940BESA TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 8 SO 8 SO UVLO Fixed Adjustable
Applications
IP Phones Wireless Access Nodes Computer Telephony
D1* GND
Security Cameras IEEE 802.3af Power Devices
Pin Configurations appear at end of data sheet.
Typical Operating Circuits
DC-DC CONVERTER
V+ GND 60V 68nF RDISC 25.5k 8 COUT
MAX5014
GND
VREG
2
RCLASS
RCL D2* -48V *OPTIONAL.
3
MAX5940A
GATE PGOOD 6
SS_SHDN
LOAD
4
VEE
OUT
5 CGATE
Typical Operating Circuits continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to VEE, unless otherwise noted.) GND........................................................................-0.3V to +80V OUT, PGOOD ...........................................-0.3V to (GND + 0.3V) RCLASS, GATE ......................................................-0.3V to +12V UVLO ........................................................................-0.3V to +8V PGOOD to OUT.........................................-0.3V to (GND + 0.3V) Maximum Input/Output Current (continuous) OUT to VEE ...................................................................500mA GND, RCLASS to VEE .....................................................70mA UVLO, PGOOD, PGOOD to VEE .....................................20mA GATE to VEE ....................................................................80mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.9mW/C above +70C)..................470mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER DETECTION MODE Input Offset Current (Note 2) Effective Differential Input Resistance (Note 3) CLASSIFICATION MODE Classification Current Turn-Off Threshold (Note 4) VTH,CLSS VIN rising Class 0, RCL = 10k Classification Current (Notes 5, 6) ICLASS VIN = 12.6V to Class 1, RCL = 732 20V, RDISC = Class 2, RCL = 392 25.5k Class 3, RCL = 255 Class 4, RCL = 178 POWER MODE Operating Supply Voltage Operating Supply Current Default Power Turn-On Voltage Default Power Turn-Off Voltage Default Power Turn-On/Off Hysteresis External UVLO Programming Range UVLO External Reference Voltage UVLO External Reference Voltage Hysteresis UVLO Bias Current VIN IIN VUVLO, ON VUVLO, OFF VHYST,
UVLO
SYMBOL IOFFSET dR
CONDITIONS VIN = 1.4V to 10.1V VIN = 1.4V up to 10.1V with 1V step, OUT = PGOOD = GND
MIN
TYP
MAX 10
UNITS A k
550
20.8 0 9.17 17.29 26.45 36.6
21.8
22.5 2 11.83 19.71 29.55 41.4 67
V
mA
VIN = (GND - VEE) Measure at GND, not including RDISC VIN increasing MAX5940A MAX5940B, UVLO = VEE 34.3 37.4 30 4.2 7.4 12 2.400 Ratio to VREF,UVLO UVLO = 2.460V 19.2 -1.5 2.460 20 0.4 35.4 38.6
V mA V V V
1 36.6 39.9
VIN decreasing, UVLO = VEE for MAX5940B MAX5940A MAX5940B, UVLO = VEE Set UVLO externally (MAX5940B only) (Note 7)
VIN,EX VREF, UVLO HYST IUVLO
67 2.522 20.9 +1.5
V V % A
2
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER UVLO Input Ground-Sense Threshold (Note 8) UVLO Input Ground-Sense Glitch Rejection Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time (Note 9) tOFF_DLY SYMBOL VTH,G,UVLO UVLO = VEE CONDITIONS MIN 50 7 TYP MAX 440 UNITS mV s
MAX5940A/MAX5940B
VIN, VUVLO falling TA = +25C (Note 10) TA = +85C
0.32
ms
Isolation Switch N-Channel MOSFET On-Resistance
RON
Output current = 300mA, VGATE = 6V, measured between OUT and VEE
0.6 0.8 0.5 38 5 5.59 1.16 10 5.76 1.23 70 4.62 4.76 80
1.1 1.5 V 80 15 5.93 1.31 A V V mV 4.91 V mV 0.4 1 1 V A A
Isolation Switch N-Channel MOSFET Off-Threshold Voltage GATE Pulldown Switch Resistance GATE Charging Current GATE High Voltage PGOOD, PGOOD Assertion VOUT Threshold PGOOD, PGOOD Assertion VGATE Threshold PGOOD, PGOOD Output Low Voltage (Note 11) PGOOD Leakage Current (Note 11) PGOOD Leakage Current (Note 11)
VGSTH RG IG VGATE VOUTEN
OUT = GND, VGATE - VEE, output current < 1A Power-off mode, VIN = 12V, UVLO = VEE for MAX5940B VGATE = 2V IGATE = 1A VOUT - VEE, |VOUT - VEE| decreasing, VGATE = 5.75V Hysteresis (GATE - VEE) increasing, OUT = VEE Hysteresis ISINK = 2mA; for PGOOD, OUT (GND - 5V) GATE = high, GND - VOUT = 67V GATE = VEE, PGOOD - VEE = 67V
VGSEN VOLDCDC
Note 1: All min/max limits are production tested at +85C. Limits at +25C and -40C are guaranteed by design. Note 2: The input offset current is illustrated in Figure 1. Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external resistance. See Figure 1. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be 1%, 100ppm or better. ICLASS includes the IC bias current and the current drawn by RDISC. Note 6: See the Thermal Dissipation section for details. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k (1%), the turnon threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage (MAX5940B only). Note 8: When the UVLO input voltage is below VTH,G,UVLO, the MAX5940B sets the UVLO threshold internally. Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the MAX5940A/MAX5940B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: Guaranteed by design. Note 11: PGOOD references to OUT while PGOOD references to VEE. _______________________________________________________________________________________ 3
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
IIN dRi 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) VINi dRi
IOFFSET IINi IINi + 1 IINi
dRi
IOFFSET VINi 1V VINi + 1 VIN
Figure1 . Effective Differential Input Resistance/Offset Current
Typical Operating Characteristics
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA = -40C to +85C. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.)
DETECTION CURRENT vs. INPUT VOLTAGE
MAX5940A/B toc01
CLASSIFICATION CURRENT vs. INPUT VOLTAGE
MAX5940A/B toc02
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE vs. INPUT VOLTAGE
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (M)
MAX5940A/B toc03
0.5 RDISC = 25.5k DETECTION CURRENT (mA) 0.4
50 CLASSIFICATION CURRENT (mA)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10
40
CLASS 4
0.3
IIN + IRDISC
30
CLASS 3 CLASS 2 CLASS 1 CLASS 0
0.2
20
0.1
10
0 0 2 4 6 8 10 INPUT VOLTAGE (V)
0 0 5 10 15 20 25 30 INPUT VOLTAGE (V)
12
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT vs. INPUT VOLTAGE
MAX5940A/B toc04
NORMALIZED UVLO vs. TEMPERATURE
1.008 1.006 NORMALIZED UVLO 1.004 VPGOOD (mV) 1.002 1.000 0.998 0.996 0.994 50 150 UVLO = VEE
MAX5940A/B toc05
PGOOD OUTPUT LOW VOLTAGE vs. CURRENT
MAX5940A/B toc06
0 -0.5 INPUT OFFSET CURRENT (A) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 1 3 5 7 9
1.010
250
200
100
0.992 0.990 11 -40 -15 10 35 60 85 INPUT VOLTAGE (V) TEMPERATURE (C) 0 0 5 10 ISINK (mA) 15 20
4
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA = -40C to +85C. Typical values are at TA = +25C. All voltages are referenced to VEE, unless otherwise noted.)
PGOOD OUTPUT LOW VOLTAGE vs. CURRENT
MAX5940A/B toc07
MAX5940A/MAX5940B
OUT LEAKAGE CURRENT vs. TEMPERATURE
VOUT = 67V OUT LEAKAGE CURRENT (nA) 16
MAX5940A/B toc08
INRUSH CURRENT CONTROL (VIN = 12V)
MAX5940A/B toc09
400
20
320 VPGOOD (mV)
VGATE 5V/div
240
12
IINRUSH 100mA/div VOUT TO VEE 10V/div
PGOOD
160
8
80
4 10V/div
0 0 5 10 ISINK (mA) 15 20
0 -40 -15 10 35 60 85 1ms/div TEMPERATURE (C)
INRUSH CURRENT CONTROL (VIN = 48V)
MAX5940A/B toc10
INRUSH CURRENT CONTROL (VIN = 67V)
MAX5940A/B toc11
VGATE 5V/div
VGATE 5V/div
IINRUSH 100mA/div VOUT TO VEE 50V/div
IINRUSH 100mA/div VOUT TO VEE 50V/div
PGOOD
PGOOD
50V/div 2ms/div 2ms/div
50V/div
_______________________________________________________________________________________
5
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Pin Description
PIN MAX5940A MAX5940B 1, 7 -- NAME N.C. No Connection. Not internally connected. Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its threshold, the device enters power mode. Connect UVLO to VEE to use the default undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series resistance value of the external resistors must add to 25.5k (1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull UVLO to between VTH,G,UVLO and VREF,UVLO. Classification Setting. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1 and 2). Gate of Internal N-Channel Power MOSFET. GATE sources 10A when the device enters power mode. Connect an external 100V ceramic capacitor (CGATE) from GATE to OUT to program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions operate normally when GATE is pulled to VEE. Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect VEE to -48V. Output Voltage. Drain of the integrated isolation N-channel power MOSFET. Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND). Connect PGOOD to the ON pin of a downstream DC-DC converter. Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream DC-DC converter. Ground. GND is the positive input terminal. FUNCTION
--
1
UVLO
2
2
RCLASS
3
3
GATE
4 5
4 5
VEE OUT
6
6
PGOOD
--
7
PGOOD
8
8
GND
Detailed Description
Operating Modes
The PD front-end section of the MAX5940A/MAX5940B operates in 3 different modes, PD detection signature, PD classification, and PD power, depending on its input voltage (VIN = GND - VEE). All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 802.3af standard (see Figure 4). Detection Mode (1.4V VIN 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum), and then records the current measurements at the two points. The PSE then computes V/I to ensure the presence of the 25.5k signature resistor. In this mode, most of the MAX5940A/
6
MAX5940B internal circuitry is off and the offset current is less than 10A. If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal damage to the MAX5940A/MAX5940B (see the Typical Application Circuits). Since the PSE uses a slope technique (V/I) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V VIN 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different classes as shown in Table 1. An external resistor (RCL) connected from RCLASS to VEE sets the classification current.
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Table 1. PD Power Classification/RCL Selection
CLASS 0 1 2 3 4 USAGE Default Optional Optional Optional Not Allowed RCL () 10k 732 392 255 178 MAXIMUM POWER USED BY PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 Reserved*
*Class 4 reserved for future use.
Table 2. Setting Classification Current
CLASS 0 1 2 3 4 RCL () 10k 732 392 255 178 VIN* (V) 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 CLASS CURRENT SEEN AT VIN (mA) MIN 0 9.17 17.29 26.45 36.6 MAX 2 11.83 19.71 29.55 41.4 IEEE 802.3af PD CLASSIFICATION CURRENT SPECIFICATION (mA) MIIN 0 9 17 26 36 MAX 4 12 20 30 44
*VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5940A/MAX5940B exhibit a current characteristic with values indicated in Table 2. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 25.5k detection signature resistor and the supply current of the MAX5940A/MAX5940B so the total current drawn by the PD is within the IEEE 802.3af standard figures. The classification current is turned off whenever the device is in power mode. Power Mode During power mode, when VIN rises above the undervoltage lockout threshold (V UVLO,ON ), the MAX5940A/ MAX5940B gradually turn on the internal N-channel MOSFET Q1 (see Figure 2). The MAX5940A/MAX5940B charge the gate of Q1 with a constant current source (10A, typ). The drain-to-gate capacitance of Q1 limits the voltage rise rate at the drain of the MOSFET, thereby
limiting the inrush current. To reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current section). When the drain of Q1 is within 1.2V of its source voltage and its gate-to-source voltage is above 5V, the MAX5940A/MAX5940B asserts the PGOOD/PGOOD outputs. The MAX5940A/MAX5940B have a wide UVLO hysteresis and turn-off deglitch time to compensate for the high impedance of the twistedpair cable.
Undervoltage Lockout
The MAX5940A/MAX5940B operate up to a 67V supply voltage with a default UVLO turn-on (VUVLO,ON) set at 35V (MAX5940A) or 39V (MAX5940B) and a UVLO turnoff (VUVLO,OFF) set at 30V. The MAX5940B has an adjustable UVLO threshold using a resistor-divider connected to UVLO (see Figure 3). When the input voltage is above the UVLO threshold, the IC is in power mode and the MOSFET is on. When the input voltage goes below the UVLO threshold for more than tOFF_DLY, the MOSFET turns off.
_______________________________________________________________________________________
7
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
GND 2.46V UVLO GND R1 (PGOOD) REF EN CLASSIFICATION 6.8V RCLASS
MAX5940B
R2 20%
Q4
R3 VGATE EN 1.2V, REF PGOOD 5V, REF Q3
(UVLO)
200mV GATE
Q2 Q1
OUT
( ) MAX5940B.
VEE
Figure 2. Block Diagram
To adjust the UVLO threshold (MAX5940B only), connect an external resistor-divider from GND to UVLO and from UVLO to VEE. Use the following equations to calculate R1 and R2 for a desired UVLO threshold: R2 = 25.5k x VREF,UVLO VIN,EX
VIN = 12V TO 67V
GND R1
R1 = 25.5k - R2 where VIN,EX is the desired UVLO threshold. Since the resistor-divider replaces the 25.5k PD detection resistor, ensure that the sum of R1 and R2 equals 25.5k 1%. When using the external resistor-divider, the MAX5940B has an external reference voltage hysteresis of 20% (typ). When UVLO is programmed externally, the turn-off threshold is 80% (typ) of the new UVLO threshold.
UVLO
MAX5940B
R2 VEE
Figure 3. Setting Undervoltage Lockout with an External Resistor-Divider 8 _______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
Inrush Current Limit
The MAX5940A/MAX5940B charge the gate of the internal MOSFET with a constant current source (10A, typ). The drain-to-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from GATE to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current: IINRUSH = IG x COUT CGATE (MAX5940B only) PGOOD is an open-drain, active-low logic output. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream DC-DC converter. Connect a 100k pullup resistor from PGOOD to GND if needed.
MAX5940A/MAX5940B
Thermal Dissipation
During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from GND to VRCLASS will be 13V. If the maximum classification current of 42mA flows through the MAX5940A/ MAX5940B, then the maximum DC power dissipation will be 546mW, which is slightly higher than the maximum DC power dissipation of the IC at maximum operating temperature. However, according to the IEEE 802.3af standard, the duration of the classification mode is limited to 75ms (max). The MAX5940A/MAX5940B handle the maximum classification power dissipation for the maximum duration time without sustaining any internal damage. If the PSE violates the IEEE 802.3af standard by exceeding the 75ms maximum classification duration, it may cause internal damage to the IC.
PGOOD/PGOOD Outputs
(MAX5940A/MAX5940B) PGOOD is an open-drain, active-high logic output. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled to VOUT (given that VOUT is at least 5V below GND). Connect PGOOD to the ON pin of a downstream DC-DC converter. Connect a 100k pullup resistor from PGOOD to GND if needed.
_______________________________________________________________________________________
9
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Typical Application Circuits
Application Circuit 1
POWER-OVER SIGNAL PAIRS 3 6 1 2 RX
VREG
PHY GND
+
RJ-45
+ -
4 5 7 8 TX
-48V
POWER-OVER SPAIR PAIRS
DC-DC CONVERTER
GND RDISC 25.5k R1*
1
V+
UVLO
GND
8
COUT
MAX5014
VREG
60V
68nF
2
RCLASS
PGOOD
7 GND SS_SHDN LOAD 6
R2*
RCL
3 GATE
MAX5940B
PGOOD
-48V
4 VEE
OUT
5 CGATE
*R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE THE 25.5k RESISTOR.
Figure 4. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs)
10
______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Typical Application Circuits (continued)
Application Circuit 2
Diode D1 prevents the power-over-ethernet to back drive the wall adapter. Whenever the wall adapter power is available, the GATE is pulled low to pinch off the power-over-ethernet. R3 provides the GATE current flow path. The wall adapter power pollutes the discovery signature, preventing PSE from detecting this PD.
DC-DC CONVERTER
GND
V+
RDISC 25.5k 60V 68nF
1
UVLO
GND
8 R3 10k
COUT
MAX5014
VREG
2
RCLASS
PGOOD
7 GND SS_SHDN 6 LOAD
RCL
3 GATE
MAX5940B
PGOOD
-48V WALL ADAPTER SUPPLY
4 VEE
OUT
5 CGATE
D1
Figure 5. Adding Wall Adapter Input Supply (Wall Adapter Supply Takes Precedence Over Power-Over-Ethernet)
______________________________________________________________________________________
11
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Typical Application Circuits (continued)
Application Circuit 3
D2 prevents the wall adapter power from polluting the discovery and classification signatures. The optional R4 provides the 10mA minimum power maintenance signature to keep the power-over-ethernet from disconnecting.
DC-DC CONVERTER
D2 GND V+
RDISC 25.5k 60V 68nF
1
UVLO
GND
8
VREG R4 4k 2W COUT
MAX5014
2
RCLASS
PGOOD
7 GND SS_SHDN
RCL
3 GATE
MAX5940B
PGOOD
LOAD
6
-48V
4 VEE
OUT
5 CGATE
WALL ADAPTER SUPPLY
D1
Figure 6. Adding Wall Adapter Input Supply (Wall Adapter Supply And Power-Over-Ethernet Co-Exist, the One with Higher Voltage Provides Power To The Load)
12
______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
Typical Application Circuits (continued)
Application Circuit 4
If the wall adapter supply comes up first, it provides power to the load and pollute the discovery and classification signatures. If the power-over-ethernet comes up first, it powers the load until taken over by a wall adapter with higher output voltage.
MAX5940A/MAX5940B
DC-DC CONVERTER
GND
V+
RDISC 25.5k 60V 68nF
1
UVLO
GND
8
COUT
VREG
MAX5014
2
RCLASS
PGOOD
7 GND SS_SHDN
RCL
3 GATE
MAX5940B
PGOOD
LOAD
6
-48V
4 VEE
OUT
5 CGATE
WALL ADAPTER SUPPLY
D1
Figure 7. Adding Wall Adapter Input Supply (the One with Higher Voltage Provides Power to the Load)
______________________________________________________________________________________
13
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet MAX5940A/MAX5940B
Typical Operating Circuits (continued)
D1* GND RDISC 25.5k
DC-DC CONVERTER V+ R1** VREG
1
60V 68nF
UVLO RCLASS GATE
GND PGOOD
8 7 6
COUT
MAX5014
GND
2 3
SS_SHDN
LOAD
R2** D2* -48V
RCL
MAX5940B
PGOOD
4
VEE
OUT
5 CGATE
*OPTIONAL. **R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE THE 25.5k RESISTOR.
Pin Configurations
TOP VIEW
N.C. RCLASS GATE 1 2 8 7 GND N.C. PGOOD OUT
Chip Information
TRANSISTOR COUNT: 3,643 PROCESS: BiCMOS
MAX5940A
3 6 5 VEE 4
SO
UVLO RCLASS GATE 1 2 8 7 GND PGOOD PGOOD OUT
MAX5940B
3 6 5 VEE 4
SO
14
______________________________________________________________________________________
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOICN .EPS
MAX5940A/MAX5940B
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX5940BESA

	To Download MAX5940BESA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .