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| Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing CMOS Image Sensor with Image Signal Processing HV7161SPA2 1.3 Mega Pixel CIS (15fps@MCLK 21MHz, PLL 2x) Preliminary V3.0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -12005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Revision History Revision V0.0 V0.1 V0.2 Script Date 2003/11/19/Wed. 2004/03/19/Fri. 2004/04/01/Wed. Comments 1.3Mega Pixel CIS Preliminary is released Some descriptions are corrected Some PLL registers are changed. Some descriptions are simplified. Pin diagram is corrected and some analog registers are removed. Frame timing and integration time are corrected. Window mode and image size are corrected. Fixed frame rate PCTRB, Anti-Banding Mode 1st full revision Device ID, Focus value, window mode, and image size CLCC Package Drawing added AWB Red/Blue Gain Maximum/Minimum Value Typical application, pin description, and pin function Some register bits corrected and video mode setting modified. Bayer 11bit enable(OUTFMT[31h]) * Output data according to video mode (page 54) * Pin diagram(symbol VDD:P and VDD:PH), * AC/DC characteristics (symbol and typical voltage condition), and electro-optical characteristics (description) changed. QCIF mode removed. * All 2.5V power supplies are changed to '2.5V to 2.8V'. DC Operating Conditions, Electro-Optical Characteristics and Condition 2nd full revision Noise filter, Focal value generator, Contrast, Digital controlled analog gain calibration, and QCIF V0.3 V0.4 V0.5 V0.6 V0.7 V2.0 V2.1 V2.2 V2.3 V2.4 2004/04/06/Tue. 2004/04/23/Fri. 2004/06/03/Thu. 2004/07/20/Tue. 2004/08/06/Fri. 2004/08/12/Thu. 2004/08/27/Fri. 2004/09/17/Fri. 2004/09/20/Mon. 2004/10/25/Tue. V2.5 2004/12/23/Thu. V2.6 2005/01/04/Tue. V3.0 2005/01/20/Thu. Copyright by MagnaChip Semiconductor Ltd., all right reserved 2005 Disclaimer This document has general product descriptions and is subject to change without any notice. MagnaChip Semiconductor Ltd., assumes no responsibility on using of circuit described. Also, no patent licenses are implied. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -22005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Contents General Description......................................................................................................................................4 Features.......................................................................................................................................................4 Block Diagram .............................................................................................................................................5 Pin Diagram .................................................................................................................................................6 Pin Description.............................................................................................................................................6 Functional Description................................................................................................................................ 10 Pixel Architecture.................................................................................................................. 11 Sensor Imaging Operation..................................................................................................... 11 Correlated Double Sampling and Programmable Gain Amplifier ........................................... 12 On-chip ADC......................................................................................................................... 12 Dark Noise Cancellation........................................................................................................ 12 Gamma Correction................................................................................................................ 12 Color Interpolation................................................................................................................. 13 Color Correction.................................................................................................................... 13 Color Space Conversion ....................................................................................................... 14 Output Formatter................................................................................................................... 14 Auto Exposure Control .......................................................................................................... 14 Auto White Balance Control .................................................................................................. 14 On-chip frequency synthesizer .............................................................................................. 15 Luminance processing........................................................................................................... 15 Chrominance processing....................................................................................................... 15 Edge enhancement ............................................................................................................... 16 Special image functions ........................................................................................................ 16 Anti-Banding Configuration......................................................................................................................... 17 Register Description ................................................................................................................................... 18 Data Output Timing and Interface............................................................................................................... 56 Output Data according to Video Mode ........................................................................................................ 57 Bayer Data Format..................................................................................................................................... 64 Window mode and image size.................................................................................................................... 65 I2C Chip Interface ...................................................................................................................................... 66 AC/DC Characteristics................................................................................................................................ 67 Electro-Optical Characteristics ................................................................................................................... 70 Electro-Optical Test Condition .................................................................................................................... 70 Typical Application ..................................................................................................................................... 71 CLCC Package Specification ...................................................................................................................... 72 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -32005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing General Description 1.3Mega pixel CIS is a highly integrated single chip CMOS color image sensor implemented by proprietary MagnaChip 0.18um CMOS sensor process realizing high sensitivity and wide dynamic range. Total active pixel array is 1.3Mega size. Each active pixel composed of 4 transistors has a micro-lens to enhance sensitivity, and converts photon energy to analog pixel voltage. On-chip 11bit Analog to Digital Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. The integration of sensor function and image processing functions make 1.3Mega pixel CIS especially very suitable for mobile imaging systems such as digital still camera, PC input camera and IMT-2000 phone's video part that requires very low power and system compactness. Features Optical format 1/3.7 inch Total pixel array 1298 x 982 Active window pixel array 1280 x 960 Optical black array Upper: 2-line, Lower: 2-line Pixel size 3.2m x 3.2m Color filter array RGB mosaic Micro-lens for high sensitivity and on-chip 11 bit ADC Correlated double sampling (CDS) for reduction of Fixed Pattern Noise (FPN) Auto Black Level Compensation (ABLC) for reduction of the dark signal Gamma correction by programmable piecewise linear approximation Optimized color interpolation, false color suppression, and edge enhancement Adaptive random noise filter Color correction by programmable 3x3 matrix operation Color space conversion from RGB to YCbCr or YUV Sub-sampling modes : 1/4(VGA), 1/16(QVGA), 4CIF, CIF, and QCIF Various output formats: CCIR-601, CCIR-656 Compatible YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, RGB5:6:5 8bit and 11bit Bayer raw 8bit/16bit Data Bus Mode Support fixed-frame rate mode and single shot mode Automatic Exposure control(AE) and Automatic White Balance control(AWB) Special image functions: hue, saturation, brightness, contrast, negative, sepia, gray, and mono. Focus value generation from image information for supporting auto focus function Hard and soft power save mode Typical supply voltage: Internal 1.8V and 2.5V to 2.8V, and I/O 2.5V to 2.8V Operation Temperature : -10 ~ +50 degrees Celsius Package Types: CLCC 48 PIN, COB(Chip-on-Board), COF(Chip-on-Flex) Internal wide-range PLL Frame Rate: 15fps at MCLK 21MHz and PLL 2x mode, or fixed frame rate supported. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -42005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Total power consumption : about 73mW Pixel Array Structure 0123 973 . *** *** 1297 * * BG GR BG BG GR BG * * * . Addressable Pixel Array 1298(H) X 974(V) (Top view) G B G B R G R G G B G B R G R G G B G B R G R G 2 1 0 GR BG Block Diagram Sensor Core RGB Processing Color Space Conversion Y Processing C Processing Output Data Format Sensor Timing Generator PLL Measurement Engine (AE, AWB) SRAM STROBE RESETB VSYNC HSYNC MCLK This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -52005 MagnaChip Semiconductor Ltd. VCLK Y[7:0] C[7:0] ENB SDA SCK Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Pin Diagram (CLCC 48LD) Y] [5 Y] [4 Y] [3 Y] [2 Y] [1 Y] [0 6 Y] [7 Y] [6 5 4 3 2 1 48 47 GND:G VDD:P VDD:P GND:G C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0] 7 41 8 GND:G VDD:PH MCLK VCLK HSYNC VSYNC VDD:P GND:G 9 40 10 39 11 38 12 1.3 Mega Pixel CIS CLCC 48 PIN Top View 37 36 13 14 15 32 16 17 31 18 21 22 23 24 25 26 27 28 29 30 Pin Description (CLCC 48LD) C[7:0] should be set up as pull-up or pull-down when 8bit output mode is used. VD H D :P GD N :G SA D SK C SRB TOE RST EEB EB N VD D :P VD H D :P GD N :G Pin 47-48, 1-6 7 8 9 10 11-18 21 22 23 24 25 26 27 Type B G P P G O PH G B I O I I Symbol Y[7:0] DGNDI DVDDI DVDDC DGNDC C[7:0] DVDDIH DGNDIH SDA SCK STROBE RESETB ENB Description Video luminance data Digital ground for I/O driver 1.8V digital power for I/O driver 1.8V power for internal digital block Ground for internal digital block Video chrominance data 2.5V to 2.8V digital power for I/O driver Digital ground for I/O Driver I2C standard data I/O port I2C clock input Strobe signal output Sensor reset. Active low Sensor sleep mode is controlled externally by this pin when This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -62005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 28 29 30 31 32 36 37 38 39 40 41 G P PH G P O O O I PH G DGNDI DVDDI AVDDPH AGNDC AVDDC VSYNC HSYNC VCLK MCLK DVDDIH DGNDI sleep mode register bit SCTRB[4] is low. ENB low : sleep mode, ENB high : normal mode Digital ground for I/O driver 1.8V digital power for I/O driver 2.5V to 2.8V analog power for pixel block Analog ground for analog block 1.8V analog power for analog block Video frame synchronization signal. VSYNC is active at start of image data frame. Video horizontal line synchronization signal. Image data is valid, when HSYNC is high. Video output clock Master input clock 2.5V to 2.8V digital power for I/O driver Digital ground for I/O driver Pins 19-20, 33-35, 42-46 are not connected. Pin function: B - CMOS Schmitt trigger, non-inverted, tri-state bidirectional buffer, 4mA drive I - CMOS Schmitt trigger level non-inverting input O - Tri-state non-inverting output, 4mA drive (VCLK - 8mA drive) PH - 2.5V to 2.8V I/O or pixel power, P - 1.8V digital or analog power G - Universal ground This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -72005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Pin Function System power supply DVDDC 1.8V power supply for the internal digital circuit. AVDDC 1.8V power supply for the internal analog circuit. Separate properly from digital power, I/O power and signals. DVDDI 1.8V I/O power supply for the input/output/bidirectional pad. AVDDPH 2.5V to 2.8V power supply for the internal pixel array. Separate properly from digital power, I/O power and signals. DVDDIH 2.5V to 2.8V power supply for the input/output/bidirectional pad. Note : Attach a bypass capacitor near each power pin. System ground DGNDC 1.8V ground for the internal digital circuit. AGNDC 1.8V or 2.5V to 2.8V ground for the internal analog circuit. Separate properly from digital power, I/O power and signals. DGNDI 1.8V ground for the input/output/bidirectional pad. DGNDIH 2.5V to 2.8V ground for the input/output/bidirectional pad. Input pins RESETB When RESETB pin is an active low input, an external reset is generated. And all internal registers are initialized and are loaded by each default value. It is required that reset period is holding for more than 4 MCLK clocks when ENB pin is high level. Shorter period is not guaranteed to produce a reset scheme and make a sensor be unstably operated. Active low RESETB pin generates all output pins except VCLK pin to low level. VCLK pin is not affected to RESETB pin. ENB When ENB pin is an active high input, all functions of a sensor can be normally operated and so all output data are valid. If ENB pin is a low level, a sensor enters into a sleep mode and all functions are suspended. And all output pins hold each previous value. Sleep mode register SCTRB[4] bit means a soft-power down and ENB pin means a hard-power down. After RESETB pin is changed from a low to a high level, pin should be changed from a low to a high level. At the external (ENB) power-down mode, all output and bidirectional pins have a state of Hi-Z (high impedance). In addition to power-down mode, Y[7:0] and C[7:0] pins have a state of Hi-Z during HSYNC pin is low level. To minimize a power consumption at the external hard power-down mode ENB pin), the sensor's main power should be turned off together. MCLK MCLK pin is a master clock of sensor and determines maximum frame rate. This pin generates video clock (VCLK) and is supplied from an external clock oscillator. Between the external clock oscillator and MCLK pin should be as near as possible. SCK SCK is an input pin to be supplied I2C bus clock from master device and sensor get to be a slave device. SCK clock frequency is able up to maximum ENB (by This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -82005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 400KHz. With SDA pin, SCK timing should satisfy the standard I2C bus timing. Output pins Y[7:0] Video luminance output is available only when VSYNC and HSYNC is active state, which VSYNC is low and HSYNC is high level. Data output is generated sequentially whenever VCLK is triggered from low to high level. So, you must capture the image data whenever VCLK is triggered from high to low level. If HSYNC is got to inactive state, each Y pin generates high-impedance output - necessary when an imaging system including sensor uses the common-bus mode. The first image data is normally BLUE color in the case of Bayer output mode, and LUMINANCE, YCbCr output mode. In power-down mode, Y[7:0] pins have a state of Hi-Z during HSYNC pin is low level. C[7:0] With data bus mode set to RGB 4:4:4-16bit output or YCbCr 4:4:416bit output, video chrominance output is available only when VSYNC and HSYNC is active state, that VSYNC is low and HSYNC is high level (Otherwise, with 8bit data output mode, C pin always goes to high-impedance output mode). Data output is generated sequentially whenever VCLK is triggered from low to high level. So, you must capture the image data whenever VCLK is triggered from high to low level. If HSYNC is got to inactive state, each Y pin generates high-impedance output - necessary when an imaging system including sensor uses the common-bus mode. In power-down mode, C[7:0] pins have a state of Hi-Z during HSYNC pin is low level. VCLK Video clock is always generated while sensor is being active operation. When HSYNC is active high, video clock has pulse count as a pixel amount corresponding to 1-line of specific image window. Data output is generated sequentially whenever VCLK is triggered from low to high level. So, you must capture the image data whenever VCLK is triggered from high to low level. When VSYNC is low and HSYNC is high level, total VCLK pulse count is equal to a total pixel amount of specific image window. Note : With OUTINV[0] set to '1', valid data is generated when VCLK is trigged from high to low level, and you can capture the image data when VCLK is trigged from low to high level. HSYNC Image data is valid, when HSYNC is high VSYNC VSYNC is active at start of image data frame. STROBE Though sensor has enough integration time to capture image, sensor can't obtain good image quality in dark environment. For this situation, sensor can generate strobe signal for driving external strobe circuit. The strobe output is active high when integration time is over than core frame time((Video Height Time + 1) X (Video Width Time + HBLANK)). Because sensor uses progressive exposure method, strobe signal should cover all line(all pixels). Note : If a sensor is got into hard or soft sleep mode, all output pins generate highimpedance output - necessary when an imaging system including sensor uses the common-bus mode. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -92005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Bi-directional SDA SDA is the Serial Data line. The data on the SDA line must be stable during the HIGH period of the SCK clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCK line is LOW. Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. Functional Description Reset sequence Internal power -on reset (POR) Sensor resets automatically by internal power-on reset circuit when power is supplied, and after 1 frame operation is done, all reset sequence is terminated as all internal registers are loaded to each default value, and sensor is stable. Therefore, image capturing or chip configuring should be executed on 1 frame time later from power-on. External reset When RESETB pin goes from high to low level, initialization is begun. After 1 frame operation is done, all reset sequence is terminated as all internal registers are loaded to each default value, and sensor is stable. Therefore, image capturing or chip configuring should be executed on 1 frame time later from external reset. We recommend initializing sensor by using RESETB pin before operating it. The condition to reset sensor follow, 1. MCLK is being supplied to sensor. 2. ENB pin is holding '1' and RESETB pin is '1'. 3. RESETB pin have to be keep '0' during minimum 4MCLK periods. 4. After RESETB pin set to '1' and 1 frame time is gone, reset sequence is terminated. Power-down mode Internal soft power-down For entering into soft power-down mode, set SCTRB[4] to '1'. In this mode, all internal digital and analog blocks go into an inactive mode(soft sleep), and power This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 10 2005 MagnaChip Semiconductor Ltd. ! 1 4 ' ! ( ' & % 2 1 3 2 1 0) ( ' & % ! $ (c) "#! | (c) Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing consumption is decreased considerably. Note: You should set the integration time to multiple of AE-Step before waking power-down mode. This is because the default integration time and integration scan offset are set to multiples of 50Hz. If you leave out Integration time setting step, the banding under fluorescent light will be occurred even though other AE related registers are set appropriately. The setting order is follow, 1. Enter into the soft power-down mode. 2. Set the AE step (minimum frame rate). 3. Set the integration time to 4 times of AE step. 4. Wake the soft power-down mode. External hard power-down During ENB pin is '0', sensor goes to a deep-sleep mode(hard power-down mode) and all sensor operation is stopped. Also power consumption is minimized dramatically. After ENB pin goes from low to high level and 1 frame operation is done, sensor operation is stable and you can capture image data and configure each specific register. The sensor reset and hard power-down scheme follows, UUU ' 2 1 %3 0 (& 1 )' % $# %' 54 " 2 ' 2 1 %3 # !" Note: In the internal(I2C control) or external(ENB) power-down mode, all output and bidirectional pins have a state of Hi-Z(high impedance). In addition to power-down mode, Y[7:0] and C[7:0] pins have a state of Hi-Z during HSYNC pin is low level. Note: To minimize a power consumption at the external hard power-down mode(by ENB pin), the sensor's main power should be turned off together. Pixel Architecture Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved. Sensor Imaging Operation Imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 11 2005 MagnaChip Semiconductor Ltd. %' 54 " 2 A BA 7 C@ @ 89 6 AB C@ A@ 89 6 7 | (c) (c) UUU Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Time Integration plane frame 0 Integration plane frame 1 Scan plane frame 0 Scan plane frame 1 Integration time Frame 0 time Frame 1 time Correlated Double Sampling(CDS) and Programmable Gain Amplifier(PGA) Correlated double sampling is a circuit for reducing any correlated noise between reset signal and video data signal. First, reset signal is taken and held at the reset sampler. Second, video signal is taken and held at the data sampler. Final, these two signal is subtracted to null any common signal(fixed pattern noise), and thereby the correlated noise that exits at both the reset signal and video signal is minimized. The above subtracted video signal is properly scaled by each R, G, and B programmable gain amplifier and sequentially transmitted from PGA to ADC via the serial line. The amplifier's gain is mutually controlled by auto-exposure control function(AE) and auto-white balance control function(AWB). Any internal offset or noise within the amplifier is removed by internal offset elimination circuit. The scaling range of pre-amplifier for AE is from 0.5X to 16.5X, and the scaling range of color-amplifier for AWB is from 0.5X to 3.5X. 11bit on-chip ADC On-chip ADC converts analog pixel voltage to 11bit digital data. On-chip ADC has a low power, a high resolution, and a high conversion speed to be suitable at an imaging system. Internally, to null the parasitic offset and the fixed pattern noise of pixel, on-chip ADC has an offset adjustment circuit. Also, to increase the conversion rate on-chip ADC has a bias control circuit. Dark Noise Cancellation(DNC) When an interesting center pixel has abnormally large value (decided to the 'dark noise') the center pixel is corrected by using neighbor pixels. Gamma Correction Piecewise linear approximation method is implemented. Ten-piece linear segments are supported and user-programmable. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 12 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing In the above figure, the blue curve is 0.45 gamma effect and the red is default gamma effect. The x-axis label is value fixed by our sensor and it isn't able to be changed by user. User is able to change only pt0 ~ pt9(programmable gamma pointer : GMAP0 ~ GMPP9) and slp0 ~ slp9(gamma slop : GMAS0 ~ GMAS9) to be calculated by below equation, x-axis(xpt) = [ 0, 8, 32, 64, 128, 256, 384, 512, 1024, 1536, 2047 ] - input data gamma pointer(pt) = [ 0, 4, 28, 52, 84, 120, 144, 164, 224, 244, 255 ] - output data (default) gamma slop(slp) = 128 * xpt / pt Color Interpolation This method is supported to interpolate missing R, G, or B for mosaic image data from pixel array. Interpolation method for missing color is done by moving window, and the missing color on center of window is neighbor pixels. Color Correction Color Correction is implemented by 3x3 matrix operation. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. Matrix coefficients are programmable from -127/64 to 127/64. Programming register value for matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer(RealCoefficientValue x 64); For negative values, CMAxx = TwoComplement(Integer(RealCoefficientValue x 64)); RealCoefficientValue values from -127/64 to 127/64 can be programmed. Color-Correction Matrix(CCM) to correct the mismatch of Color Filter Array(CFA) R' = 1.189R - 0.315G + 0.126B G' = -0.259R + 1.838G - 0.579B This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 13 2005 MagnaChip Semiconductor Ltd. # "! ! '(' (c) (c) % % ! $$ %$ %$ %$ %$ %$ " %$ | %$ & %$ Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing B' = -0.029R - 0.374G + 1.403B Color-corrected R'G'B' = CCM * Gamma-corrected RGB In the above equations, R, G, and B are gamma-corrected values. Color Space Conversion For color space conversion matrix, the equation from CCIR-601 standard is normally used. 1. RGB to YUV Color Space Conversion(CSC) equation V = (131R' - 110G' - 21B') / 256 + 128 Range: 16 ~ 240 Y = (77R' + 150G' + 29B') / 256 Range: 16 ~ 235 U = (-44R' -87G' + 131B') / 256 + 128 Range: 16 ~ 240 VYU = CSC * Color-corrected R'G'B' + [ 128 0 128 ] YUV to RGB reverse conversion equation R = Y + 1.371(V - 128) G = Y - 0.698(V - 128) - 0.336(U - 128) B = Y + 1.732(U - 128) 2. RGB to YCbCr Color Space Conversion(CSC) equation Cr = ( 112R' - 94G' - 18B' ) / 256 + 128 Output range: 16 ~ 240 Y = ( 66R' + 129G' + 25B' ) / 256 + 16 Output range: 16 ~ 235 Cb = ( -38R' -74G' + 112B' ) / 256 + 128 Output range: 16 ~ 240 CrYCb = CSC * Color-corrected R'G'B' + [ 128 16 128 ] YCbCr to RGB reverse conversion equation R = 1.1636Y - 0.0029Cb + 1.5991Cr - 222.9271 G = 1.1636Y - 0.3914Cb - 0.8184Cr + 136.2322 B = 1.1636Y + 2.0261Cb + 0.0016Cr - 278.1660 Output Formatter The output formats such as 8bit Bayer Raw Data, 16bit RGB 4:4:4, 16bit YCbCr 4:4:4, 8bit/16bit YCbCr 4:2:2, and 8bit RGB5:6:5 are supported. Possible output bus widths are 8 bits or 16bits, and the sequence of Cb and Cr are programmable. The output formats are compatible with Recommendation CCIR-601, CCIR-656. Auto Exposure Control Y mean value is continuously calculated every frame, and the integration time and the analog preamplifier gain value are mutually increased or decreased according to difference between target and current frame Y mean value. Auto White Balance Control Cb, Cr frame mean value is calculated every frame, and according to Cb, Cr frame mean values' This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 14 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing displacement from Cb, Cr white target point, R, B scaling values for R, B data are resolved and R, G color gain is mutually increased or decreased. On-chip frequency synthesizer (PLL) The PLL is a 1.8V CMOS analog programmable frequency synthesizer based on charged pump type PLL for an on-chip application. PLL has a wide output range. Operating frequency and loop characteristics of PLL are fully programmable. When it is used with the default mode(2x), the output frame rate is supported up to 15frame per second at MCLK 21MHz and VCLK generates up to 42MHz. Luminance processing - Contrast and brightness For contrast adjustment, Y digital channels are scaled by the contrast factor. Contrast factor resolution is 1/128 and its range is 0 ~ 255/128. For brightness adjustment, there is added a brightness factor to Y digital channels. Brightness factor range is -128 ~ 127 and register value for brightness adjustment is following below. For positive values, Brightness factor = Integer; For negative values, Brightness factor = Two's Complement(Integer); For example, if brightness factor is 3, register value is 8'h03 and if brightness factor is -3, register value is 8'hfd. Chrominance processing - Hue, saturation, chroma suppression, and false color suppression For saturation adjustment, Cb, Cr digital Channels are scaled by the saturation factor. Saturation factor resolution is 1/128 and its range is 0 ~ 255/128. Chroma suppression is performed in the dark environment for suppressing the color and decreasing dark bad pixel effect. Suppression level is varied in accordance with amplifier gain and This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 15 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing saturation level is user-programmable. Edge enhancement Edge enhancement is performed for increasing sharpness of image. Edge weight factor is userprogrammable. Special image functions Special image functions support the negative, mono, gray, level, and sepia image. Frame Timing For clear description of frame timing, clocks' acronym and relation are reminded in here again. < Clock Acronym Definition > MCP : Master Clock Period SCP : Sensor Clock Period VCP : Video Clock Period < Clock Frequency Relation > MCP : MCP SCP : DCP * 2 DCP : MCP * Clock Division SCP for color interpolation, SCP * 2 for 1/4 subsampling mode ICP SCP * 4 for 1/16 subsampling mode DCP : Divided Clock Period ICP : Image Processing Clock Period LCP : Line Clock Period VCP : ICP for 16bit output, ICP / 2 for 8bit LCP : HBLANK Period + HSYNC Period output HBLANK Period : HBLANK Time register value * SCP HSYNC Period : HSYNC Active Time < Frame Time Calculation > Core Frame Time is (IDLE SLOT + Video Height * LCP), and Real Frame Time is resolved as follows. When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP), otherwise is (Core Frame Time + VBLANK * LCP). If Integration Time < Core Frame Time, Real Frame Time is {(1280 + 214) * ( 960 + 10) + SCTRC[0] * 4928} * SCP = 1454108 * 47.62ns = 0.069245sec, else Real Frame Time is {Integration Time + 8 * (208 + 1280) } * SCP. 1. 1/4 Sub-sampling Timing In 1/4 subsampling mode, valid video data is produced every other line, i.e. for 960 lines, active video lines are 432 lines. HSYNC active time is equal to HSYNC active time of color interpolation This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 16 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing mode, but video clock frequency is half of color interpolation mode's to produce half size output in horizontal direction. Frame rate at the 1/4 ISP sub-sampling mode is equal to the full mode, but at the 1/4 Bayer sub-sampling mode, double of the full mode. 2. 1/16 Sub-sampling Timing In 1/16 subsampling mode, valid video data is produced every four line, i.e. for 960 lines, active video lines are 216 lines. HSYNC active time is equal to HSYNC active time of color interpolation mode, but video clock frequency is a quarter of color interpolation mode's to produce a quarter size output in horizontal direction. Frame rate at the 1/16 ISP sub-sampling mode is equal to the full mode, but at the 1/16 Bayer sub-sampling mode, 4 times of the full mode. Anti-Banding Configuration For Anti-Banding mode to work correctly, the following registers should be configured to the appropriate values. AE Mode1 AE Anti-Banding Step AE Integration Time Limit 70h 7a-7ch 7d-7fh Anti-Banding Enable[6] SCP * (2 x power line frequency) The value should be multiples of AE Anti-Banding Step When Anti-Banding is enabled, AE initializes Integration Time registers[73-75h] to 4 x AntiBanding Step value[7a-7ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 17 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Register Description Symbol DEVID SCTRA SCTRB SCTRC RSAU RSAL CSAU CSAL WIHU WIHL WIWU WIWL HBLU HBLL VBLU VBLL RCG GCG BCG PGAVAL PGAMIN PGAMAX PGANOM RCLMP Address (Hex) 00 01 02 03 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1C 1D 1E Default (Hex) 61 23 00 01 00 02 00 02 03 C0 05 00 00 D0 00 08 15 15 15 08 00 FF 08 07 11 77 Recommend (Hex) Device ID 13 Sensor Control A Sensor Control B Sensor Control C Description Row Start Address Upper Row Start Address Lower Column Start Address Upper Column Start Address Lower Window Height Upper Window Height Lower Window Width Upper Window Width Lower Horizontal Blank Time Upper Horizontal Blank Time Lower Vertical Blank Time Upper Vertical Blank Time Lower 20 20 20 22 14 5F 22 07 66 d3 Red Color Gain Green Color Gain Blue Color Gain Amp Gain for Pixel Output Amp Gain Minimum Value Amp Gain Maximum Value Amp Gain Normal Value Clamp Enable, Reset Level Clamp Enable PXLBS PGABS Pixel Bias and Shift Bias controls PGA Bias and CDS Bias controls This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 18 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing ADCBS OREDI OGRNI OBLUI OREDU OGRNU OBLUU BLKTH CREDI CGRNI CBLUI ISPFUN OUTFMT OUTINV DNCMODE DNCGAIN DNCINTH DNCINTM CRCM11 CRCM12 CRCM13 CRCM21 CRCM22 CRCM23 CRCM31 CRCM32 CRCM33 GMAP0 GMAP1 1F 21 22 23 24 25 26 27 28 29 2A 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 20 7F 7F 7F RO RO RO FF 00 00 00 02 30 00 21 3E 13 12 2F DB F6 0F 28 08 F5 C3 3D 00 01 26 26 2C D5 FE 13 2E 00 F0 BD 51 00 04 FE 85 A0 85 ADC Bias controls ADC Initial Offset Value for Optical Black Red ADC Initial Offset Value for Optical Black Green ADC Initial Offset Value for Optical Black Blue ADC Red Update Offset ADC Green Update Offset ADC Blue Update Offset Black Level Threshold Value Digital Compensation Red Offset Value Digital Compensation Green Offset Value Digital Compensation Blue Offset Value Image Signal Processing Functions Enable Image Data Output Format Output Signal Inversion Dark Noise Cancellation Mode Preamp. Gain to activate Dark Cancellation Integration time to activate Dark Cancellation Integration time Cancellation to activate Dark Noise Noise Noise Color Correction matrix coefficient 11 Color Correction matrix coefficient 12 Color Correction matrix coefficient 13 Color Correction matrix coefficient 21 Color Correction matrix coefficient 22 Color Correction matrix coefficient 23 Color Correction matrix coefficient 31 Color Correction matrix coefficient 32 Color Correction matrix coefficient 33 Start point for gamma line segment 0 Start point for gamma line segment 1 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 19 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing GMAP2 GMAP3 GMAP4 GMAP5 GMAP6 GMAP7 GMAP8 GMAP9 GMAS0 GMAS1 GMAS2 GMAS3 GMAS4 GMAS5 GMAS6 GMAS7 GMAS8 GMAS9 RCRCONST GCRCONST GCBCONST BCBCONST SINX COSX BRIGHTNESS SATURATION EGWTCON EDTHLO SUPGMIN 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5B 5C 5D 5E 60 08 20 3A 58 6D 7D AE D7 10 25 60 34 1E 15 10 0C 0A 0A 57 D4 EB 6E 00 80 00 80 00 10 24 0B 13 20 36 49 5A 98 CE 40 27 1F 1A 16 13 12 0F 0D 0C Start point for gamma line segment 2 Start point for gamma line segment 3 Start point for gamma line segment 4 Start point for gamma line segment 5 Start point for gamma line segment 6 Start point for gamma line segment 7 Start point for gamma line segment 8 Start point for gamma line segment 9 Slope value for gamma line segment 0 Slope value for gamma line segment 1 Slope value for gamma line segment 2 Slope value for gamma line segment 3 Slope value for gamma line segment 4 Slope value for gamma line segment 5 Slope value for gamma line segment 6 Slope value for gamma line segment 7 Slope value for gamma line segment 8 Slope value for gamma line segment 9 Inverse Color Space Conversion Constant for R Inverse Color Space Conversion Constant for G Inverse Color Space Conversion Constant for G Inverse Color Space Conversion Constant for B Hue Sin value Hue Cos value Brightness value Saturation value 03 07 Edge Weight Control Value Edge Enhancement Threshold Low Suppression Pre Amp Gain Min This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 20 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing SATGMIN EDGGMIN HIEDGVAL FCORTHLO FCORTHHI CONSTRAST CONTVALUE SPESEL SPETHVALUE AF_CTRL AF_WinWgt AF_EdgTh AF_StateThH AF_StateThL AEMODE1 AEMODE2 AEWINWGT INTH INTM INTL LUTARGET1 LUTARGET2 AELOCKFINEBND AEUNLOCKBND AEINTSTEPH AEINTSTEPM AEINTSTEPL AEINTLIMITH AEINTLIMITM AEINTLIMITL 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 24 24 FF 00 FF 00 00 00 00 A6 CD 00 00 0A 29 ED CD 02 71 03 5A 5A F6 2A 01 38 80 09 C4 00 50 50 F4 2B 01 96 E6 26 25 90 69 Saturation Pre Amp Gain Min Edge Enhancement Preamp. Gain Min Edge Enhancement Higher Limit Value False Color Suppression Threshold Low False Color Suppression Threshold High Contrast Contrast Control Value Special Image Functions Mode Special Image Functions Threshold value Auto Focus Value Control Window Weight Control for AF Edge Threshold for AF State-decision Threshold High for AF State-decision Threshold Low for AF AE Mode1 AE Mode2 AE Window Weight Integration Time High Integration Time Middle Integration Time Low AE In-Door Target AE Out-Door Target AE Lock Boundary AE Unlock Boundary AE Anti-Flicker Step High AE Anti-Flicker Step Middle AE Anti-Flicker Step Low AE Maximum Limit High AE Maximum Limit Middle AE Maximum Limit Low This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 21 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing AWBMODE AWBWINWGT CBTARGT CRTARGT AWBLOCKBND AWBUNLOCKBND CBWHITEBND CRWHITEBND AWBCBND AEFSM AWBFSM LUFMEAN CBFMEAN CRFMEAN KLBNDMIN KLBNDMAX AWBWHITE AWBBLACK AWBNUMBER INTSCNOFSH INTSCNOFSM INTSCNOFSL AWBRGAINMAX AWBRGAINMIN AWBBGAINMAX AWBBGAINMIN PCTRA PCTRB PREFDIV PFDDIVH 80 82 83 84 85 86 87 88 89 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 9A 9B 9C 9D A0 A1 A3 A4 18 00 80 80 04 20 30 30 30 RO RO RO RO RO 14 3D FF 00 02 RO RO RO 7F 00 7F 00 01 1D 01 00 38 AWB Mode AWB Window Weight 7C 7C AWB Cb Target Position AWB Cr Target Position AWB Lock Boundary AWB Unlock Boundary AWB Cb White Pixel Boundary AWB Cr White Pixel Boundary AWB Cb + Cr Boundary AE State Machine AWB State Machine Lu Frames Mean Cb Frame Mean Cr Frame Mean. Anti Banding Preamp Gain Min 2D Anti Banding Preamp Gain Max Awb White Pixel Boundary Awb Black Pixel Boundary Awb Valid Number Integration - Scan Plane Offset High Integration - Scan Plane Offset Mid Integration - Scan Plane Offset Low 3F AWB Red Gain Maximum Value AWB Red Gain Minimum Value 3F AWB Blue Gain Maximum Value AWB Blue Gain Minimum Value 00 10 PLL Control Register A PLL Control Register B PLL Reference Divisor PLL Feedback Divisor High This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 22 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing PFDDIVL AF_State AF_Value4 AF_Value3 AF_Value2 AF_Value1 NFILTERCON A5 B0 B1 B2 B3 B4 B5 02 RO RO RO RO RO 04 84 PLL Feedback Divisor Low Current State for AF Focal Value 4th Byte for AF (Upper) Focal Value 3rd Byte for AF Focal Value 2nd Byte for AF Focal Value 1st Byte for AF (Lower) Adaptive Noise Filter Control This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 23 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Device ID [DEVID : 00h : 61h] 7 6 5 4 3 2 1 0 Revision Number 0 1 1 0 0 0 0 High Nibble represents product number, Low Nibble represents revision number. Product ID 1 Sensor Control A [SCTRA : 01h : 23h] 7 6 5 4 3 2 1 0 Reserved 0 Fixed Frame Rate 0 X-Flip 1 Y-Flip 0 CifMode 0 SSSel 0 Video Mode 1 1 Fixed Frame Rate X-Flip Y-Flip CifMode Sensor supports the fixed frame rate with anti-banding mode Image is horizontally flipped Image is vertically flipped 4CIF, CIF(1/4 sub-sampling), or QCIF(1/16 sub-sampling) mode enable Sub-Sampling mode ISP Sub-Sampling. Image quality is better than Bayer SubSampling, but Core Frame Rate doesn't change. Bayer Sub-Sampling. Image quality is lower than ISP SubSampling, but Core Frame Rate is double. No Scaling mode 1/4 sub-sampling 1/16 sub-sampling No Scaling mode (equal to '11') SSSel 0 1 11 10 01 00 Video Mode Sensor Control B [SCTRB : 02h : 00h] 7 6 5 4 3 2 1 0 AE/AWB Block Sleep 0 Datapath Block Sleep 0 Analog Block Sleep 0 Sleep Mode 0 Strobe Enable 0 0 Clock Division 0 0 AE/AWB Block Sleep Datapath Block Sleep Analog Block Sleep Sleep Mode AE/AWB block goes into sleep mode with this bit set to high. Image processing datapath block goes into sleep mode with this bit set to high. All internal analog block goes into sleep mode with this bit set to high. With All Digital Block Sleep active, sensor goes into power down mode. All internal digital and analog block goes into soft sleep with this bit set to This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 24 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Strobe Enable Clock Division high. When strobe signal is enabled by this bit, STROBE pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image. Divides input master clock(IMC) for internal use. Internal divided clock frequency(DCF) is defined as master clock frequency(MCF) divided by specified clock divisor. Internal divided clock frequency(DCF) is as follows. 000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8 100 : MCF/16, 101 : MCF/32, 110 : MCF/64, 111 : MCF/128 Sensor Control C [SCTRC : 03h : 01h] 7 6 5 4 3 2 1 0 Bayer Output Enable 0 Single Shot Mode 0 Black Level Average Output 0 HSYNC in VBLANK 0 reserved reserved 0 0 Black Level Data Enable 0 Black Level Compens ation 1 Bayer Output Enable Single Shot Mode Black Level Average Output More information is available on Bayer Data Format section. With this register set to High, single video image is streamed out. This bit enable R/G/B Active Offset registers[24h-26h] to represent black level average value, instead of updated active offset values VBLANK is equivalent to VSYNC, and HSYNC is the inversion of HBLANK, and this bit controls whether HSYNC is active or not when VBLANK unit is LCF. VSYNC (VBLANK) HSYNC HSYNC in VBLANK Black Level Data Enable Black Level Compensation HSYNC is generated for light-shielded pixels in 4 lines. Black level average values of light-shielded pixels are compensated when active image data is produced. Row Start Address Upper [RSAU : 08h : 00h] 7 6 5 4 3 2 1 0 Reserved R0 R0 R0 R0 R0 R0 Row Start Address Upper 0 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 25 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Row Start Address Lower [RSAL : 09h : 02h] 7 6 5 4 3 2 1 0 Row Start Address Lower 0 0 0 0 0 0 1 Row Start Address register defines the row start address of image read-out operation. 0 Column Start Address Upper [CSAU : 0ah : 00h] 7 6 5 4 3 2 1 0 R0 R0 Reserved R0 R0 R0 Column Start Address Upper 0 0 0 Column Start Address Lower [CSAL : 0bh : 02h] 7 6 5 4 3 2 1 0 Column Start Address Lower 0 0 0 0 0 0 1 0 Column Start Address register defines the column start address of image read-out operation. Window Height Upper [WIHU : 0ch : 03h] 7 6 5 4 3 2 1 0 Reserved R0 R0 R0 R0 R0 R0 Window Height Upper 1 1 Window Height Lower [WIHL : 0dh : c0h] 7 6 5 4 3 2 1 0 Window Height Lower 1 1 0 0 0 0 Window Height register defines the height of image to be read-out. 0 0 Window Width Upper [WIWU : 0eh : 05h] 7 6 5 4 3 2 1 0 R0 R0 Reserved R0 R0 R0 Window Width Upper 1 0 1 Window Width Lower [WIWL : 0fh : 00h] 7 6 5 4 3 2 1 0 0 0 0 Window Width Lower 0 0 0 0 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 26 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Window Width Address register defines the width of image to be read-out. Horizontal Blank Time Upper [HBLU : 10h : 00h] 7 6 5 4 3 2 1 0 0 0 0 Horizontal Blank Time Upper 0 0 0 0 0 Horizontal Blank Time Lower [HBLL : 11h : d0h] 7 6 5 4 3 2 1 0 Horizontal Blank Time Lower 1 1 0 1 0 0 0 0 HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit, and should be larger than 208(d0h). Vertical Blank Time Upper [VBLU : 12h : 00h] 7 6 5 4 3 2 1 0 0 0 0 Vertical Blank Time Upper 0 0 0 0 0 Vertical Blank Time Lower [VBLL : 13h : 08h] 7 6 5 4 3 2 1 0 Vertical Blank Time Lower 0 0 0 0 1 0 0 0 VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames. Red Color Gain [RCG : 14h : 15h] 7 6 5 4 3 2 1 0 Reserved 0 0 0 1 Red Amplifier Gain 0 1 0 1 Green Color Gain [GCG : 15h :15h] 7 6 5 4 3 2 1 0 Reserved 0 0 0 Green Amplifier Gain 1 0 1 0 1 Blue Color Gain [BCG : 16h :15h] 7 6 5 4 3 2 1 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 27 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Reserved Blue Amplifier Gain 0 0 0 1 0 1 0 1 There are three color gain registers for R, G, and B pixels, respectively. Programmable range is from 0.5X ~ 3.5X. Effective Gain = 0.5 + B<6:0>/42.4. These registers may be used for white balance and color effect with independent R,G,and B color control. Recommend gain is 1.0X (15h). Amp Gain for Pixel Output [PGAVAL : 17h : 08h] 7 6 5 4 3 2 1 0 Amp Gain 0 0 0 0 1 0 0 0 Amp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 16.5X. Default gain is 1.0X. Gain = 0.5 + B<7:0>/16 Amp Gain Minimum Value [PGAMIN : 18h : 00h] 7 6 5 4 3 2 1 0 Amp Gain Minimum 0 0 0 0 0 0 0 0 Amp Gain Minimum Value is minimum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. Programmable range is same as Amp Gain. Default value is 0.5X. Amp Gain Maximum Value [PGAMAX : 19h : ffh] 7 6 5 4 3 2 1 0 Amp Gain Maximum 1 1 1 1 1 1 1 1 Amp Gain Maximum Value is maximum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. Programmable range is same as Amp Gain. Default value is 16.5X. Amp Gain Normal Value [PGANOM : 1ah : 08h] 7 6 5 4 3 2 1 0 Amp Gain Normal 0 0 0 0 1 0 0 0 Amp Gain Normal Value is reference value of amp gain when sensor adjusts amp gain for auto exposure control. First, sensor controls integration time before adjusting amp gain for auto exposure control. After integration time is changed to the minimum or maximum value, sensor adjusts amp gain from this register value. Refer to figure of AE mode2 register(71H). Programmable range is same as Amp Gain. Default value is 1.0X. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 28 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Reset Level Clamp [RCLMP : 1ch : 17h] 7 6 5 4 3 2 1 0 Reserved Clamp On Reset Level Clamp 0 0 0 1 0 1 1 1 Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level. Pixel Bias [PXLBS : 1dh : 11h] 7 6 5 4 3 2 1 0 Reserve Shift Bias d 0 0 0 1 0 0 0 1 Pixel Bias and Shift Bias controls the amount of current in pixel bias circuit to operate Pixel effectively. Reserved Pixel Bias Programmable Amplifier Bias [PGABS : 1eh : 77h] 7 6 5 4 3 2 1 0 PGA Bias CDS Bias 0 1 1 1 0 1 1 1 PGA Bias and CDS Bias control the amount of current in PGA and CDS bias circuit to operate PGA and CDS effectively. ADC Bias Control [ADCBS : 1fh : 20h] 7 6 5 4 3 2 1 0 Reserved ADC Bias Reserved 0 0 1 0 0 0 0 ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. 0 Auto black level compensation Each sensor has little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrates internal sensing circuit in order to get optimal performance. Sensor characteristics adjustment registers are as below. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 29 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing ADC Initial Offset Value for Optical Black Red [OREDI : 21h : 7fh] 7 6 5 4 3 2 1 0 0 1 1 Red Pixel Black Offset 1 1 1 1 1 ADC Initial Offset Value for Optical Black Green [OGRNI : 22h : 7fh] 7 6 5 4 3 2 1 0 0 1 1 Green Pixel Black Offset 1 1 1 1 1 ADC Initial Offset Value for Optical Black Blue [OBLUI : 23h : 7fh] 7 6 5 4 3 2 1 0 Blue Pixel Black Offset 0 1 1 1 1 1 1 1 These registers control the offset voltage of ADC that changes the black level value for lightshielded pixels, R,G,and B respectively. Register bit functions are composed as follows. The bit specifies whether to subtract or add the offset voltage in ADC input Pixel Black Offset[7] for light-shielded pixels. Pixel Black This value specifies the amount of offset voltage for light-shielded pixels. Offset[6:0] Red Pixel Active Offset [OREDU : 24h : RO] 7 6 5 4 3 2 1 0 RO RO RO Red Pixel Active Offset RO RO RO RO RO Green Pixel Active Offset [OGRNU : 25h : RO] 7 6 5 4 3 2 1 0 RO RO RO Green Pixel Active Offset RO RO RO RO RO Blue Pixel Active Offset [OBLUU : 26h : RO] 7 6 5 4 3 2 1 0 Blue Pixel Active Offset RO RO RO RO RO RO RO RO These registers represent black level average offset values for light-shielded pixels R,G,B or updated active offset values for R,G,B, respectively. What values are monitored is decided by This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 30 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing SCTRC[5]. Black Level Threshold Value [BLKTH : 27h : ffh] 7 6 5 4 3 2 1 0 Black Level Threshold 0 0 1 1 1 1 1 1 The register specifies the maximum value that determines whether light-shielded pixel output is valid. When light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation. ADC Compensation Offset Value for Optical Black Red [CREDI : 28h : 00h] 7 6 5 4 3 2 1 0 0 1 1 Red Pixel Compensation Offset 1 1 1 1 1 ADC Compensation Offset Value for Optical Black Green [CGRNI : 29h : 00h] 7 6 5 4 3 2 1 0 0 1 Green Pixel Compensation Offset 1 1 1 1 1 1 ADC Compensation Offset Value for Optical Black Blue [CBLUI : 2ah : 00h] 7 6 5 4 3 2 1 0 Blue Pixel Compensation Offset 0 1 1 1 1 1 1 1 These registers manually control the offset value of ADC addition to ADC initial offsets. Register bit functions are composed as follows. Compensation Offset[7] The bit specifies whether to subtract or add the offset level. Compensation Offset[6:0] This value specifies the amount of offset level. ISP Function Enable [ISPFUN : 30h : 02h] 7 6 5 4 Color False Color Smooth Saturation Filter Suppressi Suppressi Suppressio on Enable on Enable n Enable Enable 0 0 0 0 3 Edge Enhance Enable 0 2 Edge Algorithm Select 0 1 Gamma Correction 1 0 Y+16 Enable 0 Output Format [OUTFMT : 31h : 30h] This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 31 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 7 6 5 4 3 2 1 0 Reserved Bayer 11bit Output U First Y First 16bit Bus RGB 5:6:5 4:4:4 Format 24bit RGB 0 0 1 1 0 0 0 0 If this bit is high, then 11bit Bayer raw values are continuously outputted through output ports, Y0[7:0] = Bayer[10:3], Y1[2:0] = Bayer[2:0], else 8bit Bayer 11bit Output Bayer raw only, Y[7:0] = Bayer[10:3]. And when this bit is high and 16bit bus mode is enabled, Y[7:0] is outputted Bayer[10:3] and C[2:0] is outputted Bayer[2:0]. For more information, refer page 62, Bayer data format. U First Cb(B) pixel in front of Cr(R) pixel in 16bit or 8bit video data output modes. Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is Y First meaningful only with YCbCr 4:2:2 8bit output mode. If this bit is high, output format is 16bit mode(YCbCr 4:2:2, YCbCr 4:4:4, or 16Bit Bus RGB 4:4:4), otherwise output format is 8bit mode(YCbCr 4:2:2, RGB 5:6:5, Bayer). Data format of RGB 5:6:5 mode is composed with {R[7:3]/G[7:5]} , RGB 5:6:5 {G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. OUTFMT[5](Cb/B First) register affects above data form. YCbCr 4:4:4 or RGB 4:4:4 24bit data for a pixel is produced with 16bit 4:4:4 Format output mode. (16bit Bus = '1') R,G,B 4:4:4 24bit data for a pixel is produced with 16bit output mode.(16bit 24Bit RGB Bus = '1' and 4:4:4 Format = '1') Default mode of Output Format is YCbCr 4:2:2 8bit bus mode. Output Signal Inversion [OUTINV : 32h : 00h] 7 6 5 4 3 2 1 0 Reserved Clocked HSYNC VSYNC inversion HSYNC inversion VCLK inversion 0 0 0 0 0 0 0 0 Clocked HSYNC VSYNC inversion HSYNC inversion VCLK inversion In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNC time VSYNC output polarity is inverted HSYNC output polarity is inverted VCLK output polarity is inverted Dark Noise Cancellation [DNCMODE : 33h : 21h] 7 6 5 4 3 2 1 0 0 DNC Always Performing Zone 0 1 DNC Threshold DNC Mode 0 0 0 0 1 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 32 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing DNC Always Performing Zone DNC Threshold 00 In this zone, DNC function is always enabled regardless of DNC Mode. Degree of the dark noise strength (Tight)11 - 10 - 01 - 00(Loose) Always disabled Conditional enabled - Integration Time [73h-75h] > (DNC enable integration Time [35h-36h] * 256) - Pre-Amp Gain [17h] > Dnc Gain [34h] Always enabled DNC Mode 01 10 DNC Enable Gain [DNCGAIN : 34h : 3eh] 7 6 5 4 3 2 1 0 0 0 1 Dnc Enable Gain 1 1 1 1 0 DNC Enable Int. Time High [DNCINTH : 35h : 13h] 7 6 5 4 3 2 1 0 0 0 0 DNC Enable Int. Time High 1 0 0 1 1 DNC Enable Int. Time Mid [DNCINTM : 36h : 12h] 7 6 5 4 3 2 1 0 0 0 0 DNC Enable Int. Time Min 1 0 0 1 0 Color Correction Matrix Coefficient 11 [CRCM11 : 37h : 2fh] 7 6 5 4 3 2 1 0 0 0 Color Correction Matrix Coefficient 11 1 0 1 1 1 1 Color Correction Matrix Coefficient 12 [CRCM 12 : 38h : dbh] 7 6 5 4 3 2 1 0 1 1 Color Correction Matrix Coefficient 12 0 1 1 0 1 1 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 33 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Color Correction Matrix Coefficient 13 [CRCM 13 : 39h : f6h] 7 6 5 4 3 2 1 0 1 1 Color Correction Matrix Coefficient 13 1 1 0 1 1 0 Color Correction Matrix Coefficient 21 [CRCM 21 : 3ah 0fh] 7 6 5 4 3 2 1 0 0 0 Color Correction Matrix Coefficient 21 0 0 1 1 1 1 Color Correction Matrix Coefficient 22 [CRCM 22 : 3bh : 28h] 7 6 5 4 3 2 1 0 0 0 Color Correction Matrix Coefficient 22 1 0 1 0 0 0 Color Correction Matrix Coefficient 23 [CRCM 23 : 3ch : 08h] 7 6 5 4 3 2 1 0 0 0 Color Correction Matrix Coefficient 23 0 0 1 0 0 0 Color Correction Matrix Coefficient 31 [CRCM 31 : 3dh : f5h] 7 6 5 4 3 2 1 0 1 1 Color Correction Matrix Coefficient 31 1 1 0 1 0 1 Color Correction Matrix Coefficient 32 [CRCM 32 : 3eh : c3h] 7 6 5 4 3 2 1 0 1 1 Color Correction Matrix Coefficient 32 0 0 0 0 1 1 Color Correction Matrix Coefficient 33 [CRCM 33 : 3fh : 3dh] 7 6 5 4 3 2 1 0 0 0 Color Correction Matrix Coefficient 33 1 1 1 1 0 1 Gamma Segment Start Points This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 34 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma approximation. Current default gamma curve is much selected for optimum gray gradation. Gamma Point 0 [GAMP0 : 40h : 00h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Point 0 0 0 0 0 0 Gamma Point 1 [GMAP1 : 41h : 01h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Point 1 0 0 0 0 1 Gamma Point 2 [GMAP2 : 42h : 08h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Point 2 0 1 0 0 0 Gamma Point 3 [GMAP3 : 43h 20h] 7 6 5 4 3 2 1 0 0 0 1 Gamma Point 3 0 0 0 0 0 Gamma Point 4 [GMAP4 : 44h : 3ah] 7 6 5 4 3 2 1 0 0 0 1 Gamma Point 4 1 1 0 1 0 Gamma Point 5 [GMAP5 : 45h : 58h] 7 6 5 4 3 2 1 0 0 1 0 Gamma Point 5 1 1 0 0 0 Gamma Point 6 [GMAP6 : 46h : 6dh] 7 6 5 4 3 2 1 0 0 1 1 Gamma Point 6 0 1 1 0 1 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 35 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Gamma Point 7 [GMAP7 : 47h : 7dh] 7 6 5 4 3 2 1 0 0 1 1 Gamma Point 7 1 1 1 0 1 Gamma Point 8 [GMAP8 : 48h : aeh] 7 6 5 4 3 2 1 0 1 0 1 Gamma Point 8 0 1 1 1 0 Gamma Point 9 [GMAP9 : 49h : d7h] 7 6 5 4 3 2 1 0 1 1 0 Gamma Point 9 1 0 1 1 1 Gamma Slope 0 [GMAS0 4ah : 10h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 0 1 0 0 0 0 Gamma Slope 1 [GMAS1 : 4bh : 25h] 7 6 5 4 3 2 1 0 0 0 1 Gamma Slope 2 [GMAS2 : 4ch : 60h] 7 6 5 Gamma Slope 1 0 0 4 3 1 2 0 1 1 0 0 1 1 Gamma Slope 2 0 0 0 0 0 Gamma Slope 3 [GMAS3 : 4dh : 34h] 7 6 5 4 3 2 1 0 0 0 1 Gamma Slope 3 1 0 1 0 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 36 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Gamma Slope 4 [GMAS4 : 4eh : 1eh] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 4 1 1 1 1 0 Gamma Slope 5 [GMAS5 : 4fh : 15h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 5 1 0 1 0 1 Gamma Slope 6 [GMAS6 : 50h : 10h] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 6 1 0 0 0 0 Gamma Slope 7 [GMAS7 : 51h : 0ch] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 7 0 1 1 0 0 Gamma Slope 8 [GMAS8 : 52h : 0ah] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 8 0 1 0 1 0 Gamma Slope 9 [GMAS9 : 53h : 0ah] 7 6 5 4 3 2 1 0 0 0 0 Gamma Slope 9 0 1 0 1 0 Inverse Color Space Conversion Inverse color space conversion converts from YUV to RGB and default values support the CCIR601 standard. This is activated only when RGB5:6:5 or RGB 4:4:4 formats are used. R = Y + A(Cr-128) G = Y - B(Cr-128) - C(Cb-128) This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 37 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing B = Y + D(Cb-128) A : Inverse Color constant for R[54h] B : Inverse Color constant for G[55h] C : Inverse Color constant for G[56h] D : Inverse Color constant for B[57h] Inverse Color constant for R [RCRCONST : 54h : 57h] 7 6 5 4 3 2 1 0 0 1 0 Inverse Color constant for R 1 0 1 1 1 Inverse Color constant for G [GCRCONST : 55h : d4h] 7 6 5 4 3 2 1 0 1 1 0 Inverse Color constant for G 1 0 1 0 0 Inverse Color constant for G [GCBCONST : 56h : ebh] 7 6 5 4 3 2 1 0 1 1 1 Inverse Color constant for G 0 1 0 1 1 Inverse Color constant for B [BCBCONST : 57h : 6eh] 7 6 5 4 3 2 1 0 0 1 1 Inverse Color constant for B 0 1 1 1 0 Image Enhancement User is able to control Hue, Saturation, Contrast, and Brightness registers. Hue value 1 [SINX : 58h : 00h] 7 6 5 4 3 2 1 0 0 0 0 Hue value 1 0 0 0 0 0 Hue value 2 [COSX : 59h : 80h] 7 6 5 4 3 2 1 0 Hue value 2 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 38 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 1 0 0 0 0 0 0 0 Brightness value [BRIGHTNESS : 5bh : 00h] 7 6 5 4 3 2 1 0 Brightness value 0 0 0 0 0 Brightness value range is from -127 to +128(2's complement). 0 0 0 Saturation value [SATURATION : 5ch : 80h] 7 6 5 4 3 2 1 0 1 0 0 Saturation value 0 0 0 0 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 39 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Saturation value range is from 0.0x to 1.99x < Contrast & Saturation parameter > * Parameter is multiplied by 128. Number 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Contrast & Saturation (hex) 0D 1A 26 33 40 4D 5A 66 73 80 Number 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.99 Contrast & Saturation (hex) 8D 9A A6 B3 C0 CD DA E6 F3 FF Edge Weight Control value [EGWTCON : 5dh : 00h] 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 Edge weight control value range is from 0.5x to 8.0x. 0 Edge Weight 0 0 0 Edge Enhancement Vth Low [EDTHLO : 5eh : 10h] 7 6 5 4 3 2 1 0 0 0 0 Edge Enhancement Vth Low 1 0 0 0 0 Suppression Pre Amp Gain Min [SUPGMIN : 60h : 24h] 7 6 5 4 3 2 1 0 0 0 1 Suppression Pre Amp Gain Min 0 0 1 0 0 Saturation Pre Amp Gain Min [SATGMIN : 61h : 24h] 7 6 5 4 3 2 1 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 40 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 0 0 1 Saturation Pre Amp Gain Min 0 0 1 0 0 Edge Pre Amp Gain Min [EGEGMIN : 62h : 24h] 7 6 5 4 3 2 1 0 0 0 1 Edge Pre Amp Gain Min 0 0 1 0 0 Hi Edge Value [HIEDGVAL : 63h : ffh] 7 6 5 4 3 2 1 0 1 1 1 Hi Edge Value 1 1 1 1 1 False Color Th. Low [FCORTHLO : 64h : 00h] 7 6 5 4 3 2 1 0 0 0 0 False Color Th. High 0 0 0 0 0 False Color Th. High [FCORTHHI : 65h : ffh] 7 6 5 4 3 2 1 0 1 1 1 False Color Th. High 1 1 1 1 1 False Color Th. High [FCORTHHI : 65h : ffh] 7 6 5 4 3 2 1 0 1 1 1 False Color Th. High 1 1 1 1 1 Contrast [CONTRAST : 66h : 00h] 7 6 5 4 3 2 1 0 Reserved 0 0 Contrast Control 0 0 00 01 11 0 Contrast Control Value Select 0 0 0 Contrast Control Disable Updates the contrast control values. Enable This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 41 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Contrast Control Value Select 0000 ~ 0100 0101 ~ 1001 Selects the contrast X-point values. (Xpt1 ~ Xpt4) Selects the contrast slope values. (Slp1 ~ Slp5) Contrast Control Value [CONTVALUE : 67h : 00h] 7 6 5 4 3 2 1 0 0 0 0 Contrast Control Value 0 0 0 0 0 Special Image Functions Available functions are mono tone, gray scale, sepia, and negative. Sepia Cb/Cr Value bits and special image functions threshold value register can be used when you want to change Cb and Cr sense of image for sepia mode. Mono value bit and special image functions threshold value register are can be used when you want to change a threshold value determining white and black level at mono tone. Special Image Functions mode [SPESEL : 68h : 00h] 7 6 5 4 3 2 1 0 Sepia Cb/Cr Value 0 0 Mono Value 0 Reserved 0 0 0 Function Mode 0 0 Function Mode Mono Value Sepia Cb/Cr Value 000 Normal image (default) 001 Gray scale image 010 Sepia tone image 011 Negative image 100 Mono tone image 110 Auto level image If function mode is mono tone image and this pin is high, using this register can change a threshold value determining white and black level. After set SPESEL to 24h, set SPETHVALUE register to a value which you want. If you want other image tone, but not sepia, using this bits and SPETHVALUE register is possible. First, set SPESEL to 42h and set SPETHVALUE register to a Cb value which you want. Final, set SPESEL to 82h and set SPETHVALUE register to a Cr value which you want. 00 Cb and Cr are set to default value. 01 Cb value is set to SPETHVALUE register. 10 Cr value is set to SPETHVALUE register. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 42 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Special Image Functions Threshold value [SPETHVALUE : 69h : 00h] 7 6 5 4 3 2 1 0 0 0 Special Image Functions Threshold Value 0 0 0 0 0 0 Auto Focus Value Control [AF_CTRL : 6ah : a6h] 7 6 5 4 3 2 1 0 State Select 1 0 Window Ratio 1 0 0 Reserved 1 Edge Selection 1 Focus Value Enable 0 Window Weight Control for AF [AF_WinWgt : 6bh : cdh] 7 6 5 4 3 2 1 0 1 1 0 Window Weight Control 0 1 1 0 1 Edge Threshold for AF [AF_EdgTh : 6ch : 00h] 7 6 5 4 3 2 1 0 0 0 0 Edge Threshold 0 0 0 0 0 State-decision Threshold for AF [AF_StateThH : 6dh : 00h] 7 6 5 4 3 2 1 0 0 0 0 State-decision Threshold High 0 0 0 0 0 State-decision Threshold for AF [AF_StateThL : 6eh : 0ah] 7 6 5 4 3 2 1 0 0 0 0 State-decision Threshold Low 0 1 0 1 0 Current State for AF [AF_State : b0h : ROh] 7 6 5 4 3 2 1 0 Current State This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 43 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing RO RO RO RO RO RO RO RO Focal Value 4th Byte for AF [AF_StateThL : b1h : ROh] 7 6 5 4 3 2 1 0 RO RO RO Focal Value 4th Byte RO RO RO RO RO Focal Value 3rd Byte for AF [AF_StateThL : b2h : ROh] 7 6 5 4 3 2 1 0 RO RO RO Focal Value 3rd Byte RO RO RO RO RO Focal Value 2nd Byte for AF [AF_StateThL : b3h : ROh] 7 6 5 4 3 2 1 0 RO RO RO Focal Value 2nd Byte RO RO RO RO RO Focal Value 1st Byte for AF [AF_StateThL : b4h : RO] 7 6 5 4 3 2 1 0 RO RO RO Focal Value 1st Byte RO RO RO RO RO Adaptive Noise Filter Control [NFILTERCON : b5h : 04h] 7 6 5 4 3 2 1 0 Enable 0 Manual Filter Coefficient 0 0 0 Automatic Filter Coefficient 0 1 0 Reserved 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 44 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Auto Exposure Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame Y mean value and target Y mean value. FFh AE Unlock Boundary [68h] AE Lock Boundary [67h] 80h AE Target [66h] AE Lock Boundary [67h] AE Unlock Boundary [68h] 0h Y Frame Mean AE Mode Control 1 [AEMODE1 : 70h : 29h] 7 6 5 4 3 2 1 0 UserDefined Time 0 AntiBanding Mode 0 AntiBanding Min. Break 1 Ae Window Enable 0 1 Time Speed 0 0 AE Mode 1 User-Defined Time This pin make user to be able to put starting value of the integration time. If it sets this pin to high and it writes the integration time, the exposure control is started with the written integration time. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 45 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing When Anti-Banding is enabled, AE initializes Integration Time registers[73h75h] to 2 x Anti-Banding Step value[7ah-7ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove banding noise caused by intrinsic energy waveform of light sources. Anti-Banding Mode Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. In this mode, AE operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. Therefore, this mode is recommended for only indoor use. When AE is still of out lock state despite that AE preamp analog gain update value exceeds preamp minimum gain value(18h) and integration time(73hAnti-Banding Min. Break 75h) is reached to AE Anti-Banding Step(7ah-7ch), integration time(73h-75h) is broken to less than AE Anti-Banding Step(7ah-7ch). AE window mode enables. With this bit set to high, window mode is AE Window Enable discarded and full image data is accounted for AE Y frame mean evaluation. Time Speed (fast)11 - 10 - 01 - 00(slow) 11 10 01 00 Gain-Only control mode. Only preamp gain is controlled to get optimum exposure state. Time-Only control mode. Only integration time is controlled to get optimum exposure state. Time-Gain control mode. Integration time and preamp gain are controlled to get optimum exposure state. AE function is disabled AE Mode AE Mode Control 2 [AEMODE2 : 71h : edh] 7 6 5 4 3 2 1 0 Gain Speed 1 1 1 Gain Speed 2 1 0 Time Fine Tune 1 Gain Fine Tune 1 Digital Gain Control 0 Analog Gain Control 1 Gain Speed1 This value means the speed of pre-amp. Gain changed when the environment condition moves rapidly from low luminance to high luminance. Gain update speed is specified as follows at the normal condition. (fast)11 - 10 - 01 - 00(slow) Integration time fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Amp gain fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Gain Speed2 Time Fine Tune Gain Fine Tune This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 46 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Digital Gain Control If this bit is high and Amp Gain register(17h) is less than Anti-Banding Gain Min(91h), digital gain controls the amplitude of Bayer raw data to prevent not to reach the saturation level.(very high luminance compensation) AE updates Amp Gain register(17h) in order to reach optimum exposure state Analog Gain Control AE Windows Weight [AEWINWGT : 72h : cdh] 7 6 5 4 3 2 1 0 Top window 1 1 Center window 0 0 Bottom window 1 1 0 Side window 1 Integration Time High [INTH: 73h : 02h] 7 6 5 4 3 2 1 0 0 0 0 Integration Time Higher 0 0 Integration Time Middle [INTM: 74h: 71h] 7 6 5 4 3 2 1 0 0 1 1 Integration Time Middle 1 0 Integration Time Low [INTL: 75h: 03h] 7 6 5 4 3 2 1 0 0 0 Integration Time Lower 0 0 0 Integration time value register defines the time which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera so that integration time needs to be increased in dark environment and decreased according to lighting condition. Maximum integration time is This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 47 2005 MagnaChip Semiconductor Ltd. (c) ! | 0 1 0 0 0 1 1) 0 1 1 (c) | | &% $# (c) | " ! (c) | | (c) | Value 00 01 10 11 Weight 1 1/4 1/8 1/16 Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing register maximum value(2 -1) x sensor clock period (SCP = 47.62ns, SCF = 21MHz) = 0.7989sec. 1) And the lower 2bit of Integration Tim[75h] is always masking as to "11", thus Integration time increase/decrease 4code step. SCF = Sensor Clock Frequency AE Target Outdoor[LUTARGET1 : 76h : 5ah] 7 6 5 4 3 2 1 0 24 0 1 0 AE Target Outdoor 1 1 0 1 0 AE Target Indoor[LUTARGET2 : 77h : 5ah] 7 6 5 4 3 2 1 0 0 1 0 AE Target Indoor 1 1 0 1 0 AE Lock Boundary [AELOCKFINEBND : 78h : f6h] 7 6 5 4 3 2 1 0 AE Fine Boundary AE Lock Boundary 1 1 1 1 0 1 1 0 AE Lock Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded, and instead AE Speed Unlock Boundary is used as Lock boundary. AE Fine Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which AE start to tune fine integration time or amp gain in order to goes into lock state smoothly. AE Unlock Boundary [AEUNLOCKBND : 79h : 2ah] 7 6 5 4 3 2 1 0 AE Unlock Boundary 0 0 1 0 1 0 1 0 AE Speed Boundary 0 specifies Y Frame Mean displacement from AE Target where integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In anti-banding mode, this boundary is used as lock boundary for exposure control. AE Anti-Banding Step High [AEINTSTEPH : 7ah : 01h] 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 Integration Step Higher 0 1 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 48 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing AE Anti-Banding Step Middle [AEINTSTEPM : 7bh : 38h] 7 6 5 4 3 2 1 0 0 0 1 Integration Step Middle 1 1 0 0 0 AE Anti-Banding Step Low [AEINTSTEPL : 7ch : 80h] 7 6 5 4 3 2 1 0 Integration Step Lower 1 0 0 0 0 0 0 0 AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled. Anti-Banding Step value is resolved by the following equation. Anti-Banding Step Value = Sensor Clock Frequency (SCF) / (2x power line frequency) The recommend value is set with SCF 21MHz, 60Hz power line, that is, Anti-Banding Step Value = 21MHz / (2 x 60) = 175000(dec) = 2AB98(hex) AE Integration Time Limit High [AEINTLIMITH : 7dh : 09h] 7 6 5 4 3 2 1 0 0 0 0 AE Integration Time Limit Higher 0 1 0 0 1 AE Integration Time Limit Middle [AEINTLIMITM : 7eh : c4h] 7 6 5 4 3 2 1 0 1 1 AE Integration Time Limit Middle 0 0 0 1 0 0 AE Integration Time Limit Low [AEINTLIMITL : 7fh : 00h] 7 6 5 4 3 2 1 0 AE Integration Time Limit Lower 0 0 0 0 0 0 0 0 These three registers define the maximum integration time value that is allowed to sensor operation. It is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding mode enabled. The recommend value is set to 5 frames per second with SCF set to 21MHz. 21MHz / 5 = 4200000(dec) = 401640(hex) This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 49 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Auto White Balance Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved. FFh AWVB White Pixel Boundary [77h] AWB Unlock Boundary [76h] AWB Lock Boundary [75h] 80h Cb/Cr Target [73h-74h] AWB Lock Boundary [75h] AWB Unlock Boundary [76h] AWB White Pixel Boundary [77h] 0h Cb/Cr Frame Mean AWB Mode Control [AWBMODE : 80h : 18h] 7 6 5 4 3 2 1 0 Reserved 0 Test Mode Enable 0 User Color Matrix Enable 0 AWB Enable 1 AWB Full Window Enable 1 AWB Speed 0 0 AWB Low Speed 0 This value is using at only simulation or test When this bit set to high, color matrix coefficient[CMA11~CMA33] is used for User Color Matrix Enable color space conversion matrix. And if this bit set to low, the equation from CCIR-601 is used. Test Mode Enable AWB Enable AWB Full Window Enable AWB Speed Auto White Balance Control Enabled With this bit set to low, AWB windows weight can be changed (Fast)11 - 10 - 01 - 00(slow) This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 50 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing AWB Low Speed With this bit set to high, analog gain speed is decreased to 1/4 of the normal speed AWB Windows Weight [AWBWINWGT : 82h : 00h] 7 6 5 4 3 2 1 0 Top window 0 0 Center window 0 0 Bottom window 0 0 Side window 0 0 Cb Frame Mean Value [CBTARGT : 83h : 80h] 7 6 5 4 3 2 1 0 Cb Frame Mean 1 0 0 0 0 0 This register defines Cb target frame mean value for AWB operation. Cr Frame Mean Value [CRTARGT : 84h : 80h] 7 6 5 4 3 2 1 0 Cr Frame Mean 1 0 0 0 0 0 This register defines Cr target frame mean value for AWB operation. AWB Lock Boundary [AWBLOCKBND : 85h : 04h] 7 6 5 4 3 2 1 0 AWB Lock Boundary 0 0 0 0 0 1 0 0 It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) value where AWB goes into LOCK state. Reserved AWB Unlock Boundary [AWBUNLOCKLBND : 86h : 20h] 7 6 5 4 3 2 1 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 51 2005 MagnaChip Semiconductor Ltd. | " (c) 0 0 0 0 | | ! | (c) Value 00 01 10 11 Weight 1 1/4 1/8 1/16 | Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing AWB Unlock Boundary 0 0 1 0 0 0 0 0 It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) where AWB is released from LOCK state. AWB operation retains LOCK state unless Cb/Cr frame mean values' displacement value exceeds this boundary. The value should be larger AWB Lock Boundary. AWB Cb White Pixel Boundary [CBWHITEBND : 87h : 30h] 7 6 5 4 3 2 1 0 0 0 1 AWB Cb White Pixel Boundary 1 0 0 0 0 AWB Cr White Pixel Boundary [CRWHITEBND : 88h : 30h] 7 6 5 4 3 2 1 0 0 0 1 AWB Cr White Pixel Boundary 1 0 0 0 0 AWB C Boundary [AWBCBND : 89h : 30h] 7 6 5 4 3 2 1 0 0 0 1 AWB C Boundary 1 0 0 0 0 AE State Machine [AEFSM : 8ch : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO AE Mode State AE Lock state AWB State Machine [AWBFSM : 8dh : RO] 7 6 5 4 3 2 1 0 reserved RO RO RO AE/AWB Lock RO Cb Lock State RO RO Cr Lock State RO RO Lu Frame Mean [LUFMEAN : 8eh : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Lu Frame Mean This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 52 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Cb Frame Mean [CBFMEAN : 8fh : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Cb Frame Mean Cr Frame Mean [CRFMEAN : 90h : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Cr Frame Mean Anti-Banding Gain Min [KLBNDMIN : 91h : 14h] 7 6 5 4 3 2 1 0 0 0 0 Anti-Banding Gain Min 1 0 1 0 0 Anti-Banding Gain Max [KLBNDMAX : 92h : 3dh] 7 6 5 4 3 2 1 0 0 0 1 Anti-Banding Gain Max 1 1 1 0 1 AWB White Pixel Boundary [AWBWHITE : 93h : ffh] 7 6 5 4 3 2 1 0 1 1 1 AWB White Pixel Boundary 1 1 1 1 1 AWB Black Pixel Boundary [AWBBLACK : 94h : 00h] 7 6 5 4 3 2 1 0 0 0 0 AWB Black Pixel Boundary 0 0 0 0 0 AWB Valid Number [AWBNUMBER : 95h : 02h] 7 6 5 4 3 2 1 0 0 0 0 AWB Valid Number 0 0 0 1 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 53 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Integration-Scan Plane Offset High [INTSCNOFSH : 96h : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Integration-Scan Offset High Integration-Scan Plane Offset Middle [INTSCNOFSM : 97h : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Integration-Scan Offset Middle Integration-Scan Plane Offset Low [INTSCNOFSL : 98h : RO] 7 RO 6 RO 5 RO 4 RO 3 RO 2 RO 1 RO 0 RO Integration-Scan Offset Low AWB Red Gain Maximum Value [AWBRGAINMAX : 9ah : 7f] 7 6 5 4 3 2 1 0 0 1 1 R/B Gain Maximum Value 1 1 1 1 1 AWB Red Gain Minimum Value [AWBRGAINMIN : 9bh : 00] 7 6 5 4 3 2 1 0 0 0 0 R/B Gain Minimum Value 0 0 0 0 0 AWB Blue Gain Maximum Value [AWBBGAINMAX : 9ch : 7f] 7 6 5 4 3 2 1 0 0 1 1 R/B Gain Maximum Value 1 1 1 1 1 AWB Blue Gain Minimum Value [AWBBGAINMIN : 9dh : 00] 7 6 5 4 3 2 1 0 0 0 0 R/B Gain Minimum Value 0 0 0 0 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 54 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing PLL Control Mode A [PCTRA : a0h : 01h] 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 VCO Power Down 0 PLL Power Down 0 Bypass Mode 1 VCO Power Down (Active High) PLL Power Down (Active High) Bypass Mode When VCO Power Down is active, VCO does not oscillate. For getting out of VCO Power Down, VCO initialization is required. When PLL Power Down is active, digital circuits of PLL do not operate and the charge pump circuit is disabled. Also Bypass Mode or Sleep Mode(SCTRB[4]) register is set to high, PLL goes into sleep. 0 PLL output clock is 1/F(ck). 1 PLL output clock is the same of PLL input clock. * VCO initialization To ensure the proper operation of the PLL, the activation of VCO initialization signal is required just after the deactivation of the VCO Power Down. During power-up sequence VCO initialization signal is recommended for more than 100ns. PLL Control Mode B [PCTRB : a1h : 1dh] 7 6 5 4 3 2 1 0 Post Divisor 0 0 0 1 1 The value of Post Divisor according to the output frequency Post Divisor Min 11 10 01 00 5MHz 10MHz 20MHz 40MHz F(ck) Reserved Charge Pump Bias 1 1 0 Max 12.5MHz 25MHz 50MHz 100MHz PLL Reference Divisor [PREFDIV : a3h : 01h] 7 6 5 4 3 2 1 0 0 0 0 PLL Reference Divisor 0 0 0 0 1 PLL Feedback Divisor High [PFDDIVH : a4h : 00h] This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 55 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 PLL Feedback Divisor High 0 0 0 0 PLL Feedback Divisor Low [PFDDIVL : a5h : 02h] 7 6 5 4 3 2 1 0 PLL Feedback Divisor Low 0 0 0 0 0 0 1 0 The operation frequency of PLL is related to the proportion of Reference(PREFDIV) to Feedback(PFDDIV) Divisor. F(ck) is actually determined by the following equation. F (ck ) = F (ref ) ( Feedback Divisor ) ( R eference Divisor ) F(ck) : frequency of output F(ref) : frequency of PLL input Feedback Divisor : PFDDIV[13:0] + 2 Reference Divisor : PREFDIV[7:0] + 1 Data Output Timing and Interface 14 ns ~ 15 ns M CLK V C LK HSYNC Y [7 :0 ] X Y0 Y1 Y2 4ns ~ 5ns As specified is the above data output timing diagram, the timing margin between video clock pin(VCLK) and data pins(Y[7:0]) is about 4n~5ns. This margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. To safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of VCLK. The above timing margin diagram represents 16bit output interface, but is also valid for 8bit output interface.. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 56 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Output Data according to Video Mode Output Data according to Video Mode is controlled by configuring Sensor Control A[01h]. Configurable options are specified again for your reference. < Video Mode Setting (@ MCLK 21MHz, PLL 2x) Format Mode SubSampling Mode (SCTRA[4]) * YCbCr 4:2:2 SCTRC[7] = 0h OUTFMT[3:0] = 0h * RGB 5:6:5 SCTRC[7] = 0h OUTFMT[3:0] = 4h SXGA SCTRA[3] = 0h SCTRA[1:0] = 3h VGA SCTRA[3] = 0h SCTRA[1:0] = 2h QVGA SCTRA[3] = 0h SCTRA[1:0] = 1h 4CIF SCTRA[3] = 1h SCTRA[1:0] = 3h CIF SCTRA[3] = 1h SCTRA[1:0] = 2h QCIF SCTRA[3] = 1h SCTRA[1:0] = 1h (don't care) ISP(0) Bayer(1) ISP(0) Bayer(1) O O O O O 42 21 21 10.5 10.5 15 15 28 15 55 O X O X O 21 X 10.5 X 5.25 (don't care) ISP(0) Bayer(1) ISP(0) Bayer(1) O O X O X 42 21 X 10.5 X 15 15 X 15 X X X X X X X X X X X Output timings for general configurations are described below. Slot named as "X" means that it is has no meaningful value and should be discarded. If a clock division(SCTRB[2:0]) is nothing(3'b000), VCLK is equal to MCLK in the case of PLL off, and twice of MCLK in the case of PLL 2x. Output data should be captured when VCLK is falling edge. If you have OUTINV = 0x01, should capture at the rising edge. SXVGA(Full), VGA(1/4), QVGA(1/16) Mode (Operating clock = MCLK, PLL off) 1. YCbCr 4:2:2 with 8bit output Register bit configurations : Sensor Control A : Full or Sub-sampling Mode Output Format : 8bit Output, Y First, Cb(Blue) First This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 57 2005 MagnaChip Semiconductor Ltd. Video Clock (MHz) Frame Rate ( 1fps) Bayer Output SCTRC[7] = 1h OUTFMT[3:0] = 0h Video Clock (MHz) Frame Rate ( 1fps) 15 X 28 X 56 X X X X X This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. v k g t kf u k g t gf e m k vt mf u m k t kf w w0# xe Y~ } | { z Y w x w x w u e i g vt i g t s s s rrrr qqqq pppp oooo s if gf e srrrr qqqq pppp | s o| o| s o| s o | u l k t kf v j i t jf ww0# xe Y x w w0# xe Y xx ww 0# e Y~~~~ }}}} |||| {{{{ 0# xe Y x w w x u v u e j i t h g t h g t if h f gf e w w zzzz yyyy xxxx wwww w w s s srrr qqq ppp ooo sqo r p | | | v n m t nf u n m t mf v l k t lf s h i r sg s h i p t s i r tg t s i p sg q h i r ' $ '($ % $ #" | ed c Yu V W V & ! (c) % b'3a 3 qg q h i p hg f T R 05 USQ | ))| 1111 ))| | F8 '''(& #!!" | e bb33 33Y '''' $$$$ ($$$$ %%%% $$$$ #" | (c) edddd cccc %%''a YXXXX WWWW VVVV '(& #!!" | (c) e a Y (& #" | (c) e %b'3 Y & (c) % b ' 3 aa 33 E F D @ D 8 C B @9 B 8 AB 9 @ 9 8 7 7 UT S R 05 Q 1 )| '(& #!" (c) (c)| ( #" | '''' $$$$ '($$$$ %%%% $$$$ #!!" (c) | '(&& #" (c) (c)(c)| '& ! (c) (c) 664334 4534 44 45542222 66 5 3 0| ))0| )) 1111 0| 0| C P @I P8 E P I@ I8 C H @G H8 E H G@ G8 C F @D 3. YCbCr 4:4:4 with 16bit output # e y w# xe xx xx xx xx wwww vvvv ww w# xe y w w# xe y w w x y d( d( d( ( d | |yyyy | | Sensor Control A : Full or Sub-sampling Mode Output Format : 16bit Output, Cb(Blue) First 2. YCbCr 4:2:2 with 16bit output Register bit configurations Register bit configurations : Sensor Control A : Full or Sub-sampling Mode Output Format : 16bit Output, Y First, Cb(Blue) First Confidential - 58 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing e s s s rrrr qqqq pppp oooo s s o| o| ss o| rrrr qqqq pppp | s o | | | hg f UTTTT RRRR 05555 UU S QQ0 U S 0 S Q0 SQ | 11 ))| p (c)u w e 8 tG r This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. (c) (c) (c)7 y y($ 7 d ydc y y d y d (c)7 ($ 7 ~ ~ ~ ~ }}}} |||| {{{{ c xxxx yyyy xxxx (c)7 y y($ 7 d ydc (c)7 y y($ 7 d ydc (c) v u t (e w s rki rih qki qih pk i pih oki oih nki (c)7 ( c ~ } | { (c)cz y x y y d yd nih mk i mih lki l ih jk i jih g g v t se wu (c)7 y y 7 (c) y y (c)7 7 (c) yyy xxx 7 y y 7 (c) (c) f d 4e 7 7 7 Sensor Control A :Full or Sub-sampling Mode i w(c)u e i (c)u v if g wu e p (c)u v pf i (c)u w e i (c)u v if h u w e )4' (c) $""dc (c) b| a (c)&&!(c)WW(c) 43 )4 (c) $"dc (c) b| a (c)!X)(c)3(c) 4 | )))) %%%% 4%%%% (c)&&&& %%%% $dc (c)|||| b a YYYY (c)&!X))(c)3(c)VVVV 4qqqq SSSS TTTT SSSS )4' (c) $dc (c) b| a (c)&!X(c)3WW(c) 43 ) '' " X)3 33 h vu g wu g vu e P(c) ! P RRQQ (c)II HH! hf e gf e (c) P(c) H$ R(c) P(c) H$ (c)QQQQ (c)IIII $5555 RR(c) P(c) H$ RPH 0 0 111 0 Gsr G9 8 tF r Fsr F9 8 tE r Esr E9 8 tD r Dsr D9 8 tC r Csr C9 ) % )4(% (c)& % $dc (c)| b aY (c)&!X)(c)3W(c)VU T S ' " | 3 tB r B s r A t r A s r t@ r @ s r 8 8 (c)Q (c)I H! RP 8 B9 8 A9 8 @9 8 8 R(c)Q I $5 PH 1 0 )'( (c) $#! | (c)| ( (c) $""#! || (c) )))) %%%% )(%%%% (c)&&&& %%%% $"#!|||| (c)|| )''( (c) $"#! (c) ) ' | | 4675(c)34 466675(c)34 5 3 47(c)42222 475(c)34 0( 0( 1111 ( 0( 0 5. RGB 5:6:5 with 16bit output 4. RGB 5:6:5 with 8bit output g v(c)u gf e Register bit configurations : Register bit configurations : Sensor Control A : Full or Sub-sampling Mode Output Format : 16bit Output, Cb(Blue) First, RGB5:6:5 Output Format : 8bit Output, Cb(Blue) First, RGB5:6:5 Confidential - 59 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing (c) w s( w s w s( vvv uuu ttt (eee e R P(c) ! RPH P(c) ! RQQQ (c)III HH! (c)Q (c)I $5 RPH 0 0 111 0 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. n h p h p p 3i n h q h q q i p h p p 3i o h o o 3i h 3e y h e d i 3e y i 3e d Fw8 F87 Ew8 E87 Dw8 D87 4CIF(Full) or CIF(1/4) Mode (Operating clock = MCLK, PLL off) n n i j j h v3 rrrb v3 b v3 rb 3uuuu tttt ssss b v h j 3i h v u t s "f r | e e 3 "!b ~~ } } X|| {{ zz a ww xx ww 3 "!b X e ea n n i l h l l 3i j h j j 3i h h v3 v 3 v3uuu ttt v v v uuuu tttt v r rb sss b rb r" r" ssss "ffff r" r | | | | n h n n i m h m m 3i 3 "! | a X 3ea 3 "! | a X e 3ea 3 "! | a~~~~ }}}} X|||| {{{{ zzzz 3ayyyy xxxx wwww 3 "! | a X ee 3ea e e l l k j j k h h v rb v rb v rb uuuu tttt ssss b v r l 3i h i k h j 3i h h uuuu ssss rr|ffff v t r| vv t | t | vtr | | | | h 3 ! 3X| 3 ! 3X| 3 ! 3X| 3 ! 3X| g& e( g& e( g& e( &ffff (dddd g e | f (e y f e d c h (e y h e d g (e y 3e d g ' # '3# $ # ! a Y XW V U ap R S R % (c) $ '2 2 f (e y c I Gb Q I b I GGGb QQPPPP HHHH b QI f e d c Q 3P I H "4 G )| ) 000 | )| '3% 3 "!b ' ''' ### '3### $$$ ### "!b %% "!b v t sB v t sB Aw8 A87 @w8 @ 8 7 3a $XW2 3 (c) 3(c)(c)a $XW''2 3 $ W'2 2 3a YYY XVVV UUU 322TTT SSS RRR Ar 9 8q Fr 9 7 q 6 6 I Gb Q I Gb I Gb QQPPPP HHHH b QIG QI P H G|4 0 | ) Cw8 C87 Bw8 B87 ' # (&# $ # "! (c)| '% 542 &31 ))|| 000 || )|| 1. YCbCr 4:2:2 with 8bit output 6. RGB 4:4:4 with 16bit output Register bit configurations : Register bit configurations : Sensor Control A : CIF Mode, Full or Sub-sampling Mode Sensor Control A : Full or Sub-sampling Mode Output Format : 16bit Output, Cb(Blue) First, RGB4:4:4 Confidential - 60 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing c I Gb Q I b I GGGb QQPPPP HHHH b QI Q3 G" Q3 G" Q3 G" 3PPPP IIII HHHH "4444 Q G )| )| 0000 | )| ) F r 9 w u t s9 D r 9 u8 t sB xw8 987 This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. l fj g l f hfl g j g h g k j g k hk g j g l fj g l f hfl g j g h g k j g k hk g j g h g i j g i h g Q Q QYYYY Q i @ @ @ @ yy xxYY YYY rTq G uuQ srT h fG uQ rTqqq hhYY ffG Q G G tw tw tw tw wwww vvvv tttt ssss tu tu tu tu ssTpppp iiii cccc cccc eeee gd gd gd gd Geeee hgd hgd hgd hgd Q wwww ssss Gaaaa YYYY sr h YY fu G h g i j g i h g Q Q QYYYY Q i @ @ @ @ y xY YYYY ssT YY ff bb tw tw tw tw wwww vvvv tttt ssss tu tu tu tu sTqqpppp iiii cccc hcccc eeee gd gd gd gd eeee dddd ccbbaaaa YYYY XXXX srrT h ff rTq h c r q h YY c Y y b xY W 6 3UV 1V 4 UV 3 1U W W W W 6 378 18 4 78 3 7 1 W W W 0 6 3UV 1V 4 UV 3 1U 0 0 0 0 6 378 18 4 78 3 7 1 0 T G !Q T G !Q T G !Q G E ''G E #### #### """" !!!! T |||| (c) (c) (c) (c) GSSSS (c)R (c)R (c)R (c)R QPPPP #### '''' IIII HHHH ''GFFFF ! G E E 0 0 0 6 5 32 5 1 45 23 12 0 0 9@ 9@ DDDD BC BC BC BC AAAA @(((( 9@ 9 $$ %%%% $$ #### #### """" !!!! |||| (c) (c) (c) (c) |||| )))) (((( '''' &&&& $ $ %%%% $ $ 3. YCbCr 4:4:4 with 16bit output 2. YCbCr 4:2:2 with 16bit output Register bit configurations : Output Format : 16bit Output, Cb(Blue) First Sensor Control A : CIF Mode, Full or Sub-sampling Mode Output Format : 8bit Output, Y First, Cb(Blue) First Output Format : 16bit Output, Y First, Cb(Blue) First Register bit configurations : Sensor Control A : CIF Mode, Full or Sub-sampling Mode Confidential - 61 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing W 6 5 32 5 1 45 23 12 0 0 9@ 9@ DDDD BC BC BC BC AAAA @(((( 9@ 9 $$ %%%% $$ This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. d l l k k j j i i h h g g f f e e d d 5 y d x u x w u t v u tq p d |d f he @ ih vD x t @b sr i g a l l k k j j i i h h g g f f e e d d 5 yy yy x u x w u t v u tsrq p d |d f he f e dc|b Y i g a y y cccc y y Output Format : 8bit Output, Cb(Blue) First, RGB5:6:5 Sensor Control A : CIF Mode, Full or Sub-sampling Mode W G3 V 2 G3 UX V U W V TX V T W V SX V S W V RX V R W V QX V Q W V PX V P W V IX V I W V HX V H W V G X V G W V 3X V 3 W V U2 1 T2 1 S2 1 R2 1 Q2 1 P2 1 I2 1 H2 1 G2 1 32 1 1 1 4D 4D 9999 78 78 78 78 6666 D 4D 4 4 99 78 78 66 5)) 45 & % 0)(' W G3 V 2 G3 | @ ""D | @ D @ ((@ $$$$ !!!! $$$$ #### !!!! """" !!!! | (c)(c)(c)(c) @FFFF E E E E DCCCC $$$$ (((( BBBB AAAA ((@ | @ "D " @ 1 UX V U W V TX V T W V SX V S W V RX V R W V QX V Q W V PX V P W V IX V I W V HX V H W V G X V G W V 3X V 3 W V 9 78 6 D 4 1 U2 1 T2 1 S2 1 R2 1 Q2 1 P2 1 I2 1 H2 1 G2 1 32 1 45 45 9999 78 78 78 78 6666 5)))) 45 4 %% &&&& %% 0000 )))) (((( '''' | | | | $$$$ !!!! $$$$ #### !!!! """" !!!! | (c)(c)(c)(c) (c)(c)(c)(c) | | | 0000 )))) (((( '''' % % &&& % 5. 4. RGB 5:6:5 with 8bit output RGB 5:6:5 with 16bit output Register bit configurations : Register bit configurations : Output Format : 16bit Output, Cb(Blue) First, RGB5:6:5 Sensor Control A : CIF Mode, Full or Sub-sampling Mode Confidential - 62 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. k jl jk j li i ki hl hk gl gk fl fk h g f le k jl jk j li i ki hl hk gl gk fl fk h g f X IH G G IH F WX G WGF VXG V FG UXG U FG TXG TGF SGF XS G X IH G G IH F WX G WGF VXG V FG UXG U FG TXG TGF SGF XS G QCIF(1/16) Mode (Operating clock = MCLK, PLL off) e ek dl dk l d t3sD i g8 v 3sDrr ii g8 v 8 8 ux ux ux ux xxxx wwww uuuu tttt vvvv uuuu t3Drqqqq pppp dddd dddd ffff he he he he 8 ih ih ih ih xxxx tttt 8 ab ab ab ab t3sDr g8 v ts i gv 8 le e k d l d k l k l k l k e d 3 3 3 3 yyyy ttt rrr gg c ux ux ux ux xxxx wwww uuuu tttt vvvv uuuu ssss qqqq pppp id id id id dddd ffff he he he he ffff eeee dd ab ab ab ab YYYY t r c g dc g dc yyyy cccc RX G RGF QX G QGF RX G RGF QX G QGF !3D 8 # 3D 8 # )8 )8 "% "% "% "% %%%% $$$$ """" !!!! #### """" !3D |||| |||| (c)(c)(c)(c) 8CCCC B B B B AAAA %%%% )))) @@@@ 9999 !!!! 8 !3D 8 # ! # )8 ) PX G IXG HX G EE 7 56 4 2 PGF I FG HGF EE 7 56 4 30 2 '''' &&&& 1111 0000 )))) (((( !!! "% "% "% "% %%%% $$$$ """" !!!! #### """" | | | | |||| (c)(c)(c)(c) (c)(c)(c)(c) || ! | | 10)( '''' &&&& 6. RGB 4:4:4 with 16bit output PX G PGF Register bit configurations : Register bit configurations : Output Format : 8bit Output, Y First, Cb(Blue) First Sensor Control A : CIF Mode, Bayer Sub-sampling, 1/16 Sub-sampling Mode Output Format : 16bit Output, Cb(Blue) First, RGB4:4:4 Sensor Control A : CIF Mode, Full or Sub-sampling Mode Confidential - 63 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing k l k l k 3 3 3 3 yyyy IXG I FG HX G HGF E E E E 23 23 7777 56 56 56 56 4444 30000 23 2 '& This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. 8bit/16bit raw or gamma-corrected Bayer output When Bayer output mode is selected, Window Width x Window Height raw image data is produced with the following sequence. After VSYNC goes low state, the first HSYNC line of a frame is activated with B pixel data appearing first when both of Column Start Address and Row Start Address are even. 7 G T G V F T VF 7 GUT FUT eeee eeee 7 E TU VE U DVU DUT 7 7 7 7 7 hV U h TU 7 7 7 7 7 7 7 G V U G U T F V U F TU ee 7 7 Ah @ 7 7 C @DE 7 7 GC @ G A @ FC @ F A @ 7 7 7 Bd 8 Bc 8 7 eeee eeee EA @ 8G 7 C @FG eeee eeee 8G DC @ 8F A FG @ 8F DA @ 7 Ch @ 7 E8 EC @ E A @ DC @ D A @ 7 7 8G 8F 7 7 gC @ 8D 8E A DE @ 8D Ag @ 7 BC @ 7 B8 7 Bayer Data Format (Operating clock = MCLK, PLL off) Output Format is controlled by configuring Sensor Control C(SCTRC) and Format(OUTFMT) register. Configurable options are specified again for your reference. TE E TU EV DT DV DUT 7 gVU gUT VE U E U T D V U D U T 7 Confidential - 64 - 2005 MagnaChip Semiconductor Ltd. HV7161SPA2 CMOS Image Sensor With Image Signal Processing Output 7 7 7 7 BVU B TU 7 7 7 7 7 7 7 BA@ 7 7 2 2 666 45 45 45 333 2 BT BV 9T 9V 7 7 BU 9U 77 2 66 45 45 33 !00 2! '& ! PY! PY "% "% %% $$ "" ## "" ! 4P 4P 4P 4P !XX WW 9VU 77 2 2 6666 45 45 45 45 3333 2 2 9UT 77 2! 2! 6666 45 45 45 45 3333 !0000 2! 2 '& "% % $ " "# ! " H b f R 4 4b !X W Y B V U B TU 9 V U 9 U T 7 7 2! 2! 6666 45 45 45 45 3333 !0000 2! 2 '''' &&&& "% % $ " "# " H S R 4 4b a!X W Y B C @ B A @ 9C @ 9 A @ 7 7 6 45 3 2 B8 89 77 2! 2! 6666 45 45 45 45 3333 !0000 2! 2 '''' &&&& 9C @ 9 A @ "% "% "% "% %%%% $$$$ """" 7 #### """" 4P 4P 4P 4P 4P 4P 4P 4P PPPP IIII HHHH 0000 7 2! 2! 6666 45 45 45 45 3333 !0000 2! 2 89 77 '''' &&&& ! ! RRR "% "% "% "% %%%% $$$$ """" #### """" ! " " " " HHHH bbbb ffff 4Q 4Q 4Q 4Q 4Q 4Q 4Q 4Q PPPP IIII HHHH 0000 ! R 2! 2! C B @9 B 8 AB 9@ 89 7 7 6666 45 45 45 45 3333 !0000 2! 2 '''' &&&& ! ! "% "% "% "% %%%% $$$$ """" #### """" ! " " " " HHHH SSSS RR 4Q 4Q 4Q 4Q 4Q 4Q 4Q 4Q PPPP IIII HHHH 0000 ! R R 10)( ! "% "% %% $$ "" ## "" ! | | || (c)(c) || 10)( '& Full(SXGA) 1280 960 1/4(VGA) 640 480 1/16(QVGA) 320 240 4CIF 704 576 CIF 352 288 QCIF 176 144 Note: The 'Width' means the number of VCLK during HSYNC is active high and the 'Height' means the number of HSYNC during VSYNC is active low. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. TG TG SI SI SG SG RI RI RG RG QI QI QG QG PI PI ( ' $& V W#$" ! U Y A (c) | X V V TG SI SG RI RG QI QG PG HI i gd eq d c i gh d ef d c A @A A PI PG HI HG F EEEE CD CD CD CD BBBB @@A8888 @ 5555 4444 $ VVW$ U (((( '''' $&&&& VVVV VVW##$"""" !!!! U (c)(c)(c)(c) |||| $ W$ U $ W#$ U # HG F QI QG PI PG ) A %#$ U t A %$ U ts A %###$ U tss 3333 2222 1111 0000 (((( '''' A&&&& %$"""" !!!! U trrrr uuuu (c)(c)(c)(c) |||| )) ) s HI HG F TG SI SG RI RG QI )U )U A t###$ U Y At A t$ U Y At 3333 2222 1111 0000 U (((( '''' A&&&& t$"""" !!!! U Y Atssss rrrr (c)(c)(c)(c) |||| )U ) A t#$ U Y At i gh d ef d p i gh d ef d c QG PI PG HI HG F E CD B A8 @ 4 4 555 4 ) ) $ %#$ # 333 222 111 000 ((( ''' $&&& %$""" !!! (c)(c)(c) ||| ) $ %#$ 9999 8888 7777 6666 4 4 5555 4 4 Window mode and image size PG PG HI HI b H a Q H G b R a PH H G F Mode Confidential Width - 65 - 2005 MagnaChip Semiconductor Ltd. Height HV7161SPA2 CMOS Image Sensor With Image Signal Processing v F @$ @$ EEEE CD CD CD CD BBBB $ @$ @ A @A A EEEE CD CD CD CD BBBB @@A8888 @ Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing I2C Chip Interface The serial bus interface consists of the SDA(serial data) and SCK(serial clock) pins. HV7161SP sensor can operate only as a slave. The SCK only controls the serial interface. However, MCLK should be supplied and RESET should be high signal during controlling the serial interface. The Start condition is that logic transition (High to Low) on the SDA pin while the SCK pin is at high state. The Stop condition is that logic transition (Low to High) on the SDA pin while the SCK pin is at high state. To generate Acknowledge signal, the Sensor drives the SDA low when the SCK pin is at high state. Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an Acknowledge. The most significant bit of the byte should always be transmitted first. SDA SCK START MSB LSB 1 2 8 9 ACK 1 2 8 9 ACK STOP Register Write Sequences One Byte Write S *1 22H *2 A *3 01H *4 A *5 03H *6 A *7 P *8 Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Video Mode : SXGA] *7. Read: acknowledge from sensor *8. Drive: I2C stop condition Multiple Byte Write using Auto Address Increment S *1 22H *2 A *3 76H *4 A *5 70H *6 A *7 70H *8 A *9 P *10 Set "LuTarget1, LuTarget2" register as 70H, 70H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 66 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing *4. Drive: 76H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 70H [LuTarget1] *7. Read: acknowledge from sensor *8. Drive: 70H [LuTarget2] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition Register Read Sequence S *1 22H *2 A *3 50H *4 A *5 S *6 23H *7 A *8 Data of 50H *9 A P *10 *11 Read "Gamma Slope 6" register from HV7161SP *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 50H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read "Gamma Slope 6" from sensor *10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition AC/DC Characteristics Absolute Maximum Ratings Symbol Vpp:ph Vpp:p Vipp Top Tst Parameter I/O and pixel block supply voltage Internal analog and digital supply voltage Input signal voltage Operating Temperature Storage Temperature Units Volts Volts Volts C C Min. -0.3 -0.3 -0.3 -10 -30 Max. 3.62 2.5 3.3 50 80 Caution: Stresses exceeding the absolute maximum ratings may induce failure. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 67 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing DC Operating Conditions Symbol Vdd:ph Vdd:p Vih Vil Voh Vol Iih Iil Ta Parameter I/O and pixel block supply voltage Internal analog an digital operation supply voltage Input voltage logic "1" Input voltage logic "0" Output voltage logic "1" Output voltage logic "0" Input High Current Input Low Current Ambient operating temperature Units Volt Volt Volt Volt Volt Volt uA uA C -10 -10 -10 25 2.4 0.4 10 10 50 Min. 2.3 1.6 2.0 0.8 Typ. 2.5 to 2.8 1.8 Max. 2.9 2.0 30[pF] 30[pF] 30[pF] 30[pF] 30[pF] 30[pF] Load[pF] AC Operating Conditions Symbol MCLK SCK 1. 2. 3. 2 Parameter Main clock frequency I C clock frequency Max Operation Frequency 21 400 Units MHz KHz Notes 1,2 3 MCLK may be divided by internal clock division logic for easy integration with high speed video codec system. Frame Rate : 15 frames/sec at 21Mhz, HBLANK = 208, VBLANK = 8 SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section Output AC Characteristics All output timing delays are measured with output load 30[pF]. Output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, video output signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 68 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing V C LK HSY NC Y /C [7:0] X D a ta 0 D ata 1 D ata 2 D ata 3 6 ns I2C Bus Timing s to p s ta rt s ta rt s to p SDA tr tb u f tf tlo w th d ;s ta SCK th d ;s ta th d ;d a t t h ig h ts u ;d a t ts u ;s ta ts u ; s to Parameter SCK clock frequency Time that I C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of SCK/SDA 2 Symbol f sck tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb Min. 0 1.2 1.0 1.2 1.0 1.2 0.1 250 1.2 - Max. 400 300 300 - Unit KHz us us us us us us ns ns ns us pf This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 69 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Electro-Optical Characteristics Parameter G Sensitivity Dark Signal Saturation Dynamic range SNR Units mV / lux sec Code Code dB dB ) 1) Min. Typ. 1700 2.13 190 48 Max. Note 0 ~ 255 0 ~ 255 40 51 73 95 Note 1). Others except power consumption are tested under below electro-optical test condition, and the power consumption is tested under default operating condition at MCLK 25MHz and PLL off. Parameter G Sensitivity Dark Signal Saturation Dynamic range SNR DC and AC conditions Description preamp gain = 2x, R/G/B gain = 1x, 30lux, integration time @ 128code preamp gain = 2x, R/G/B gain = 1x, 1/10sec, 0lux preamp gain = 1x, R/G/B gain = 1x, 1/10sec, 100lux (Temperature = 30 Internal 1.8V and 2.6V, and I/O 2.6V@ MCLK 25Mhz, PLL off - Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used. This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 70 2005 MagnaChip Semiconductor Ltd. (Temperature = 30 Electro-Optical Test Condition (Temperature = 50 Power Consumption (25 mW ) Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing Typical Application This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 71 2005 MagnaChip Semiconductor Ltd. Confidential HV7161SPA2 CMOS Image Sensor With Image Signal Processing CLCC Package Specification MagnaChip Semiconductor Ltd. System IC SP Div. * Contact Point * CIS Marketing Team 15Floor, MagnaChip Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea Tel: 82-2-3459-5579 Fax: 82-2-3459-5580 E-mail : suyeon.moon@MagnaChip.com This document has a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 72 2005 MagnaChip Semiconductor Ltd. |
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