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ee FAS366U h aSFast Architecture SCSI Processor t
Data Sheet
H H H H H H H H H H H
Support for hot plugging Target and initiator block transfer sequences Bus idle timer Split-bus architecture Pipelined command structure On-chip, single-ended SCSI transceivers (48-mA drivers) Initiator and target roles Active negation 16-bit recommand counter Differential mode SCSI bus reset watchdog timer
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QLogic Corporation
Features
H Compliance with ANSI draft Fast-20 standard H Compliance with ANSI X3T10/855D SCSI-3 H Compliance with ANSI SCSI configured H Sustained SCSI data transfer rates of up to: h 40 Mbytes/sec synchronous (ultra and wide H Synchronous DMA timing; DMA speed of
50 Mbytes/sec deassertion control automatically (SCAM) protocol levels 1 and 2 parallel interface (SPI) standard
h 14 Mbytes/sec asynchronous (wide SCSI)
SCSI)
H REQ and ACK programmable assertion and
DB BUS
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PAD BUS
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SCSI DATA PARITY (2) DATA (16) BLOCK REGISTERS
FIFO
COMMAND
RECOMMAND COUNTER TRANSFER COUNT SEL/RESEL BUS ID SEL/RESEL TIMEOUT TRANSFER COUNTER
INTERRUPT
STATUS SEQUENCERS SEQUENCE STEP
SYNC PERIOD SYNC OFFSET/ SYNC ASSERT/ SYNC DEASSERT CLOCK CONVERSION CONFIGURATION TEST (SCAM)
SCSI CONTROL
Figure 1. FAS366U Block Diagram
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FAS366U
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QLogic Corporation
Product Description
The FAS366U is a new addition to the QLogic fast architecture SCSI processor (FAS) chip family. The FAS366U supports advanced SCSI-3 options including ultra SCSI synchronous transfers. Also included is the advanced SCAM level 2 SCSI controller core. The FAS366U is a single-chip controller for use in host and peripheral applications. It is firmware and pin-out compatible with the QLogic FAS366 chip. The FAS366U block diagram is shown in figure 1. The FAS366U implements QLogic's new SCSI target and initiator block transfer sequences. The block sequences reduce firmware overhead and are composed of the following new commands: Target Block Sequence (including the bus idle timer), Initiator Block Sequence, Load/Unload Block Registers sequences, Abort Block Sequence, and Disconnect Abort Block Sequence. The FAS366U supports both single-ended and differential mode SCSI operations and operates in initiator and target roles. The FAS366U has been optimized for interaction with a DMA controller and the controlling microprocessor. The versatile split-bus architecture supports various microprocessor and DMA bus configurations. A separate 8-bit microprocessor bus (PAD) provides access to all internal registers, and a 16-bit DMA bus (DB) provides a path for DMA transfers through the FIFO. Each bus is protected by a parity bit (byte-wide parity) to improve data integrity. During data transfer, the microprocessor has instant access to status and has the ability to execute commands.
drivers onto the DMA bus. The chip select role of DACK helps support the burst timing of fast DMA mode. DACK selects the FAS366U after DREQ is asserted and is removed either after DREQ is deasserted or when the DMA transfer is paused. DBRD requests data from the FAS366U and DBWR validates data sent to the FAS366U. Data is valid around the rising (trailing) edge of DBRD or DBWR. DMA transfers are terminated by deasserting DREQ. Deassertion of DREQ is triggered by the leading edge of DBRD or DBWR (see timing parameter t1 in figures 2 and 3) under any of the following conditions: H To prevent FIFO overrun conditions H To prevent FIFO underrun conditions H When the required amount of data has been transferred When DREQ is deasserted, the FAS366U ignores DBRD and DBWR. Data transfers do not take place unless DREQ is asserted. The FAS366U does not generate parity on the incoming DMA bus. Correct parity must always be supplied with the data. The DMA interface signals are given in table 1. DMA timing is given in table 2 and figures 2 and 3. Table 1. DMA Interface Signals
SCAM Implementation
The FAS366U supports levels 1 and 2 of the SCAM protocol. Refer to the latest revision of X3T10/855D, Annex B. The SCAM protocol requires direct access and control over the SCSI data bus and several of the SCSI phase and control signals. The majority of the SCAM protocol can be implemented in firmware at microprocessor speeds. The following SCAM features are supported in the hardware:
H Arbitration without an ID H Slow response to selection with an unconfirmed ID H Detection of and response to SCAM selection
Fast DMA Protocol
The fast DMA protocol is required for supporting the full bandwidth of ultra, wide SCSI. The DREQ signal initiates DMA transfers and runs asynchronous to the user's clock. For read operations, DACK acts as a chip select to enable the FAS366U
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FAS366U
A A AAAAAAAAAAAAAAAA A AA A AA AAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA AAAAAAAA A A A A AA AA AAAAAAAAAAAAAAA AAAAAAAAA AA A AAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAA AAAAAAAA A A A AAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAA A A A A AAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AAAAAAAAA AA
Pin Type O Active Level High Description DREQ The FAS366U DMA request line begins and ends DMA cycles. DACK I Low The acknowledge is used as a chip select to activate FAS366U drivers and to acknowledge acceptance of DREQ. DBRD I Rising edge The trailing edge accepts data from the FAS366U for DMA read operations. The trailing edge strobes data into the FAS366U FIFO on DMA write operations. DBWR I Rising edge DB15-0 I/O N/A This is the DMA data bus.
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AA A A AAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A
Symbol tW7 tW6 tW5 tW4 tW3 tW2 tW1 tR9 tR8 tR7 tR6 tR5 tR4 tR3 tR2 tR1 t3 t2 t1 DB15-0 write hold from DBWR high DB15-0 write setup to DBWR high DBWR low to DBWR low cycle DBWR high to DACK high DBWR deassertion pulse width DBWR assertion pulse width DACK low to DBWR low DBRD low to DB15-0 read invalid DBRD low to DB15-0 read valid DACK high to DB15-0 read off DACK low to DB15-0 read on DBRD low to DBRD low cycle DBRD high to DACK high DBRD deassertion pulse width DBRD assertion pulse width DACK low to DBRD low DACK high to DACK low DACK high to DREQ high DBRD/DBWR low to DREQ low Description
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Table Notes aDREQ loading is 30 pf. bDBRD low to DACK highwtR5 cData loading is 50 pf. dDBWR low to DACK highwtW5
Table 2. DMA Timing
Minimum (ns)
TBD
tW3
tW5
tR3
tR5
10
40
15
15
40
15
15
40
5
0
2
Maximum (ns)
15
15
12
Note
FAS366U
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b
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QLogic Corporation
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QLogic Corporation
DREQ DACK
DBRD
DB15-0
Figure 2. DMA Read Cycle
DREQ DACK
DBWR
DB15-0
Figure 3. DMA Write Cycle
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FAS366U
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QLogic Corporation
Interfaces
The FAS366U interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces and other chip operations are shown in figure 4.
FAS366U
A3-0 MICROPROCESSOR INTERFACE CS INT PAD7-0 PADP PAUSE RD WR 42-45 13 3 92-97, 99, 100 91 10 14 15 58 62 61 33 31 56 32 57 SEE NOTE 75, 63 DACK DMA AND MICROPROCESSOR INTERFACE DB15-0 DBP1-0 DBRD DBWR DREQ 9 SEE NOTE 127, 117 4 5 8 11 47 39 20 RESETI RESET RESETO 38 2 1 SEE NOTE 86, 48 36 CLOCK CLK 19 88 MODE1-0 DIFFM DIFFSENS EBSY EIGS ERST ESD15-0 ESDP1-0 ESEL ETGS DIFFERENTIAL MODE SUPPORT 55 ACK ATN BSY CD IO MSG REQ RST SD15-0 SDP1-0 SEL SCSI INTERFACE
POWER AND GROUND
VDD VSS
41, 40 SEE NOTE SEE NOTE SEE NOTE
BUS CONFIGURATION
NO CONNECT
NOTE:
DB15-0 ESD15-0 NO CONNECT SD15-0 VDD VSS
= = = = = =
126-122, 120-118, 116, 115, 113-108 101-104, 21-24, 49-52, 82-85 16, 37, 53, 60, 67, 90, 105 76, 78-80, 26-28, 30, 64, 65, 68-70, 72-74 7, 12, 17, 35, 87, 106 6, 18, 25, 29, 34, 46, 54, 59, 66, 71, 77, 81, 89, 98, 107, 114, 121, 128
Figure 4. FAS366U Functional Signal Grouping
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FAS366U
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QLogic Corporation
Packaging
The FAS366U is available in a 128-pin plastic quad flat pack (PQFP). The pin diagram for this package is illustrated in figure 5. The FAS366U package dimensions are shown in figure 6.
VDD ESDP1 ESD14 ESD15 PADP ESD0 ESD1 ESD2 ESD3 VSS SD12 SDP1 PAD0 PAD1 VSS PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 SD13 SD14 VSS SD15 VSS SD2 VSS VSS
CLK
SD0 SD1
SD3 SD4
102 101
100 99
98 97
96
95
94
93
92 91
90 89
88 87
86 85
84 83
82 81
80 79
78 77
76 75
74 73
72 71
70 69
68 67
SD5 NC
ESD13 ESD12 NC VDD VSS DB0 DB1 DB2 DB3 DB4 DB5 VSS DB6 DB7 DBP0 DB8 DB9 DB10 VSS DB11 DB12 DB13 DB14 DB15 DBP1 VSS
103 104 105 106 107 108 109 110 111 112 113
66 65 64 63 62 61 60 59 58 57 56 55 54
SD6
NC
SD7 SDP0 ATN BSY NC VSS ACK RST MSG SEL VSS NC ESD4 ESD5 ESD6 ESD7 ESDP0 DIFFSENS VSS A0 A1 A2 A3 MODE1 MODE0 EBSY
114 115 116 117 118
FAS366U
119 120
121 122 123 124 125 126 127 128
RESETO
ESD11 ESD10
DIFFM
ETGS
SD11 SD10 SD9
EIGS
IO REQ
INT
RD WR NC
CS
DBWR VSS VDD DREQ
RESETI
NC = NO CONNECT
DACK PAUSE
DBRD
Figure 5. FAS366U Pin Diagram
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FAS366U
NC ERST
VDD VSS
VSS
VSS
CD VSS
SD8
ESD9 ESD8
ESEL
VDD
VDD
A A A A A A A A A A A A A A A A A A A A A A A
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA
1 2
9 10 11
12
13 14
15 16
17 18
19
20 21
22
23 24 25
26 27
28 29
30 31 32
33
34 35
36
37 38
3
4
5 6
7 8
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QLogic Corporation
23.2 " 0.25 PIN 102 PIN 103 20.00 PIN 65 0.18 " 0.05 PIN 64 17.2 " 0.25 14.00 INDEX MARK PIN 39 0.8 " 0.15 1.6 REF PIN 128 DETAIL A PIN 1 PIN 38 NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. 0.5 " 0.1 0.23 " 0.05 0.3 + 0.1 -0.05 4_ TYP 2.8 TYP 3.4 MAX A
Figure 6. FAS366U Mechanical Drawings
Electrical Characteristics
Table 1. Operating Conditions
Symbol VDD IDDa IDDb TA Description Supply voltage Supply current (static IDD) Supply current (dynamic IDD) Ambient temperature 0 Minimum 4.75 Maximum 5.25 TBD TBD 70 Unit V mA mA
oC
Table Notes Conditions not within the operating conditions but within the absolute maximum stress ratings may cause the chip to malfunction. aStatic IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, and all bidirectional pins configured as inputs. bDynamic IDD is dependent on the application.
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FAS366U
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QLogic Corporation
Specifications are subject to change without notice. QLogic is a trademark of QLogic Corporation.
EJuly 14, 1995 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
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FAS366U
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