 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Ordering number : EN6015 CMOS IC LC78622NE Compact Disc Player DSP Overview The LC78622NE is a CMOS IC that implements the signal processing and servo control required by compact disc players. At the same time as providing an EFM PLL circuit, a 1-bit D/A converter, and an analog low-pass filter the LC78622NE realizes an optimal costperformance tradeoff for low-end players by strictly limiting functionality to basic signal-processing and servo system functionality. The LC78622NE signal-processing system provides demodulation of the EFM signal from the pickup, de-interleaving, error detection and correction, and digital filters that can prove useful in reducing the cost of end products. The LC78622NE servo control system processes servo commands sent from the control microprocessor. The LC78622NE is an improved version of the LC78622E that adds 8x oversampling digital filters, three generalpurpose output ports (that also have specific shared functions) and the PCCL pin (pin 34). However, some handling of general-purpose ports differ from that of the LC78622E, therefore care must be taken.(Refer to pages 16 and 21). * * * * * * * * Functions * Input signal processing: The LC78622NE takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. * Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator * Disk motor speed control using a frame phase difference * * * * * signal generated from the playback clock and the reference clock Frame synchronization signal detection, protection and interpolation to assure stable data readout EFM signal demodulation and conversion to 8-bit symbol data Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor Subcode Q signal output to a microprocessor over the serial I/O interface after performing a CRC error check (LSB first) Demodulated EFM signal buffering in internal RAM to handle up to 4 frames of disk rotational jitter Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) Sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a dual-interpolation scheme. The previous value is held if the C2 flags indicate errors two or more times consecutively. Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) Built-in digital output circuits. Arbitrary track counting to support high-speed data access D/A converter outputs with data continuity improved by 8x oversampling digital filters. Built-in third-order D/A converters (An analog lowpass filter is built in.) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 11999RM (OT) No. 6015-1/31 LC78622NE * * * * Built-in digital attenuator (8 bits - alpha, 239 steps) Built-in digital de-emphasis Zero cross muting Supports the implementation of a double-speed dubbing function. * Support for bilingual applications. * General-purpose I/O ports: 5 pins Package Dimensions unit: mm 3159-QFP64E [LC78622NE] 1.0 1.6 1.0 48 49 32 0.8 17.2 14.0 0.35 33 1.6 1.0 0.15 Features * 5 V single-voltage power supply 17.2 14.0 0.8 17 1.0 64 1 16 3.0max 0.8 0.1 2.7 15.6 SANYO: QFP64E (QIP64E) Equivalent Circuit Block Diagram No. 6015-2/31 LC78622NE Pin Assignment Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -20 to +75 -40 to +125 Unit V V V mW C C No. 6015-3/31 LC78622NE Allowable Operating Ranges at Ta = 25C, VSS = 0 V Parameter Symbol VDD (1) Supply voltage VDD (2) VIH (1) VIH (2) VIL (1) Input low level voltage VIL (2) Data setup time Data hold time High level clock pulse width Low level clock pulse width Data read access time Command transfer time Subcode Q read enable time Subcode read cycle time Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Operating frequency range Crystal oscillator frequency tSU tHD tWH tWL tRAC tRWC tSQE tSC tSE tCSU tCHD tRCQ tCDD VIN (1) VIN (2) fop fX Conditions VDD, XVDD, LVDD, RVDD, VVDD: During normal-speed playback VDD, XVDD, LVDD, RVDD, VVDD: During double-speed playback DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL EFMIN DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL EFMIN COIN, RWC: Figure 1 COIN, RWC: Figure 1 SBCK, CQCK: Figures 1, 2 and 3 SBCK, CQCK: Figures 1, 2 and 3 SQOUT, PW: Figures 2 and 3 RWC: Figure 1 WRQ: Figure 2, with no RWC signal SFSY: Figure 3 SFSY: Figure 3 CONT1 to CONT5, RWC: Figure 4 CONT1 to CONT5, RWC: Figure 4 RWC, CQCK: Figure 4 CONT1 to CONT8, RWC: Figure 5 EFMIN: Slice level control XIN: Capacitor-coupled input EFMIN XIN, XOUT 16.9344 1.0 1.0 10 400 400 400 100 1200 min 3.6 typ max 5.5 Unit V 3.6 0.7 VDD 0.6 VDD 0 0 400 400 400 400 0 1000 11.2 136 5.5 VDD VDD 0.3 VDD 0.4 VDD V V V V V ns ns ns ns Input high level voltage 400 ns ns ms s ns ns ns ns ns Vp-p Vp-p MHz MHz Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V Parameter Current drain Input high level current Symbol IDD IIH (1) IIH (2) Input low level current IIL VOH (1) Output high level voltage VOH (2) VOH (3) VOL (1) Output low level voltage VOL (2) VOL (3) IOFF (1) Output off leakage current IOFF (2) Charge pump output current IPDOH IPDOL Conditions VDD, XVDD, LVDD, RVDD, VVDD DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TEST1: VIN = VDD TAI, TEST2 to TEST5, CS, PCCL: VIN = VDD = 5.5 V DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TAI, TEST1 to TEST5, CS, PCCL: VIN = 0 V EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH/CONT6, EFLG, FSX: IOH = -1 mA MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to CONT5: IOH = -0.5 mA DOUT: IOH = -12 mA EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH/CONT6, EFLG, FSX: IOH = 1 mA MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to CONT5: IOH = 2 mA DOUT: IOH = 12 mA PDO, CLV+, CLV-, JP+, JP-, CONT1 to CONT5: VOUT = VDD PDO, CLV+, CLV-, JP+, JP-, CONT1 to CONT5: VOUT = 0 V PDO: RISET = 68 k PDO: RISET = 68 k -5 64 -96 80 -80 96 -64 25 -5 4 min typ 25 max 35 5 75 Unit mA A A A V 4 4.5 1 V V V 0.4 V 0.5 5 V A A A A No. 6015-4/31 LC78622NE One-Bit D/A Converter Analog Characteristics at Ta = 25C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V Parameter Total harmonic distortion Symbol THD + N Conditions LCHO, RCHO; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) LCHO, RCHO; 1 kHz: -60 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHO, RCHO; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHO, RCHO; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) 87 min typ 0.009 max 0.012 Unit % Dynamic range DR 90 dB Signal-to-noise ratio S/N 93 95 dB Crosstalk CT 82 84 dB Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal). Figure 1 Command Input No. 6015-5/31 LC78622NE Figure 2 Subcode Q Output Figure 3 Subcode Output Figure 4 General-Purpose Port Input Timing Figure 5 General-Purpose Port Output Timing No. 6015-6/31 LC78622NE Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol DEFI TAI PDO VVSS ISET VVDD FR VSS EFMO EFMIN TEST2 CLV+ CLV- V/P HFL TES TOFF TGL JP+ JP- PCK FSEQ VDD CONT1 CONT2 CONT3 CONT4 CONT5 EMPH/CONT6 C2F DOUT TEST3 TEST4 I/O I I O - AI - AI - O I I O O O I I O O O O O O - I/O I/O I/O I/O I/O O O O I I PLL pins Function Defect detection signal (DEF) input. (Must be connected to 0 V when unused.) Test input. A pull-down resistor is built in. Must be connected to 0 V. Internal VCO control phase comparator output Internal VCO ground. Must be connected to 0 V. PDO output current adjustment resistor connection Internal VCO power supply VCO frequency range adjustment Digital system ground. Must be connected to 0 V. Slice level control EFM signal output EFM signal input Test input. A pull-down resistor is built in. Must be connected to 0 V. Disc motor control output. Three-value output is also possible when specified by microprocessor command. Output pin states during a reset -- -- -- -- -- -- -- -- Undefined -- -- Low-level output Low-level output Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and Low-level output a low level during phase control. Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. Tracking off output Tracking gain switching output. Increase the gain when low. Track jump output. Three-value output is also possible when specified by microprocessor command. EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and the internally generated synchronization signal agree. Digital system power supply. General-purpose I/O pin 1 General-purpose I/O pin 2 General-purpose I/O pin 3 General-purpose I/O pin 4 General-purpose I/O pin 5 De-emphasis monitor pin. A high level indicates playback of a emphasis disk./general-purpose I/O port 6 C2 flag output Digital output. (EIAJ format) Test input. A pull-down resistor is built in. Must be connected to 0 V. Test input. A pull-down resistor is built in. Must be connected to 0 V. General-purpose I/O command identification pin. A pull-down resistor is built in. If only the same functions as those provided by the LC78622E are used, this pin must be left open or connected to 0 V. High: Only the general-purpose I/O port commands are allowed. Low: All commands are allowed. Left channel mute output/general-purpose I/O port 7 Left channel one-bit D/A converter Left channel power supply Left channel output Left channel ground. Must be connected to 0 V. Right channel ground. Must be connected to 0 V. Right channel one-bit D/A converter Right channel output Right channel power supply Right channel mute output/general-purpose I/O port 8 Crystal oscillator power supply. Connections for a 16.9344 MHz crystal oscillator element Crystal oscillator ground. Must be connected to 0 V. Subcode block synchronization signal output C1, C2, single and double error correction monitor pin Subcode P, Q, R, S, T, U, V and W output Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. Controlled by serial data commands from the microprocessor. Any of these that are unused must be either set up as input ports and connected to 0 V, output ports and set up as left open. -- -- High-level output Undefined Low-level output Low-level output Low-level output Undefined -- Input Input Input Input Input Low-level output Undefined Undefined -- -- 34 PCCL I -- 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MUTEL/CONT7 LVDD LCHO LVSS RVSS RCHO RVDD MUTER/CONT8 XVDD XOUT XIN XVSS SBSY EFLG PW SFSY O - O - - O - O - O I - O O O O High-level output -- -- -- -- -- -- High-level output -- -- -- -- Undefined Undefined Undefined Undefined Continued on next page. No. 6015-7/31 LC78622NE Continued from preceding page. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol SBCK FSX WRQ RWC SQOUT COIN CQCK RES TST11 16M 4.2M TEST5 CS TEST1 I/O I O O I O I I I O O O I I I Function Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.) Output for the 7.35 kHz synchronization signal divided from the crystal oscillator Subcode Q output standby output Read/write control input. This is a Schmitt input. Subcode Q output Command input from the control microprocessor Input for both the command input clock and the subcode readout clock. This is a Schmitt input. Chip reset input. This pin must be set low briefly after power is first applied. Test output. Leave open. (Normally outputs a low level.) 16.9344 MHz output. 4.2336 MHz output Test input. A pull-down resistor is built in. Must be connected to 0 V. Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled. Test input. No pull-down resistor. Must be connected to 0 V. Output pin states during a reset -- Undefined Undefined -- Undefined -- -- -- Low-level output Clock output Clock output -- -- -- Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDD, LVDD, RVDD, and XVDD. Pin Applications 1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV+ An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78622NE handles defects as follows. When a high level is input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 14) is low. This function can be used in combination with the LA9240M and LA9241M DEF pins. Note: If the EFMIN and CLV+ signal lines are too close to each other, unwanted radiation can result in error rate degradation. We recommend laying a ground or VDD shield line between these two lines. 2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78622NE includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 k, C1 = 0.1 F R2 = 680 , C2 = 0.1 F R3 = 1.2 k No. 6015-8/31 LC78622NE 3. VCO Monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided from the VCO frequency. 4. Synchronization Detection Monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.) 5. Servo Command Function; Pin 54: RWC, pin 56: COIN, pin 57: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCKclock. Note that commands are executed on the falling edge of RWC. Focus start Track jump Muting control Disk motor control Miscellaneous control Track check Digital attenuator General-purpose I/O, E/D * One-byte commands One-byte commands Two-byte command (RWC set twice) Two-byte commands (RWC set once) * Two-byte commands (RWC set twice: For track checking) No. 6015-9/31 LC78622NE * Two-byte commands (RWC set once: Sets up the digital attenuation and the general-purpose I/O ports) * Command noise rejection MSB LSB Command COMMAND INPUT NOISE REDUCTION MODE RESET NOISE EXCLUSION MODE RES = low 11101111 11101110 q This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings tWL, tWH, and tSU, must be set for at least 1 s. 6. CLV Servo Circuit; Pin 12: CLV+, pin 13: CLV-, pin 14: V/P MSB LSB Command DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) RES = low 00000100 00000101 00000110 00000111 q The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV- pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV- outputs in each of these modes. Mode Accelerate Decelerate CLV Stop CLV+ High Low Pulse output CLV- Low High Pulse output Low Low Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode. No. 6015-10/31 LC78622NE * CLV mode In CLV mode the LC78622NE detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control. Internal mode Rough servo (velocity too low) Rough servo (velocity too high) Phase control (PCK locked) CLV+ High Low PWM CLV- Low High PWM V/P High High Low * Rough servo gain switching MSB LSB Command DISC 8 SET DISC 12 SET RES = low 10101000 10101001 q For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm disks. * Phase control gain switching MSB LSB Command CLV PHASE COMPARATOR DIVISOR: 1/2 CLV PHASE COMPARATOR DIVISOR: 1/4 CLV PHASE COMPARATOR DIVISOR: 1/8 NO CLV PHASE COMPARATOR DIVISOR USED RES= low 10110001 10110010 10110011 10110000 q The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator. No. 6015-11/31 LC78622NE * CLV three-value output MSB LSB Command CLV THREE VALUE OUTPUT CLV TWO VALUE OUTPUT (the scheme used by previous products) RES = low 10110100 10110101 q The CLV three-value output command allows the CLV to be controlled by a single pin. * Internal brake modes MSB LSB Command INTERNAL BRAKE ON INTERNAL BRAKE OFF INTERNAL BRAKE CONTROL INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE TON MODE DURING INTERNAL BRAKING RESET TON MODE RES = low 11000101 11000100 10100011 11001011 11001010 11001101 11001100 q q q -- Issuing the internal brake-on (C5H) command sets the LC78622NE to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command (06H) is executed. -- In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV- pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode (CBH), the CLV- pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem may be rectified by changing the EFM signal count from four to eight with the internal brake control command (A3H). -- In TOFF output disabled mode (CDH), the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface. No. 6015-12/31 LC78622NE Note: 1. If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must be reissued. 2. Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disk defects, access in progress), we recommend using these functions in combination with a microprocessor. 7. Track Jump Circuit; Pin 15: HFL, pin 16: TES, pin 17: TOFF, pin 18: TGL, pin 19: JP+, pin 20: JP- * The LC78622NE supports the two track count modes listed below. MSB LSB Command NEW TRACK COUNT (using the TES/HFL combination) STANDARD TRACK COUNT (directly counts the TES signal) RES = low 00100010 00100011 q The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function. No. 6015-13/31 LC78622NE * TJ commands MSB LSB Command STANDARD TRACK JUMP NEW TRACK JUMP 1 TRACK JUMP IN #1 1 TRACK JUMP IN #2 1 TRACK JUMP IN #3 1 TRACK JUMP IN #4 2 TRACK JUMP IN 4 TRACK JUMP IN 16 TRACK JUMP IN 32 TRACK JUMP IN 64 TRACK JUMP IN 128 TRACK JUMP IN 1 TRACK JUMP OUT #1 1 TRACK JUMP OUT #2 1 TRACK JUMP OUT #3 1 TRACK JUMP OUT #4 2 TRACK JUMP OUT 4 TRACK JUMP OUT 16 TRACK JUMP OUT 32 TRACK JUMP OUT 64 TRACK JUMP OUT 128 TRACK JUMP OUT 256 TRACK CHECK TOFF TON TRACK JUMP BRAKE TOFF OUTPUT MODE DURING JP PULSE PERIOD RESET TOFF OUTPUT MODE DURING JP PULSE PERIOD RES = low 10100000 10100001 00010001 00010010 00110001 01010010 00010000 00010011 00010100 00110000 00010101 00010111 00011001 00011010 00111001 01011010 00011000 00011011 00011100 00111000 00011101 00011111 00010110 00001111 10001111 10001100 00100001 00100000 q q q When the LC78622NE receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78622NE detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TES signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In during TOFF output mode JP pulse period the TOFF signal is held high during the JP pulse generation period. Note: Of the modes related to disk motor control, the TOFF pin only goes low in CLV mode, and will be high during accelerate, stop, and decelerate modes.Note that the TOFF pin can be turned on and off independently by microprocessor issued commands. However, this function is only valid when disk motor control is in CLV mode. No. 6015-14/31 LC78622NE * Track jump modes The table lists the relationships between acceleration pulses (the a period) , deceleration pulses (the b period), and the braking period (the c period). Command 1 TRACK JUMP IN (OUT) #1 1 TRACK JUMP IN (OUT) #2 1 TRACK JUMP IN (OUT) #3 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period None 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period Standard track jump mode a 233 s 233 s 233 s b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. None 60 ms 60 ms 60 ms 60 ms 60 ms c 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period a 233 s The same time as "a" The same time as "a" The same time as "a" The same time as "a" The same time as "a" The same time as "a" 14 track jump period 28 track jump period 56 track jump period New track jump mode b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. 60 ms 60 ms 60 ms 60 ms 60 ms 60 ms c 1 TRACK JUMP IN (OUT) #4 233 s 2 TRACK JUMP IN (OUT) 4 TRACK JUMP IN (OUT) 16 TRACK JUMP IN (OUT) 32 TRACK JUMP IN (OUT) 64 TRACK JUMP IN (OUT) 128 TRACK JUMP IN (OUT) None 466 s 7 track jump period 14 track jump period 28 track jump period 56 track jump period 256 TRACK CHECK TRACK JUMP BRAKE TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a or b periods. 60 ms 60ms TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods. 60 ms 60 ms Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. If another track jump command is issued during a track jump operation, the content of that new command will be executed starting immediately. 4. The 1 TRACK JUMP #3 mode does not have a braking period (the C period). Since brake mode must be generated by an external circuit, care is required when using this mode. 5. While there was no braking period (the C period) in the LC78620E/21E for the new track jump command "2 TRACK JUMP IN (OUT)", this has been changed in this LSI, which has a C period of 60 ms. The THLD signal is generated by the LA9230M, LA9231M, or LA9240M, and the tracking signal is held during the JP pulse period. No. 6015-15/31 LC78622NE 5. Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region. * JP three-value output MSB LSB Command JP THREE VALUE OUTPUT JP TWO VALUE OUTPUT (earlier scheme) RES = low 10110110 10110111 q The JP three-value output command allows the track jump operation to be controlled from a single pin. * Track check mode MSB LSB Command TRACK CHECK IN TRACK CHECK OUT TWO BYTE COMMAND RESET RES = low 11110000 11111000 11111111 q The LC78622NE will count the specified number of tracks plus one when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command. Note: Data for the desired track count must not be set to the general-purpose command $D9 to $DF. No. 6015-16/31 LC78622NE Note: 1. When the desired track count has been input in binary, the track check operation is started by the fall of RWC. 2. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. 3. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control microprocessor should monitor this signal for a low level to determine when the track check completes. 4. If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 199 command once, and then count the WRQ signal 100 times. This will check 20,000 tracks. 5. After performing a track check operation, use the brake command to have the pickup lock onto the track. 8. Error Flag Output; Pin 48: EFLG, pin 52: FSX The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The FSX low-level period indicates the C1 correction state, and the high-level period indicates the C2 correction state. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 9. Subcode P, Q and R to W Output Circuit; Pin 49: PW, pin 47: SBSY, pin 50: SFSY, pin 51: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 s after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal. SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format) No. 6015-17/31 LC78622NE 10. Subcode Q Output Circuit; Pin 53: WRQ, pin 54: RWC, pin 55: SQOUT, pin 57: CQCK, pin 63: CS MSB LSB Command ADDRESS FREE ADDRESS 1 RES = low 00001001 10001001 q Subcode Q can be read from the SQOUT pin by applying a clock to the CQCKpin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Note that data is read out in an LSB first format. Note: * That state will be ignored if an address free command is input. This is provided to handle CD-ROM applications. Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) 2. The LC78622NE becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state. No. 6015-18/31 LC78622NE 11. Bilingual Function MSB LSB Command STO CONT Lch CONT Rch CONT RES = low 00101000 00101001 00101010 q * Following a reset or when a stereo (28H) command has been issued, the left and right channel data is output to the left and right channels respectively. * When an Lch set (29H) command is issued, the left and right channels both output the left channel data. * When an Rch set (2AH) command is issued, the left and right channels both output the right channel data. 12. De-Emphasis; Pin 29: EMPH/CONT6 The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78622NE internal de-emphasis circuit operates and the digital filters and the D/A converter output deemphasized data. 13. Digital Attenuator Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding two-byte command to the COIN pin in synchronization with the CQCK clock. MSB LSB Command ATT DATA SET ATT 4 STEP UP ATT 4 STEP DOWN ATT 8 STEP UP ATT 8 STEP DOWN ATT 16 STEP UP ATT 16 STEP DOWN RES = low DATA 00H set (MUTE - dB) 10000001 10000010 10000011 10000100 10000101 10000110 10000111 * Attenuation setup Since the attenuation level is set to the muted state (a muting of - is specified by an attenuation coefficient of 00H) after the attenuation level is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET command) to output audio signals. Note that the attenuation level can be set to one of 239 values from 00H to EEH. These two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set RWC once and a two-byte command reset is not required. After inputting the target attenuation level as a value in the range 00H to EEH, sending an attenuator step up/down command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in synchronization with rising edges on the LRSY input. However, the ATT DATA SET command sets the target value directly. If a new data value is input during the transition, the value begins to approach the new target value at that point. Note that the UP/DOWN distinction is significant here. No. 6015-19/31 LC78622NE ATT DATA [dB] 100H Audio output level = 20 log For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command. 238 level x 4STEP UP 21.6 ms 44.1 kHz Note: Setting the attenuation level to values of EFH or higher is disallowed to prevent overflows in one-bit D/A converter calculations from causing noise. 14. Mute Output; Pin 35: MUTEL/CONT7, pin 42: MUTER/CONT8 15. C2 Flag Output; Pin 30: C2F C2F output flag information in 8-bit units. 16. Digital Output Circuit; Pin 31: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer. MSB LSB Command DOUT ON DOUT OFF UBIT ON UBIT OFF CDROM-XA ROMXA-RST RES = low 01000010 01000011 01000000 01000001 10001000 10001011 q q q * The DOUT pin can be locked at the low level by issuing a DOUT OFF command. * The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. * The DOUT data can be switched to data for which interpolation and muting processing have not been performed by issuing a CD-ROM XA command. * When searching and when returning the pickup to its initial position, there are cases when the frequency output data will contain a parity error and locking is lost temporarily. To prevent this, we recommend directly executing a UBIT OFF ($41) command and then directly executing a UBIT ON ($40) command when searching and when returning the pickup to its initial position. 17. Mute Control Circuit MSB LSB Command MUTE: 0 dB MUTE: - dB RES = low 00000001 00000011 q Inputting the above command mutes the audio level (MUTE - dB). Since zero-cross muting is used, there is very little noise associated with this operation. The IC defines zero cross to be the ranges where the upper 7 bits of the data are all zeros or all ones. Note that the MUTE -12 dB instruction supported by the LC78620E has been removed from this product. No. 6015-20/31 LC78622NE 18. Interpolation Circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78622NE replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. If one set of C2 flags indicate errors, the above replacement is performed, and if two or more sets of C2 flags indicate errors, the IC holds the previous value. However, when correct data is output following two or more consecutive C2 flags indicating errors, the data point between the correct data and the data output two points previously (the held value) is replaced with a value computed by linearly interpolating those two values. 19. General-Purpose I/O Ports; Pin 24: CONT1, Pin 25: CONT2, Pin 26: CONT3, Pin 27: CONT4, Pin 28: CONT5, Pin 29: EMPH/CONT6, Pin 34: PCCL, Pin 35: MUTEL/CONT7, Pin 42: MUTER/CONT8 The LC78622NE provides five I/O ports CONT1 to CONT5 and three output ports CONT6 to CONT8. After a reset, these five I/O ports are set to function as input pins and the three output ports are set to function as EMPH, MUTEL, and MUTER pins, respectively. Unused I/O ports must be connected to ground set to function as input ports or set to function as output ports. Code $DD $DB $DC $D9 $DA $DE $DF PORT READ PORT I/O SET PORT OUTPUT SET Enable the CONT6 function Enable the EMPH function Enable the CONT7 and CONT8 functions Enable the MUTEL and MUTER functions q q PORT I SET Command RES = low The port information can be read out from the SQOUT pin in synchronization with the falling edge of the CQCK signal in the order CONT1 to CONT5 by using the PORT READ command. When the pin WRQ enters `H' level by the subcode Q output while controlling general-purpose port, the data for the subcode Q should be invalid and another subcode Q should be read out. This command has the 1-byte command format. Command control limited to only the general-purpose ports is possible by using the PCCL pin setting, even during track check, track jump, and internal MTR braking operations. When using the general-purpose port command control function during track check and similar operations, set the PCCL pin high and input the desired general-purpose I/O ports commands (codes $D9 through $DF). (Only the general-purpose I/O port commands are accepted when the PCCL pin is high.) The PCCL pin must be set low to input a command other than a general-purpose I/O port command. However, if a track check or other command is applied when the PCCL pin is at the low level, the operation that is being performed will be interrupted. The state of the PCCL pin must only be changed when the RWC pin is low. However, it must not be changed during subcode Q readout. Note: When track checking, if the same number of desired tracks as general-purpose I/O port commands (codes $D9 to $DF) is applied to with the PCCL held at `L' level, general-purpose port command as well as track count operation for desired track count will be executed. Therefore, the desired tarack count data should not be set to the codes $D9 to $DF with the PCCL held at `L' level when track checking. No. 6015-21/31 LC78622NE Additionally, CONT1 to CONT5 ports can be set up individually to function as control output pins with the PORT OP-E/D SET command. The ports are selected using the lower 5 bits of the 1Byte data. The bits in the data correspond to CONT1 to CONT5 in order starting with the LSB of the 1Byte data. This command is a Two- byte command. (RWC set once) MSB LSB Command PORT OP-E/D SET 1 1 0 1 1 0 1 1 X X X d5 d4 d3 d2 d1 dn =1 ... Sets CONTn to be an output pin dn =0 ... Sets CONTn to be an input pin X... don't care Ports set to be output pins can output high or low levels independently. The 8 bits of the 1 Byte data correspond to those ports. The bits in the data correspond to CONT1 to CONT8 in order starting with the LSB of the 1 Byte data. To use CONT6 through CONT8 as output ports, the port functions must be set with the $D9 and $DE commands. This command is a two-byte command. (RWC set once) MSB LSB Command PORT DATA SET 1 1 0 1 1 1 0 0 X X X d5 d4 d3 d2 d1 dn =1 ... Sets CONTn to be an output pin dn =0 ... Sets CONTn to be an input pin X... don't care 20. Clock Oscillator; Pin 45: XIN, pin 44: XOUT MSB LSB OSC ON OSC OFF XTAL 16M NORMAL-SPEED PLAYBACK DOUBLE-SPEED PLAYBACK Command RES = low 10001110 10001101 11001110 11000010 11000001 q q q The clock that is used as the time base is generated by connecting a 16.9344 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. The system control microprocessor can issue double-speed or normal-speed playback command when the application implements double-speed playback system. 21. 16M and 4.2M Pins; Pin 60: 16M, pin 61: 4.2M Both in normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz signal. The 4.2M pin supplies the LA9240M or LA9241M system clock, normally outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low. No. 6015-22/31 LC78622NE 22. Reset Circuit; Pin 58: RES When power is first applied, this pin should be briefly set low and then set high. This will set the muting to - dB and stop the disk motor. Constant linear velocity servo Muting control Q subcode address conditions Track jump mode Track count mode Digital attenuator OSC Playback speed Digital filter normal speed START 0 dB Address 1 Standard Standard DATA 0 ON Normal speed ON STOP BRAKE CLV - Address free New New DATA 00H to EEH OFF Double speed OFF Setting the RES pin low sets the LC78622NE to the settings enclosed in boxes in the table. 23. Other Pins; Pin 2:TAI, pin 64: TEST1, pin 11: TEST2, pin 32: TEST3, pin 33: TEST4, pin 62: TEST5, pin 59: TST11 These pins are used for testing the LSI's internal circuits. Even though pull-down resistors are built into the TAI and TEST2 to TEST5 input pin circuits, these pins must be connected to 0 V during normal operation. TST11 is an output pin and should normally be left open. Since TEST 1 is an input pin without a pull-down resistor built in, be sure to connect to 0V. No. 6015-23/31 LC78622NE 24. Circuit Block Operating Descriptions * RAM address control The LC78622NE incorporates an 8-bit x 2k-word RAM on chip. This RAM has an EFM demodulated data jitter handling capacity of 4 frames implemented using address control. The LC78622NE continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the 4 frame buffer capacity is exceeded, the LC78622NE forcibly sets the write address to the 0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period. Position -4 or less -3 -2 -1 0 +1 +2 +3 +4 or more Division ratio or processing Force to 0 589 589 589 588 587 587 587 Force to 0 Decrease ratio Standard ratio Increase ratio * C1 and C2 Error Correction The LC78622NE writes EFM demodulated data to internal RAM to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. First, the LC78622NE performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC78622NE performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM. C1 flag No errors 1 error 2 errors 3 errors or more C2 flag No errors 1 error 2 errors 3 errors or more Error correction and flag processing No correction required * Flag reset Correction * Flag reset Correction * Flag set Correction not possible * Flag set Error correction and flag processing No correction required * Flag reset Correction * Flag reset Depends on C1 flags*1 Depends on C1 flags*2 Note: 1. If the positions of the errors determined by the C2 check agree with those specified by the C1 flags, the correction is performed and the flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the C2 flags without change. 2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other No. 6015-24/31 LC78622NE 25. Command Summary Table Blank entry: Illegal command, #: Changed or added command, *: Latching commands (mode setting commands), q: Commands shared with an ASP (LA9220M/30M/40M or other processor), Items in parentheses are ASP commands (provided for reference purposes) 00000000 (ADJ.reset) 0 dB 0 0 1 0 0 0 0 0 * TOFF low in TJ mode 0 0 1 0 0 0 0 1 * TOFF high in TJ mode 0 0 1 0 0 0 1 0 * New TRACK COUNT - dB 0 0 1 0 0 0 1 1 * Old TRACK COUNT 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 * UBIT ON * UBIT OFF * DOUT ON * DOUT OFF 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 # 01101100 # 01101101 0 1 1 0 1 1 1 0 *DF normal speed off 01101111 # 0 0 0 0 0 0 0 1 * MUTE 00000010 # 0 0 0 0 0 0 1 1 * MUTE 0 0 0 0 0 1 0 0 * DISC MTR START 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 * DISC MTR CLV 0 0 0 0 0 1 1 1 * DISC MTR STOP 0 0 0 0 1 0 0 0 q FOCUS START #1 0 0 0 0 1 0 0 1 * ADDRESS FREE 00001010 # 00001011 00001100 00001101 00001110 # 0 0 0 0 1 1 1 1 * TRACKING OFF 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 128TJ OUT 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ 256TC 128TJ IN 2TJ 1TJ 1TJ 4TJ 16TJ 64TJ OUT OUT #1 OUT #2 OUT OUT OUT IN IN #1 IN #2 IN IN IN 00100101 0 0 0 0 0 1 1 0 * DISC MTR BRAKE 0 0 1 0 0 1 1 0 00100111 0 0 1 0 1 0 0 0 * STO CONT 0 0 1 0 1 0 0 1 * LCH CONT 0 0 1 0 1 0 1 0 * RCH CONT 00101011 # 00101100 # 00101101 # 00101110 # 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 32TJ 1TJ IN IN #3 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 1TJ IN #4 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 1TJ OUT #4 01111010 01111011 01111100 01111101 01111110 01111111 32TJ 1TJ OUT OUT #3 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 Continued on next page. No. 6015-25/31 LC78622NE Continued from preceding page. Blank entry: Illegal command, #: Changed or added command, *: Latching commands (mode setting commands), q : Commands shared with an ASP (LA9240M/41M or other processor), Items in parentheses are ASP commands (provided for reference purposes) 10000000 1 0 0 0 0 0 0 1 * ATT DATA SET 1 0 0 0 0 0 1 0 * ATT 4STP UP 1 0 0 0 0 0 1 1 * ATT 4STP DWN 1 0 0 0 0 1 0 0 * ATT 8STP UP 1 0 0 0 0 1 0 1 * ATT 8STP DWN 1 0 0 0 0 1 1 0 * ATT 16STP UP 1 0 0 0 0 1 1 1 * ATT 16STP DWN 1 0 0 0 1 0 0 0 * #CDROMXA 1 0 0 0 1 0 0 1 * ADDRESS 1 10001010 # 1 0 0 0 1 0 1 1 * #ROMXA RST 10001100 TRACK JMP BRK 1 0 1 0 0 0 0 0 * Old TRK JMP 1 0 1 0 0 0 0 1 * New TRK JMP 10100010 11000000 11000001 * Double-speed playback * Normal-speed playback 11100000 11100001 11100010 11100011 * Internal BRK OFF * Internal BRK ON 11100100 11100101 11100110 11100111 # *# 11101000 11101001 FOCUS START #2 1 1 0 0 0 0 1 0 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 1 0 1 0 0 0 1 1 * Internal BRAKE CONT 10100100 10100101 10100110 10100111 1 0 1 0 1 0 0 0 * DISC 8 SET 1 0 1 0 1 0 0 1 * DISC 12 SET 10101010 10101011 10101100 10101101 10101110 10101111 * Internal BRK-DMC 1 1 1 0 1 0 1 0 low * Internal BRK-DMC 1 1 1 0 1 0 1 1 high * TOFF during internal BRAKE * TON during internal BRAKE * Xtal 16M 11101100 11101101 1 1 1 0 1 1 1 0 * Command noise rejecter OFF 1 1 1 0 1 1 1 1 * Command noise rejecter ON 1 1 1 1 0 0 0 0 * q TRCK CHECK IN (2BYTE DETECT) 11110001 11110010 11110011 11110100 11110101 11110110 11110111 1 1 1 1 1 0 0 0 * q TRCK CHECK OUT (2BYTE DETECT) #CONT6 #EMPH #PORT I/O SET 11111001 11111010 11111011 1 0 0 0 1 1 0 1 * OSC OFF 1 0 0 0 1 1 1 0 * OSC ON 1 0 0 0 1 1 1 1 * TRACKING ON 1 0 0 1 0 0 0 0 (* F.OFF.ADJ.ST) 1 0 1 1 0 0 0 0 * CLV-PH 1/1 mode 11010000 1 0 0 1 0 0 0 1 (* F.OFF.ADJ.OFF) 1 0 0 1 0 0 1 0 (* T.OFF.ADJ.ST) 1 0 0 1 0 0 1 1 (* T.OFF.ADJ.OFF) 1 0 0 1 0 1 0 0 (* LSR.ON) 1 0 1 1 0 0 0 1 * CLV-PH 1/2 mode 1 0 1 1 0 0 1 0 * CLV-PH 1/4 mode 1 0 1 1 0 0 1 1 * CLV-PH 1/8 mode 11010001 11010010 11010011 1 0 1 1 0 1 0 0 * CLV3ST output ON 1 1 0 1 0 1 0 0 11010101 11010110 1 0 0 1 0 1 0 1 (* LSR.OF/F.SV.ON) 1 0 1 1 0 1 0 1 * CLV3ST output OFF 1 0 0 1 0 1 1 0 (* LSR.OF/F.SV.OF) 1 0 1 1 0 1 1 0 * JP3ST output ON 1 0 0 1 0 1 1 1 (* SP.8CM) 1 0 0 1 1 0 0 0 (* SP.12CM) 10111000 1 0 1 1 0 1 1 1 * JP3ST output OFF 1 1 0 1 0 1 1 1 11011000 1 0 0 1 1 0 0 1 (* SP.OFF) 1 0 0 1 1 0 1 0 (* SLED.ON) 1 0 0 1 1 0 1 1 (* SLED.OFF) 1 0 0 1 1 1 0 0 (* EF.BAL.START) 1 0 0 1 1 1 0 1 (* T.SERVO.OFF) 1 0 0 1 1 1 1 0 (* T.SERVO.ON) 10011111 10111001 10111010 10111011 10111100 10111101 10111110 10111111 11011001 11011010 11011011 11011100 11011101 11011110 11011111 #PORT OUTPUT SET 1 1 1 1 1 1 0 0 #PORT READ #CONT7, 8 #MUTEL, R 11111101 1 1 1 1 1 1 1 0 q NOTHING 1 1 1 1 1 1 1 1 * q 2BYTE CMD RST Note: VCO x 2 SET command should be issued in case of low voltage power supply application. No. 6015-26/31 LC78622NE 26. Sample Application Circuit No. 6015-27/31 LC78622NE 27. CD-DSP Functional Comparison Product Function EFM-PLL RAM Playback speed Digital output Interpolation Zero-cross muting Level meter peak search Bilingual Digital attenuator Digital filters Digital de-emphasis Generalpurpose port I/O VCD support Anti-shock interface Anti-shock control CD text CD-ROM interface 1-bit DAC L.P.F Supply voltage Package Output LC786021E Built-in VCO FR = 1.2 K 16K 2! q 4 q -12 dB, - q q q 8fs q 2 ! ! q ! ! q q ! 3.6 to 5.5 V QFP80E LC78625E Built-in VCO FR = 1.2 K 16K 2! q 4 q -12 dB, - q q q 8fs q 2 (4) q q ! ! q q ! 3.0 to 5.5 V QFP80E LC78630E Built-in VCO FR = 1.2 K 18K 4! q 2 q - ! q q 2fs q 2 2 + (4) q q ! ! q q ! 3.6 to 5.5 V QFP80E LC78624E Built-in VCO FR = 1.2 K 16K 2! q 2 q - ! q ! ! ! ! 5 ! ! ! q ! ! ! 3.0 to 5.5 V QFP64E LC78626E (LC78626KE) Built-in VCO FR = 5.1 K 16K 2! q 2 q - ! q q 4fs (8fs) q ! 1 + (3) ! Not required q max 4MDRAM (max 16MDRAM) ! ! q q 3.0 to 5.5 V (3.0 to 3.6 V) QFP100E 16K 2! q 2 q - ! q q 4fs q ! 5 ! ! ! ! ! q q 3.0 to 5.5 V QFP64E LC78622E LC78622NE Built-in VCO FR = 1.2 K 16K 2! q 2 q - ! q q 8fs q (3) 5 ! ! ! ! ! q q 3.6 to 5.5 V QFP64E Notes on Application Design While it goes without saying that to achieve system reliability the absolute maximum ratings and allowable operating conditions specified for this IC must be strictly adhered to, adequate consideration must also be given to the operating environmental conditions, such as ambient temperature and static electricity, and to the mounting conditions used. This section presents items that require special care during application design and IC mounting. Handling of Unused Pins * If unused input pins on this IC are left in the open state during IC operation, there are times when the IC may enter an unstable state. Always follow all the directions for handling unused pins included in the documentation for this IC. Also, do not connect any output pins to power supply, ground, or any other output lines. * All general-purpose I/O ports must either be set to the output state and set to output a low level in software, or must be left in the input state and pulled up or pulled down to a fixed input level. Latch-up Prevention * Due to the structure of this IC, all supply voltage pins must be supplied with the same potential. -- Also supply the same potential to the servo system ASP. The slice level control circuit is shared with this IC, and application of the same potential is necessary. Also, the same potential must be supplied to all supply voltage pins on the ASP IC. * Latch-up may occur if any discrepancy occurs in the timing of the rise of the supply voltage applied to the different supply voltage pins. Do not allow timing discrepancies to occur when power is first applied. * Do not allow the pin voltages on any of the input or output pins to exceed VDD or to fall lower than VSS. The timing of signal application requires special care at power on to assure that this condition is met. * Do not allow overvoltages or abnormal noise to be applied to this IC. continued on next page. No. 6015-28/31 LC78622NE Continued from preceding page. * In general, latch-up can be prevented by tying any unused pins to either VDD or VSS. However, be sure to follow any special instructions provided with this IC for unused pin handling. * Do not short the outputs. Interface When the inputs and outputs of devices of different types are connected, incorrect operation may occur due to discrepancies between the input VIL/VIH and output VOL/VOH values. Insert level shifters between devices that have different supply voltages to prevent device destruction in systems that use dual power-supply systems. Load Capacitance and Output Current * When a load with a large capacitance is connected, since a load short that lasts for an extended period, fused output lines can be caused. Also, high charge and discharge currents can result in noise which can degrade end product performance or result in incorrect operation. Always use the recommended load capacitances. * Large output sink or source currents can also cause the same types of problems described in the previous item. Use the recommended currents, while taking the maximum allowable power dissipation into account. Notes on Power Application and Reset * There are points that require care that are related to power application, the period during which a reset is applied, and the period after a reset is cleared. Refer to the specific notes provided in the specification sheets for the individual products, and design end products with these points in mind. * The pin output states, the pin I/O settings, the contents of registers, and other aspects of this IC are not guaranteed when power is first applied. Aspects that are defined by the reset operation or by settings are only guaranteed once the reset or setting has been performed. Applications that use this IC should apply a reset immediately after power is applied. Pin states and register values that are undefined may differ between samples, and may change between lots over time. Applications should not depend on undefined states and values. * The general-purpose I/O ports are set to the input state during a reset. For pins that must be fixed at high or low due to fail-safe design considerations, pulling up to VDD or pulling down to VSS through an individual resistor can be an effective design. * When the 4.2MHz output is used as the microcontroller master clock, the reset circuit will be shared with the microcontroller. Since the microcontroller will not be reset unless a clock signal is applied, do not control the reset input to this IC from a microcontroller output port. If this IC has not been reset, the 4.2-MHz output is not guaranteed, and the microcontroller may not be reset. This can result in incorrect application system operation. Notes on Thermal Design The failure rate of semiconductor devices is significantly accelerated by increases in ambient temperature and power dissipation. To assure high reliability, designs must include adequate margins to take possible changes in ambient conditions into account. Notes on Printed Circuit Board Patterns * If possible, the influence of common impedances should be reduced by separating the VDD and ground lines for each system. * The VDD and ground lines should be as wide and as short as possible to lower their high-frequency impedance. Ideally, decoupling capacitors (0.01 to 1 F) should be inserted between each VDD and ground pair. These capacitors should be located extremely close to their corresponding power supply system pins. Additionally, it is appropriate to insert a capacitor of about 100 to 220 F between VDD and ground as a low-frequency filter. However, note that using excessively large capacitors here can result in latch-up. -- In servo systems, the VREF lines should be handled in the same manner as the VCC and ground lines. Driver ground lines should be particularly wide, and the recommended driver pattern should be used direct under the power devices taking heat radiation effect into consideration. -- If a current output type pickup is used, locate the optical sensor connector and the ASP RF input as close together as possible. If a voltage output type pickup is used, locate the I/V conversion resistor as close to the ASP RF input side as possible. Continued on next page. No. 6015-29/31 LC78622NE Continued from preceding page. * EFM signal lines should be kept as short as possible, and either adjacent lines should be avoided or VDD or ground shield lines should be run between adjacent EFM signal lines. Since the slice level controller output (EFMO) and the ASP clock output (4.2MHz) lines can easily disrupt EFM signal lines, resistors connected to output pins should be located extremely close to the pin. Note that the smaller these resistors, the larger the amount of spurious radiation emitted. Inversely, the output level may be adversely influenced if the resistors are made too large. Design the 4.2MHz output according to the ASP input level requirements. (Design center: 1 V p-p) * Noise on the microcontroller interface signal lines can result in incorrect operation. While the best method for reducing noise depends on the application itself, in general, the interface lines should be made as short as possible and inductances and capacitances minimized. However, designs must also take crosstalk into account. If long interface lines must be used, or if noise is a problem, inserting a noise exclusion circuit may be effective. Design noise filters with the interface timing taken into account. Issuing the command noise reduction command [$EF] may also be effective. * Cover the area around the crystal oscillator element with the ground pattern. Notes on Software Design * Always follow the recommendations for software design provided in the IC documentation and do not use any techniques specifically forbidden. * If the digital outputs are used, issue a UBIT OFF [$41] command to this IC during initialization. UBIT ON [$40] should only be used during playback to prevent DIR unlock and incorrect subcode recognition. * During initialization, after clearing an IC reset, and after turning this IC's oscillator on, issue a 2-byte reset command [$FF] to the LA9230M Series or LA9240M Series ASP to set up the ASP command register. * Since the LA9230M Series and LA9240M Series ASP ICs use the 4.2MHz output from this IC as their master clock, an additional 30 ms of setup time is required after the oscillator stabilization time during initialization, after clearing an IC reset, and after turning this IC's oscillator on. This 30 ms of setup time is also required after issuing an ASP reset command [$00] to the ASP. * Since the command timing for the LA9230M Series and LA9240M Series ASP ICs is slower than that for this IC, be sure to refer to the ASP IC documentation when designing application software. Other Notes If you have any questions, please do not hesitate to contact your Sanyo representative, or your Sanyo semiconductor sales outlet. Since this IC is specifically designed for use in CD players, its specifications differ from those of standard logic and other general-purpose IC products. We recommend adopting failsafe design techniques in the applications, and we also recommend debugging applications in the application equipment itself. No. 6015-30/31 LC78622NE Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1999. Specifications and information herein are subject to change without notice. PS No. 6015-31/31 |
Price & Availability of LC78622NE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |