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KM684002, KM684002E, KM684002I
Document Title
PRELIMINARY CMOS SRAM
512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial, Extended and Industrial Temperature Range.
Revision History
Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to final Data Sheet. 1.1. Delete Preliminary 2.1. Delete 15ns part 2.2. Add 17ns part. 2.3.Add the test condition for Voh1 with Vcc=5V5% at 25C 3.1.Delete Low power product with Data Retention Mode. 3.1.1. Delete Data Retention Characteristics 3.2.Add Industrial and Extended Temperature Range parts with the same parameters as Commercial Temperature Range parts. 3.2.1 Add KM684002I for Industrial Temperature Range. 3.2.2.Add KM684002E for Extended Temperature Range. 3.2.3.Add ordering information. 3.2.4. Add the condition for operating at Industrial and Extended Temperature Range. 3.3.Add timing diagram to define tWP as (Timing Wave Form of Write Cycle(CS=Controlled) Draft Data Jun. 1th, 1991 Oct. 4th, 1993 Remark Preliminary Final
Rev. 2.0
Apr. 2th, 1994
Final
Rev. 3.0
Jun. 17th, 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
U U
PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The KM684002 is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The KM684002 uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM684002 is packaged in a 400 mil 36-pin plastic SOJ.
U
U
U
U
U
U
U
Fast Access Time 17,20,25A(Max.) Low Power Dissipation Standby (TTL) : 60I(Max.) (CMOS) : 10I(Max.) Operating KM684002 - 17 : 180I(Max.) KM684002 - 20 : 170I(Max.) KM684002 - 25 : 160I(Max.) Single 5.0V10% Power Supply TTL Compatible Inputs and Outputs I/O Compatible with 3.3V Device Fully Static Operation - No Clock or Refresh required Three State Outputs Center Power/Ground Pin Configuration Standard Pin Configuration KM684002J : 36-SOJ-400
PIN CONFIGURATION(Top View)
A0 A1 1 2 3 4 5 6 7 8 9 10 36 N.C 35 A18 34 A17 33 A16 32 A15 31 OE 30 I/O8
ORDERING INFORMATION
KM684002 -17/20/25 KM684002E -17/20/25 KM684002I -17/20/25 Commercial Temp. Extended Temp. Industrial Temp.
A2 A3 A4 CS I/O1 I/O2 Vcc
SOJ
29 I/O7 28 Vss 27 Vcc 26 I/O6 25 I/O5 24 A14 23 A13 22 A12 21 A11 20 A10 19 N.C
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. A0 A1 A2 A3 A4 A7 A8 A9 A13 A14 I/O1 ~ I/O8 Pre-Charge Circuit
Vss
I/O3 11 I/O4 12 WE A5 A6 13 14 15 16 17 18
Row Select
A7
Memory Array 1024 Rows 512x8 Columns
A8 A9
PIN FUNCTION
Data Cont. I/O Circuit Column Select Pin Name A0 - A18 CLK Gen. A6 A5 A10 A11 A15 A17 A12 A16 A18 WE CS OE I/O1 ~ I/O8 VCC CS WE OE VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection
-2-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Commercial Operating Temperature Extended Industrial Symbol VIN, VOUT VCC PD TSTG TA TA TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85
PRELIMINARY CMOS SRAM
Unit V V
W
C C C C
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C)
Parameter Supply Voltage Ground Input Low Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC+0.5** 0.8 Unit V V V V
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges. * VIL(Min) = -2.0V a.c(Pulse Width 10ns) for I20I ** VIH(Max) = VCC + 2.0V a.c (Pulse Width 10ns) for I20I
DC AND OPERATING CHARACTERISTICS(TA=0 to 70C, Vcc= 5.0V10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 17ns 20ns 25ns ISB Standby Current Output Low Voltage Level Output High Voltage Level ISB1 VOL VOH VOH1* Min -2 -2 2.4 Max 2 2 180 170 160 60 10 0.4 3.95 Unit A A
Operating Current
ICC
I I I
V V V
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges. * VCC=5.0V5% Temp. = 25C
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 6 Unit pF pF
* NOTE : Capacitance is sampled and not 100% tested .
-3-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
NOTE: Above test conditions are also applied at industrial temperature ranges.
PRELIMINARY CMOS SRAM
Value 0V to 3V 3A 1.5V See below
Output Loads(A) +5.0V 480 DOUT 255 30pF*
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 DOUT 255 5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD KM684002-17 Min 17 3 0 0 0 3 0 Max 17 17 8 7 7 17 KM684002-20 Min 20 3 0 0 0 4 0 Max 20 20 10 8 8 20 KM684002-25 Min 25 3 0 0 0 5 0 Max 25 25 12 10 10 25 Unit
A A A A A A A A A A A
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
-4-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
WRITE CYCLE
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW KM684002-17 Min 17 12 0 12 12 17 0 0 8 0 3 Max 8 KM684002-20 Min 20 13 0 13 13 20 0 0 9 0 4 Max 8 -
PRELIMINARY CMOS SRAM
KM684002-25 Min 25 15 0 15 15 25 0 0 10 0 5 Max 10 Unit
A A A A A A A A A A A
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC ADD tAA tOH Data Out Previous Data Valid Data Valid
-5-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
TIMING WAVE FORM OF READ CYCLE(2) (WE=VIH)
tRC ADD tAA tCO CS tOE OE tOLZ tLZ(4,5) Data Out tPU Vcc Current Icc ISB 50% Data Valid
PRELIMINARY CMOS SRAM
tHZ(3,4,5)
tOHZ
tOH
tPD 50%
NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device. 5. Transition is measured 200AE from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
TIMING WAVE FORM OF WRITE CYCLE(1) (OE=Clock)
tWC ADD tAW OE tCW(3) CS tAS(4) WE tDW Data In High-Z tOHZ(6) High-Z(8) Data Out Data Valid tDH tWP(2) tWR(5)
-6-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
TIMING WAVE FORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC ADD tAW tCW(3) CS tAS(4) WE tDW Data In High-Z tWHZ(6) Data Out High-Z(8) Data Valid tDH tWP1(2)
PRELIMINARY CMOS SRAM
tWR(5)
tOH
tOW
(10)
(9)
TIMING WAVE FORM OF WRITE CYCLE(3) (CS=Controlled)
tWC ADD tAW tCW(3) CS tAS(4) WE tDW Data In High-Z tLZ Data Out High-Z tWHZ(6) Data Valid tDH High-Z tWP(2) tWR(5)
High-Z(8)
-7-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
NOTES(WRITE CYCLE)
PRELIMINARY CMOS SRAM
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC
* NOTE : X means Don't Care.
-8-
Rev 3.0 June -1997
KM684002, KM684002E, KM684002I
PACKAGE DIMENSIONS
36-SOJ-400
#36 #19
PRELIMINARY CMOS SRAM
Units : Inches (millimeters)
11.180.12 0.4400.005
10.16 0.400
9.400.25 0.3700.010
0.20
+0.10 -0.05
0.008 +0.004 -0.002 #1 #18 0.69 MIN 0.027 23.90 MAX 0.941 23.500.12 0.9250.005 ( 1.19 ) 0.047
3.76 MAX 0.148 0.10 MAX 0.004 0.43 +0.10 -0.05 0.017 +0.004 -0.002 0.71 +0.10 -0.05 0.028 +0.004 -0.002 ( 1.27 ) 0.050
( 0.95 ) 0.0375
1.27 0.050
-9-
Rev 3.0 June -1997

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