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HIP5062
August 1998 File Number 3208.2
Power Control IC Single Chip Dual Switching Power Supply
The HIP5062 is a complete power control IC, incorporating two high power DMOS transistors, CMOS logic and two low level analog control circuits on the same Intelligent Power IC. Both the standard "Boost" and the "SEPIC" (SingleEnded Primary Inductance Converter) power supply topologies are easily implemented with this single control IC. Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage. As a result of the power DMOS transistor's current and voltage capability (5A and 60V), multiple output power supplies with total output power capability up to 100W are possible.
Features
* * * * * * * * * * Two Current Mode Control Regulators Two 60V, 5A On-chip DMOS Transistors Thermal Protection Over-Voltage Protection Over-Current Protection 1MHz Operation or External Clock Synchronization Output On-Chip Reference Voltage - 5.1V Output Rise and Fall Times ~ 3ns Designed for 26V to 42V Operation
Applications
* * * * Single Chip Power Supplies Current Mode PWM Applications Distributed Power Supplies Multiple Output Converters
Ordering Information
PART NUMBER HIP5062DY HIP5062DW TEMPERATURE RANGE 0oC to +85oC 0oC to +85oC PACKAGE 40 Pad Chip Wafer
Chip
(2) D2 (3) D2 (5) D2 (6) D2 (1) S2 (4) S2 (7) S2 (8) VDDP2 (9) VCMP2 (10) PSOK (11) VREG2 (12) FLTN (13) PSEN (14) SHRT (15) SLRN (16) SFST (17) VDDD (18) VDDA (19) VREG1 (20) VDDP1 S1 (21)
V+ (40) TMON (39) IRFI2 (38) IRFO2 (37) VINP (36) AGND (35) DGND (34) XCKS (33) CKIN (32) IRFI1 (31) IRFO1 (30) VCMP1 (29) VTCN (28)
S1 (27)
D1 (26)
D1 (25)
S1 (24)
D1 (23)
175 mils x 175 mils (4.44mm x 4.44mm)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
D1 (22)
HIP5062 Simplified Block Diagram
VIN 4H 5H 0.66F 11H 0.1F 0.1F VDDD 4.7 H 4.0 H 1.0F 4H
12V
15 F
0.88 F
0.1 F
D2
VDDP2
V+ INTERNAL POWER SUPPLY AND REF VOLTAGE
VDDP1
D1 VDDP1 S1
0.1 F
1.0 F
33 F
5.1V
GATE DRIVERS S2 511 681 DGND VREG2 IRFO2 IRFI2 VCMP2 CONTROL Q AND LOGIC
GATE DRIVERS
CLOCK
Q CONTROL AND LOGIC
VREG1 IRFO1 IRFI1 VCMP1 VTCN VINP
TMON
AGND
PSOK
XCKS
PSEN
SLRN
TYPICAL SEPIC CONFIGURATION
2
SHRT
VDDD
VDDA
FLTN
SFST
CKIN
HIP5062
Absolute Maximum Ratings
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 42V DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC
Thermal Information
Thermal Resistance JC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050" Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = 0oC to +110oC; Unless Otherwise Specified
SYMBOL DEVICE PARAMETERS I+ VDDA Supply Current Internal Regulator Output Voltage V+ = 42V, PSEN = 12V V+ = 30V to 42V, IOUT = 0mA V+ = 30V to 42V, IOUT = 30mA SLRN = 12V, IOUT = 0mA VINP RVINP Reference Voltage VINP Resistance VDDA = SLRN = 12V, IVINP = 0mA VINP = 0 11.7 11.5 11.5 5.01 24.7 5.1 900 30 13.3 13.3 13.3 5.19 mA V V V V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIERS | VIO | RIN VREG gm (VREG) gm (SFST) IVCMP Input Offset Voltage (REG - VINP) Input Resistance to GND VREG Transconductance (IVCMP/(VREG - VINP) SFST Transconductance IVCMP/(VREG - SFST) Maximum Source Current Maximum Sink Current OVTH CLOCK fq V TH CKIN Internal Clock Frequency External Clock Input Threshold Voltages XCKS = 12V, V DDD = 12V 0.9 33 1.0 1.1 66 MHz %VDDD Over-Voltage Threshold IVCMP = 0mA VREG = 5.1V VCMP = 1V to 8V, SFST = 11V VSFST < 4.9V VREG = 4.95V, VCMP = 8V VREG = 5.25V, VCMP = 0.4V Voltage at VREG for FLTN to be latched 39 15 0.8 -2.5 0.75 6.05 30 10 85 50 6 -0.75 2.5 6.5 mV k mS mS mA mA V
DMOS TRANSISTORS rDS(on) IDSS Drain-Source On-State Resistance Drain-Source Leakage Current I Drain = 2.5A, VDDD = 11V, TJ = +25oC Drain to Source Voltage = 60V 1 0.22 100 A
CURRENT CONTROLED PWM |VIO| VCMP Buffer Offset Voltage (VCOMP VIFRO) IFRO = 0mA to -5mA, VTCN = 0.2V to 7.6V, VCMP2 = 0.2V to 7.6V 125 mV
3
HIP5062
Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = 0oC to +110oC; Unless Otherwise Specified (Continued)
SYMBOL VTH IFRO PARAMETER Voltage at IRFO that disables PWM. This is due to low load current Voltage at IRFO to enable SHRT output current. This is due to Regulator Over Current Conditions SHRT Output Current, During Over-Current Threshold voltage on SHRT to set FLTN latch IPEAK (DMOSDRAIN)/IIRFI IRFI Resistance to GND Current Comparator Response Time (Note 1) Minimum Controllable Pulse Width (Note 1) Minimum Controllable DMOS Peak Current (Note 1) VIRFO = 7.7V VDDD = 11V I (DMOSDRAIN)/t = 1A/ms IIRFI = 2mA I (DMOSDRAIN)/t > 1A/s TEST CONDITIONS MIN 116 TYP MAX 250 UNITS mV
ITH IFRO
6.85
-
7.65
V
ISHRT VTH SHRT IGAIN RIRFI tRS MCPW MCPI START-UP V+
-75 2.0 150 25 125
5 30 50 250
-33 3.2 360 100 500
A V A/mA ns ns mA
Rising V+ Power-On Reset Voltage Falling V+ Power-Off Set Voltage V+ Power-On Hysteresis
23 9.5 VDDD = 11V 3.6 VSFST = 0V to 11V SFST = 11V, PSOK = 12V SFST = 0V, IPSOK = 1mA VDDD = 11V -1.5 -1 8.1
15 12 -1.0 -
26.3 11.8 6.5 -0.65 1 0.4 9.9
V V V V K A A V V
VTH PSEN rPSEN ISFST IPSOK VPSOK VTH SFST
Voltage at PSEN to Enable Supply Internal Pull-Up Resistance, to VDDD Soft-Start Charging Current PSOK High-State Leakage Current PSOK Low-State Voltage PSOK Threshold, Rising V SFST
THERMAL MONITOR TEMP NOTE: 1. Determined by design, not a measured parameter. Substrate Temperature for Thermal Monitor to Trip (Note 1) TMON = 0V 105 135
oC
4
HIP5062 Pin Descriptions
PAD NUMBER 1, 4, 7 2, 3, 5, 6 8 DESIGNATION S2 D2 VDDP2 DESCRIPTION Source pads for the channel 2 regulator. Drain pads for the channel 2 regulator. This pad is the power input for the channel 2 DMOS gate driver and also is used to decouple the high current pulses to the output driver transistors. The decoupling capacitor should be at least a 0.1F chip capacitor placed close to this pad and the DMOS source pads. Output of the second channel transconductance amplifier. This node is used for both gain and frequency compensation of the loop. This pad provides delayed positive indication when both supplies are enabled. Input to the transconductance error amplifier. The other common input for both amplifiers is VINP, Pad 36. This is an open drain output that remains low when V+ is too low for proper operation. This node and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current is experienced. V+ must be powered down to reset. This terminal is provided to activate the converter. When the input is low, the DMOS drivers are disabled. There is an internal 12K pull-up resistor on this terminal. 50A is internally applied to this node when there is an over-current condition. Control input to internal regulator that is used during the "start-up" of the supply. In normal operation this terminal starts at 0V and shuts down the internal regulator at approximately 9V. This pad is usually connected to SFST, pad 16. Controls the rate of rise of both output voltages. Time is determined by an internal 1A current source and an external capacitor. Voltage input for the chip's digital circuits. This pad also allows decoupling of this supply. This is the analog supply and internal 12V regulator output usually used only during the start-up sequence. The internal regulator reduced to a nominal 9.2V when SLRN is returned to 12V. Output current capability is 30mA at both voltages. Input to channel one transconductance error amplifier. The other, common input for both amplifiers is VINP, pad 36. This pad is the power input for the channel 1 DMOS gate driver and also is used to decouple the high current pulses to the output driver transistors. The decoupling capacitor should be at least a 0.1F chip capacitor placed close to this pad and the DMOS source pads. Drain pads for the channel 1 regulator. Source pads for the channel 1 regulator. Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP1, pad 29. Output of the first channel transconductance amplifier. This node is used for both gain and frequency compensation of the loop. A resistor placed between this pad and IRFI1 converts the VCMP1 signal to a current for the current sense comparator. The maximum current is set by the value of the resistor, according to the equation: IPEAK = 16/R. Where R is the value of the external resistor in K and must be greater than 1.5K but less than 10K. For example, if the resistor chosen is 1.8K, the peak current will be 8.8A. This assumes VCMP1 is 7.3V. Maximum output current should be kept below 10A. See IRFO1.
9
VCMP2
10 11
PSOK VREG2
12
FLTN
13
PSEN
14 15
SHRT SLRN
16
SFST
17 18
V DDD VDDA
19
VREG1
20
VDDP1
22, 23, 25, 26 21, 24, 27 28
D1 S1 VTCN
29
VCMP1
30
IRFO1
31
IRFI1
5
HIP5062 Pin Descriptions
PAD NUMBER 32 33 (Continued) DESCRIPTION Clock input when XCKS is grounded. Grounding this terminal provides for the application of an external clock to CKIN input terminal. For normal internal clock operation, this terminal may be left floating or returned to 12V. There is an internal 30K pull-up resistor on this terminal. Ground of the DMOS gate drivers. This pad is used for bypassing. Analog ground. Internal 5.1V reference. This point is usually bypassed. A resistor placed between this pad and IRFI2 converts the VCMP2 signal to a current for the current sense comparator. The maximum current set by the value of the resistor, according to the equation: IPEAK = 16/R. Where R is the value of the external resistor in K and must be greater than 1.5K but less than 10K. For example, if the resistor chosen is 1.8K, the peak current will be 8.8A. This assumes VCMP2 is 7.3V. Maximum output current should be kept below 10A. See IRFO2. This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to VDDA or 12V the function is disabled. Returning this pad to ground will put the IC into the thermal shutdown state. Thermal shutdown occurs at a nominal junction temperature or +120oC. This terminal is normally returned to ground. This is the main supply voltage input pad to the regulator IC. Because of the high peak currents this pad must be well bypassed with at least a 0.1F capacitor.
DESIGNATION CKIN XCKS
34 35 36 37
DGND AGND VINP IRFO2
38 39
IRFI2 TMON
40
V+
6
HIP5062 Functional Block Diagram
VDDA
SLRN
V+
SFST
PSOK
FLTN
XCKS
CKIN
VDDD
BIAS CIRCUITS
12V REG VDDA POWER SUPPLY OK
30K
VDDD
1 MHz CLOCK V+ MONITOR VDDP1 MULTIPLEXER
VDDP2
BAND GAP REF REG
DRAIN 2 GATE DRIVERS
VREF = 5.1V Q S FLIP-FLOP R FAST RESET VDDA S FLIP-FLOP Q R FAST RESET GATE DRIVERS
DRAIN 1
1A SOURCE 2 CURRENT MONITORING AMP CONTROL & BLANKING LOGIC CONTROL & BLANKING LOGIC CURRENT MONITORING AMP SOURCE 1
TO
gm SD
IRFI2 + IRF02 + 13.3K
LOW LOAD VDDA
LOW LOAD
IRFI1 + +
98K VREF 2K
VREF 98K 2K TO VREG2 OVER VOLTAGE + 11.3K 11.3K TO TO VINP
IRFO1
VCMP2 VREF TO SFST gm AMP + VREG2 31.3K VREF +
TO IFRO1 13.3K
50A
VTCN
VINP
900
VCMP1 SFST gm AMP + -
SHORT CIRCUIT VDDD 12K THERMAL MONITOR
VREF 45K
VREG1
gm SD
DGND
SHRT
PSEN
TMON
AGND
7

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