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Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications.
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 400 10.7 147 0.55 UNIT V A W
PINNING - SOT404
PIN 1 2 3 mb gate drain source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ID IDM PD PD/Tmb VGS EAS IAS Tj, Tstg Continuous drain current Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C Tmb > 25 C VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V MIN. - 55 MAX. 10.7 6.7 43 147 1.176 30 520 10 150 UNIT A A A W W/K V mJ A C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 0.85 UNIT K/W K/W
April 1997
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
ELECTRICAL CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL V(BR)DSS V(BR)DSS / Tj RDS(ON) VGS(TO) gfs IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss PARAMETER Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current Gate-source leakage current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 6 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 6 A VDS = 400 V; VGS = 0 V VDS = 320 V; VGS = 0 V; Tj = 125 C VGS = 30 V; VDS = 0 V ID = 10 A; VDD = 320 V; VGS = 10 V MIN. 400 2.0 3.5 TYP. 0.4 0.42 3.0 6.0 1 30 10 90 7 49 13 65 108 70 3.5 4.5 7.5 1080 190 110 MAX. 0.55 4.0 25 250 200 110 9 60 UNIT V V/K V S A A nA nC nC nC ns ns ns ns nH nH nH pF pF pF
VDD = 200 V; ID = 10 A; RG = 9.1 ; RD = 20
Measured from tab to centre of die Measured from drain lead solder point to centre of die Measured from source lead solder point to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL IS ISM VSD trr Qrr PARAMETER Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 10 A; VGS = 0 V IS = 10 A; VGS = 0 V; dI/dt = 100 A/s MIN. TYP. 330 4.8 MAX. 10.6 43 1.2 UNIT A A V ns C
April 1997
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1
Zth j-mb / (K/W) D= 0.5 0.2
BUKx57-mv
0.1
0.1 0.05 0.02
0.01 0 P D tp D= tp T t 1E+01
0
20
40
60
80 100 Tmb / C
120
140
0.001 1E-05 1E-03 t/s
T 1E-01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID, Drain current (Amps) Tj = 25 C
120 110 100 90 80 70 60 50 40 30 20 10 0
40
PHP10N40 10 V
30 7V 6.5 V 20 6V 5.5 V 10 5V VGS = 4.5 V 0
0
20
40
60
80 Tmb / C
100
120
140
0
5
10 15 20 VDS, Drain-Source voltage (Volts)
25
30
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V
ID / A
VD S /ID
Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms) 4.5 V 5V 5.5 V 6V 6.5 V PHP10N40
100
BUK457-400B
1
VGS = 7 V Tj = 25 C
10
R
D
S(
O
N
)=
tp = 10 us 100 us 1 ms DC
0.8 10 V 0.6
0.4
1
10 ms 100 ms
0.2
0.1 1 10 100 VDS / V 1000
0
0
5
10 15 20 25 ID, Drain current (Amps)
30
35
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS
April 1997
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
40
ID, Drain current (Amps) VDS = 30 V
PHP10N40 Tj = 25 C
4
VGS(TO) / V max.
30
3
typ.
Tj = 150 C 20
min. 2
10
1
0
0
0
2 4 6 VGS, Gate-Source voltage (Volts)
8
10
-60
-40
-20
0
20
40 60 Tj / C
80
100
120
140
Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj
gfs, Transconductance (S) VDS = 30 V PHP10N40
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
ID / A SUB-THRESHOLD CONDUCTION
10
1E-01
8
1E-02
6 150 C 4 Tj = 25 C
1E-03
2%
typ
98 %
1E-04
2
1E-05
0
1E-06
0
10
20 ID, Drain current (A)
30
40
0
1
2 VGS / V
3
4
Fig.8. Typical transconductance. gfs = f(ID); parameter Tj
a Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
PHP10N40
10000
Junction capacitances (pF)
2
Ciss 1000
1
100 Coss
Crss
0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140
10
1
10 100 VDS, Drain-Source voltage (Volts)
1000
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 6 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
April 1997
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
15
VGS, Gate-Source voltage (Volts) ID = 10 A Tj = 25 C 200 V 80 V
PHP10N40
20
IF, Source-Drain diode current (Amps) VGS = 0 V
PHP10N40
VDD = 320 V
15
10
10 150 C Tj = 25 C
5
5
0
0
50 100 Qg, Gate charge (nC)
150
0
0
0.2
0.4 0.6 0.8 1 VSDS, Source-Drain voltage (Volts)
1.2
1.4
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS
Switching times (ns) VDD = 200 V VGS = 10 V RD = 20 Ohms ID = 10 A Tj = 25 C td(off) tf tr PHP10N40
Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
1000
120 110 100 90 80 70 60 50 40 30 20 10
100
td(on) 10 0 10 20 30 40 RG, Gate resistance (Ohms) 50 60
0 20 40 60 80 100 Starting Tj ( C) 120 140
Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj V(BR)DSS @ 25 C
Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj)
1.15 1.1 1.05 1 0.95 0.9
+
L VDS VGS 0 RGS T.U.T. R 01 shunt
VDD
-ID/100
0.85 -100
-50
0 50 Tj, Junction temperature (C)
100
150
Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 C = f(Tj)
Fig.18. Unclamped inductive test circuit. 2 EAS = 0.5 LID V(BR)DSS /(V(BR)DSS - VDD )
April 1997
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max 4.5 max 1.4 max
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.19. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.20. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
April 1997
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
April 1997
7
Rev 1.000

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