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NBC12429, NBC12429A 3.3V/5V Programmable PLL Synthesized Clock Generator
25 MHz to 400 MHz
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The NBC12429 and NBC12429A are general purpose, Phase-Lock-Loop (PLL) based synthesized clock sources. The VCO will operate over a frequency range of 200 MHz to 400 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 125 kHz, 250 kHz, 500 kHz, or 1.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers. The PLL loop filter is fully integrated and does not require any external components.
MARKING DIAGRAMS
1 28
NBC12429x PLCC-28 FN SUFFIX CASE 776 AWLYYWW
* * * * * * * * * *
Best-in-Class Output Jitter Performance, 20 ps Peak-to-Peak 25 MHz to 400 MHz Programmable Differential PECL Outputs Fully Integrated Phase-Lock-Loop with Internal Loop Filter Parallel Interface for Programming Counter and Output Dividers During Powerup Minimal Frequency Overshoot Serial 3-Wire Programming Interface Crystal Oscillator Interface Operating Range: VCC = 3.135 V to 5.25 V CMOS and TTL Compatible Control Inputs Pin and Function Compatible with Motorola MC12429 and MPC9229 0C to 70C Ambient Operating Temperature (NBC12429)
NBC12429x LQFP-32 FA SUFFIX CASE 873A AWLYYWW 32 1 x A WL YY WW = Blank or A = Assembly Location = Wafer Lot = Year = Work Week
* * -40C to 85C Ambient Operating Temperature (NBC12429A) * Pb-Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2004
1
November, 2004 - Rev. 3
Publication Order Number: NBC12429/D
NBC12429, NBC12429A
+3.3 or 5.0 V 1 PLL_VCC PHASE DETECTOR VCO XTAL1 OSC 5 XTAL2 9-BIT B M COUNTER BN (1, 2, 4, 8) 24 23 FOUT FOUT VCC
B 16
1 MHz FREF with 16 MHz Crystal
+3.3 or 5.0 V 21, 25
4 10-20 MHz
200-400 MHz
20 OE 6 LATCH 28 7 0 27 9-BIT SR 26 1 0 1 LATCH LATCH
TEST
S_LOAD P_LOAD
S_DATA S_CLOCK
2-BIT SR
3-BIT SR
8 16 9 M[8:0]
17, 18 2 N[1:0]
22, 19
Figure 1. Block Diagram (PLCC-28) Table 1. Output Division
N[1:0] 00 01 10 11 FOUT FOUT GND VCC VCC Output Division 1 2 4 8 TEST GND
Table 2. XTAL_SEL and OE
Input OE 0 Outputs Disabled 1 Outputs Enabled
TEST
26
FOUT
FOUT
GND
25
24
23
22
21
20
19 18
S_CLOCK S_DATA S_LOAD PLL_VCC NC NC XTAL1
26
N[1]
32 31 30 29 28 27 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
GND
VCC
VCC
VCC
27
17
N[0] M[8] M[7] M[6] M[5] M[4]
S_CLOCK S_DATA
1 2 3 4 5 6 7 8
N/C N[1] N[0] M[8] M[7] M[6] M[5] M[4]
28
16
S_LOAD PLL_VCC PLL_VCC N/C N/C XTAL1
1
15
2
14
3
13
4 5 6 7 8 9 10 11
12
M[0]
M[1]
M[2]
XTAL2
P_LOAD
M[3]
M[0]
M[1]
M[2]
XTAL2
M[3]
Figure 2. PLCC-28 (Top View) http://onsemi.com
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Figure 3. LQFP-32 (Top View)
P_LOAD
N/C
OE
OE
NBC12429, NBC12429A
The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge.
Table 3. PIN FUNCTION DESCRIPTION
Pin Name INPUTS XTAL1, XTAL2 S_LOAD* Crystal Inputs CMOS/TTL Serial Latch Input (Internal Pulldown Resistor) CMOS/TTL Serial Data Input (Internal Pulldown Resistor) CMOS/TTL Serial Clock Input (Internal Pulldown Resistor) CMOS/TTL Parallel Latch Input (Internal Pullup Resistor) These pins form an oscillator when connected to an external series-resonant crystal. This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. This pin acts as the data input to the serial configuration shift registers. This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation. These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD. Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. Function Description
S_DATA* S_CLOCK* P_LOAD**
M[8:0]** N[1:0]** OE** OUTPUTS FOUT, FOUT TEST POWER VCC PLL_VCC GND
CMOS/TTL PLL Loop Divider Inputs (Internal Pullup Resistor) CMOS/TTL Output Divider Inputs (Internal Pullup Resistor) CMOS/TTL Output Enable Input (Internal Pullup Resistor)
PECL Differential Outputs CMOS/TTL Output
These differential, positive-referenced ECL signals (PECL) are the outputs of the synthesizer. The function of this output is determined by the serial configuration bits T[2:0].
Positive Supply for the Logic Positive Supply for the PLL Negative Power Supply
The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V. This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. These pins are the negative supply for the chip and are normally all connected to ground.
* When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH.
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NBC12429, NBC12429A
Table 4. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model PLCC LQFP Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 2 kV > 150 V > 1 kV Level 1 Level 2 UL 94 V-0 @ 0.125 in 2035
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol VCC VI Iout TA Positive Supply Input Voltage Output Current Operating Temperature Range NBC12429 NBC12429A Tstg qJA qJC qJA qJC Tsol Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board < 2 to 3 sec @ 248C PLCC-28 PLCC-28 PLCC-28 LQFP-23 LQFP-23 LQFP-23 0 to 70 -40 to +85 -65 to +150 63.5 43.5 22 to 26 80 55 12 to 17 265 C C/W C/W C/W C/W C/W C/W C Parameter Condition 1 GND = 0 V GND = 0 V Continuous Surge VI VCC Condition 2 Rating 6 6 50 100 Unit V V mA mA C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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NBC12429, NBC12429A
Table 6. DC CHARACTERISTICS (VCC = 3.3 V 5%; TA = 0C to 70C (NBC12429), TA = -40C to 85C (NBC12429A))
Symbol VIH LVCMOS/ LVTTL VIL LVCMOS/ LVTTL IIN VOH VOL VOH PECL VOL PECL ICC Input HIGH Voltage Characteristic Condition VCC = 3.3 V Min 2.0 Typ Max Unit V
Input LOW Voltage
VCC = 3.3 V
0.8
V
Input Current Output HIGH Voltage TEST Output LOW Voltage TEST Output HIGH Voltage Output LOW Voltage Power Supply Current FOUT FOUT FOUT FOUT VCC PLL_VCC VCC = 3.3 V (Notes 2, 3) VCC = 3.3 V (Notes 2, 3) 2.155 1.355 48 18 58 22 IOL = 0.8 mA IOH = -0.8 mA 2.5
1.0
mA V
0.4 2.405 1.605 70 26
V V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. FOUT/FOUT output levels will vary 1:1 with VCC variation. 3. FOUT/FOUT outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 7. DC CHARACTERISTICS (VCC = 5.0 V 5%; TA = 0C to 70C (NBC12429), TA = -40C to 85C (NBC12429A))
Symbol VIH CMOS/ TTL VIL CMOS/ TTL IIN VOH VOL VOH PECL VOL PECL ICC Input HIGH Voltage Characteristic Condition VCC = 5.0 V Min 2.0 Typ Max Unit V
Input LOW Voltage
VCC = 5.0 V
0.8
V
Input Current Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Power Supply Current TEST TEST FOUT FOUT FOUT FOUT VCC PLL_VCC IOH = -0.8 mA IOL = 0.8 mA VCC = 5.0 V (Notes 4, 5) VCC = 5.0 V (Notes 4, 5) 3.855 3.055 50 19 60 23 2.5
1.0
mA V
0.4 4.105 3.305 75 27
V V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. FOUT/FOUT output levels will vary 1:1 with VCC variation. 5. FOUT/FOUT outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V 5%; TA = 0C to 70C (NBC12429), TA = -40C to 85C
(NBC12429A)) (Note 6) Symbol FMAXI FMAXO tjitter(pd) tjitter(cyc-cyc) tLOCK ts Characteristic Maximum Input Frequency Maximum Output Frequency Period Jitter (RMS) Cycle-to-Cycle Jitter (Peak-to-Peak) Maximum PLL Lock Time Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD S_LOAD P_LOAD 20 20 20 20 20 50 50 47.5 FOUT 20%-80% 175 52.5 425 S_CLOCK Xtal Oscillator VCO (Internal) FOUT (1s) (8s) 50 MHz v fOUT < 100 MHz 100 MHz v fOUT < 800 MHz 50 MHz v fOUT < 100 MHz 100 MHz v fOUT < 800 MHz (Note 7) 10 200 25 Condition Min Max 10 20 400 400 8 5 "40 "20 10 Unit MHz MHz ps ps ms ns
th tpwMIN DCO tr, tf
Hold Time Minimum Pulse Width Output Duty Cycle Output Rise/Fall
ns ns % ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. FOUT/FOUT outputs are terminated through a 50 W resistor to VCC - 2.0 V. 7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6.
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NBC12429, NBC12429A
FUNCTIONAL DESCRIPTION The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 16 before being sent to the phase detector. With a 16 MHz crystal, this provides a reference frequency of 1 MHz. Although this data sheet illustrates functionality only for a 16 MHz crystal, Table 9, any crystal in the 10 MHz - 20 MHz range can be used, Table 11. The VCO within the PLL operates over a range of 200 to 400 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector. The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve loop lock. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4, or 8). This divider extends the performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated into 50 W to VCC - 2.0 V. The positive reference for the output driver and the internal logic is separated from the power supply for the PLL to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally upon system reset, the P_LOAD input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the chip. The serial interface logic is implemented with a fourteen bit shift register scheme. The register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. With P_LOAD held high, the configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information.
Table 9. Programming VCO Frequency Function Table with 16 MHz Crystal
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VCO Frequency Freq ency (MHz) 200 201 202 203 * * * 256 M8 0 0 0 0 * * * 128 M7 1 1 1 1 * * * 64 32 16 8 4 2 1 MC t Count Divisor 200 201 202 203 * * * M6 1 1 1 1 * * * M5 0 0 0 0 * * * M4 0 0 0 0 * * * M3 1 1 1 1 * * * M2 0 0 0 0 * * * M1 0 0 1 1 * * * M0 0 1 0 1 * * * 397 398 399 400 397 398 399 400 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 0
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NBC12429, NBC12429A
PROGRAMMING INTERFACE Programming the NBC12429 and NBC12429A is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula:
FOUT + (FXTAL B 16) MBN
(eq. 1)
The input frequency and the selection of the feedback divider M is limited by the VCO frequency range and FXTAL. M must be configured to match the VCO frequency range of 200 MHz to 400 MHz in order to achieve stable PLL operation.
M min + fVCOmin B (fXTAL B 16) and M max + fVCOmax B (fXTAL B 16)
(eq. 3) (eq. 4)
where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 M 400 for a 16 MHz input reference. Assuming that a 16 MHz reference frequency is used the above equation reduces to:
FOUT + M B N
(eq. 2)
Substituting the four values for N (1, 2, 4, 8) yields:
Table 10. Programmable Output Divider Function
N1 0 0 1 1
N0 0 1 0 1
N Divider B1 B2 B4 B8
FOUT M
Output Frequency Range (MHz)* 200-400 100-200 50-100 25-50
FOUT Step
1 MHz
MB2 MB4 MB8
500 kHz 250 kHz 125 kHz
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the desired frequency from the above equations. The four output frequency ranges established by N are 200 MHz - 400 MHz, 100 MHz - 200 MHz, 50 MHz - 100 MHz and 25 MHz - 50 MHz, respectively. From these ranges, the user will establish the value of N required. The value of M can then be calculated based on Equation 1. For example, if an output frequency of 131 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 131 MHz falls within the frequency range set by an N value of 2; thus, N [1:0] = 01. For N = 2, FOUT = M / 2 and M = 2 x FOUT. Therefore,
M + 131 2 + 262, soM[8 : 0] + 100000110.
Following this same procedure, a user can generate any whole frequency desired between 25 and 400 MHz. Note that for N > 2, fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus, the indicator of the fractional output frequencies achievable) will be equal to FXTAL / 16 / N. For input reference frequencies other than 16 MHz, see Table 11, which shows the usable VCO frequency and M divider range.
The value for M falls within the constraints set for PLL stability. If the value for M fell outside of the valid range, a different N value would be selected to move M in the appropriate direction. The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW, the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port, the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final nine bits of the data stream on the S_DATA input. For each register, the most significant bit is loaded first (T2, N1, and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figures 4 and 5 illustrate the timing diagram for both a parallel and a serial load of the device synthesizer. M[8:0] and N[1:0] are normally specified once at powerup through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. The T2, T1, and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin.
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NBC12429, NBC12429A
Table 11. Frequency Operating Range
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VCO Frequency Range for a Crystal Frequency of: 10 12 14 16 Output Frequency for FXTAL = 16 MHz and for N = B2 B4 M M[8:0] 18 20 B1 B8 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101101000 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 111001100 111010110 111100000 111101010 111110100 111111110 200 206.25 212.5 218.75 225 231.25 237.5 243.75 250 256.25 262.5 268.75 275 281.25 287.5 293.75 300 306.25 312.5 318.75 202.5 210 217.5 225 232.5 240 247.5 255 262.5 270 277.5 285 292.5 300 307.5 315 322.5 330 337.5 345 352.5 360 367.5 375 382.5 201.25 210 218.75 227.5 236.25 245 253.75 262.5 271.25 280 288.75 297.5 306.25 315 323.75 332.5 341.25 350 358.75 367.5 376.25 385 393.75 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 200 212.5 225 202.5 213.75 225 236.25 247.5 258.75 270 281.25 292.5 303.75 315 326.25 337.5 348.75 360 371.25 382.5 393.75 237.5 250 262.5 275 287.5 300 312.5 325 337.5 350 362.5 375 387.5 400 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 90 92.5 95 97.5 100 25 26.25 27.5 28.75 30 31.25 32.5 33.75 35 36.25 37.5 38.75 40 41.25 42.5 43.75 45 46.25 47.5 48.75 50
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Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110, the device is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 6 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 250 MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 250 MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented.
T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST (Pin 20) SHIFT REGISTER OUT HIGH FREF M COUNTER OUT FOUT LOW PLL BYPASS FOUT B 4
M[8:0] N[1:0] P_LOAD
M, N
Figure 4. Parallel Interface Timing Diagram
S_CLOCK
S_DATA
T2 T1 First Bit
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0 Last Bit
S_LOAD
Figure 5. Serial Interface Timing Diagram
FREF MCNT SCLOCK M COUNTER PLL 12429
VCO_CLK 0 1 SEL_CLK FDIV4 MCNT LOW FOUT MCNT FREF HIGH NB (1, 2, 4, 8) FOUT (VIA ENABLE GATE)
7 TEST MUX 0 TEST
LATCH Reset SDATA SHIFT REG T0 14-BIT T1 T2 SLOAD PLOAD DECODE
T2=T1=1, T0=0: Test Mode SCLOCK is selected, MCNT is on TEST output, SCLOCK B N is on FOUT pin. PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
* *
Figure 6. Serial Test Clock Block Diagram
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APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator Power Supply Filtering
The NBC12429 and NBC12429A feature a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the device as possible to avoid any board level parasitics. To facilitate co-location, surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the crystal terminals, loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance, it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required, it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 W and 1 kW. The oscillator circuit is a series resonant circuit and thus, for optimum performance, a series resonant crystal should be used. Unfortunately, most crystals are characterized in a parallel resonant mode. Fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result, a parallel resonant crystal can be used with the device with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified (a few hundred ppm translates to kHz inaccuracies). In a general computer application, this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the device.
Table 12. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75 ppm at 25C 150 ppm 0 to 70C 0 to 70C 5-7 pF 50 to 80 W 100 mW 5 ppm/Yr (First 3 Years)
The NBC12429 and NBC12429A are mixed analog/digital products and as such, exhibit some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NBC12429 and NBC12429A provide separate power supplies for the digital circuitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog PLL. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the NBC12429 and NBC12429A. Figure 7 illustrates a typical power supply filter scheme. The NBC12429 and NBC12429A are most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the NBC12429 and NBC12429A. From the data sheet, the PLL_VCC current (the current sourced through the PLL_VCC pin) is typically 23 mA (27 mA maximum). Assuming that a minimum of 2.8 V must be maintained on the PLL_VCC pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 7 must have a resistance of 10 - 15 W to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL.
3.3 V or 5.0 V 3.3 V or 5.0 V
RS = 10-15 W PLL_VCC NBC12429 NBC12429A VCC 0.01 mF 22 mF 0.01 mF
L=1000 mH R=15 W
*See accompanying text for series versus parallel resonant discussion.
Figure 7. Power Supply Filter
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NBC12429, NBC12429A
A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. Figure 7 shows a 1000 mH choke. This value choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin, a low DC resistance inductor is required (less than 15 W). Generally, the resistor/capacitor filter will be cheaper, easier to implement, and provide an adequate level of supply filtering. The NBC12429 and NBC12429A provide sub-nanosecond output edge rates and therefore a good power supply bypassing scheme is a must. Figure 8 shows a representative board layout for the NBC12429 and NBC12429A. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 8 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NBC12429 and NBC12429A outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors.
C1 C1 T0 T1 TJITTER(cycle-cycle) = T1 - T0
Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. Although the NBC12429 and NBC12429A have several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise-related problems in most designs.
Jitter Performance
Jitter is a common parameter associated with clock generation and distribution. Clock jitter can be defined as the deviation in a clock's output transition from its ideal position. Cycle-to-Cycle Jitter (short-term) is the period variation between two adjacent cycles over a defined number of observed cycles. The number of cycles observed is application dependent but the JEDEC specification is 1000 cycles.
R1 1 C3 C2 R1 = 10-15 W C1 = 0.01 mF C2 = 22 mF C3 = 0.1 mF Xtal
= VCC = GND = Via
RMS or one Sigma Jitter
Figure 8. PCB Board Layout (PLCC-28)
Time
Typical Gaussian Distribution
Figure 10. Peak-to-Peak Jitter
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Peak-to-Peak Jitter (8 s)
Jitter Amplitude
EEE EEE EEE EEE EEE EEE EE EE EE EE
Figure 9. Cycle-to-Cycle Jitter
Peak-to-Peak Jitter is the difference between the highest and lowest acquired value and is represented as the width of the Gaussian base.
NBC12429, NBC12429A
There are different ways to measure jitter and often they are confused with one another. The typical method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period-to-period or cycle-to-cycle. If the scope is set up to trigger on every rising or falling edge, set to infinite persistence mode and allowed to trace sufficient cycles, it is possible to determine the maximum and minimum periods of the timing signal. Digital scopes can accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. These scopes can also store a finite number of period durations and post-processing software can analyze the data to find the maximum and minimum periods. Recent hardware and software developments have resulted in advanced jitter measurement techniques. The Tektronix TDS-series oscilloscopes have superb jitter analysis capabilities on non-contiguous clocks with their histogram and statistics capabilities. The Tektronix TDSJIT2/3 Jitter Analysis software provides many key timing parameter measurements and will extend that capability by making jitter measurements on contiguous clock and data cycles from single-shot acquisitions. M1 by Amherst was used as well and both test methods correlated. This test process can be correlated to earlier test methods and is more accurate. All of the jitter data reported on the NBC12429 and NBC12429A was collected in this manner.
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Figure 12 shows the jitter as a function of the output frequency. The graph shows that for output frequencies from 25 to 400 MHz the jitter falls within the "20 ps peak-to-peak specification. The general trend is that as the output frequency is increased, the output edge jitter will decrease. Figure 11 illustrates the RMS jitter performance of the NBC12429 and NBC12429A across specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency. However, the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter. Long-Term Period Jitter is the maximum jitter observed at the end of a period's edge when compared to the position of the perfect reference clock's edge and is specified by the number of cycles over which the jitter is measured. The number of cycles used to look for the maximum jitter varies by application but the JEDEC spec is 10,000 observed cycles. The NBC12429 and NBC12429A exhibit long term and cycle-to-cycle jitter, which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility associated with a synthesizer over a fixed frequency oscillator. The jitter data presented should provide users with enough information to determine the effect on their overall timing budget. The jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. These features are not available with a fixed frequency SAW oscillator.
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20 RMS JITTER (ps) RMS JITTER (ps) 300 350 400
20
15
15
10
N=8
10
N=4
5 N=1 0 200 N=2 250 VCO FREQUENCY (MHz)
5 0 50 100 150 200 250 300 350 400 OUTPUT FREQUENCY (MHz)
Figure 11. RMS Jitter vs. VCO Frequency
Figure 12. RMS Jitter vs. Output Frequency
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NBC12429, NBC12429A
S_DATA
S_CLOCK tHOLD
tSETUP
Figure 13. Setup and Hold
S_DATA tHOLD
S_LOAD
tSETUP
Figure 14. Setup and Hold
M[8:0]
N[1:0]
P_LOAD tSETUP tHOLD
Figure 15. Setup and Hold
FOUT
FOUT Pulse Width tPERIOD
DCO +
Figure 16. Output Duty Cycle
tpw tPERIOD
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NBC12429, NBC12429A
Zo = 50 W
FOUT Driver Device FOUT
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NBC12429FA NBC12429FAG NBC12429FAR2 NBC12429FAR2G NBC12429FN NBC12429FNG NBC12429FNR2 NBC12429AFA NBC12429AFAR2 NBC12429AFN NBC12429AFNR2 Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 LQFP-32 LQFP-32 PLCC-28 PLCC-28 Shipping 250 Units / Rail 250 Units / Rail 2000 / Tape & Reel 2000 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 250 Units / Rail 2000 / Tape & Reel 37 Units / Rail 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NBC12429, NBC12429A
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
E G G1 0.010 (0.250)
S
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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NBC12429, NBC12429A
PACKAGE DIMENSIONS
A
32
4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V
AE P AE
17
V1
DETAIL Y
BASE METAL
N -Z- 9 S1 S
8X 4X
F
D
M_ R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC _ 1 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC _ 1 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
K
Q_
GAUGE PLANE
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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0.20 (0.008)
0.20 (0.008) AC T-U Z
EE EE EE
9
M
AC T-U Z
DETAIL Y
-T-, -U-, -Z-
LQFP-32 FA SUFFIX PLASTIC LQFP PACKAGE CASE 873A-02 ISSUE B
NBC12429, NBC12429A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NBC12429/D

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