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NB6N239S 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT /1/2/4/8, /2/4/8/16 Clock Divider
Description
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16 1
The NB6N239S is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive LVDS compatible outputs. (More device information on page 7). The NB6N239S is a member of the ECLinPS MAXTM family of high performance clock products.
Features
1 Bottom View QFN-16 MN SUFFIX CASE 485G A L Y W G
* * * * * * * * * * * * * *
Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1) Input Compatibility with LVDS/LVPECL/CML/HSTL Rise/Fall Time 120 ps Typical < 5 ps Typical Within Device Output Skew Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz Outputs Internal 50 W Termination Provided Random Clock Jitter < 2 ps RMS QA B1 Edge Aligned to QB Bn Edge Operating Range: VCC = 3.0 V to 3.465 V with GND = 0 V Master Reset for Synchronization of Multiple Chips VBBAC Reference Output Synchronous Output Enable/Disable TIA/EIA - 644 Compliant Pb-Free Packages are Available
NB6N 239S ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
SELA0 SELA1 CLK VT CLK VBBAC 50 W 50 W R B2 B4 B B8 B16 B1 B2 A B4 B8 QA QA
QB QB
EN SELB0 SELB1 MR
+
Figure 1. Simplified Logic Diagram
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 3
1
Publication Order Number: NB6N239S/D
NB6N239S
MR 16 VT CLK CLK VBBAC 1 2 NB6N239S 3 4 5 EN 6 7 8 10 9 SELA0 SELA1 VCC 15 14 13 12 11 QA QA QB QB
SELB0 SELB1 GND Exposed Pad (EP)
Figure 2. Pinout: QFN-16 (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VT CLK CLK VBBAC EN* SELB0* SELB1* GND QB QB QA QA VCC SELA1* SELA0* MR** EP LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply LVDS Output LVDS Output LVDS Output LVDS Output Power Supply LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply (OPT) LVDS, LVPECL, CML, HSTL Input LVDS, LVPECL, CML, HSTL Input I/O Description Internal 100 W Center-Tapped Termination Pin for CLK and CLK. Noninverted Differential CLOCK Input. Inverted Differential CLOCK Input. Output Voltage Reference for Capacitor Coupled Inputs, only. Synchronous Output Enable Clock Divide Select Pin Clock Divide Select Pin Negative Supply Voltage Inverted Differential Output. Typically terminated with 100 W across differential outputs. Noninverted Differential Output. Typically terminated with 100 W across differential outputs. Inverted Differential Output. Typically terminated with 100 W across differential outputs. Noninverted Differential Output. Typically terminated with 100 W across differential outputs. Positive Supply Voltage. Clock Divide Select Pin Clock Divide Select Pin Master Reset Asynchronous, Default Open High, Asserted LOW The Exposed Pad on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board.
*Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.
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NB6N239S
+
SELA0 VCC SELA1 B1 B2 B4 R B8
CLK VT CLK 50 W 50 W
A
QA QA
R B2 B EN SELB0 SELB1 MR VBBAC B4 B8 B16
QB QB
+
GND
Figure 3. Logic Diagram Table 2. FUNCTION TABLE
CLK EN* L H X MR** H H L FUNCTION Divide Hold Q Reset Q
X
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1* L L H H SELA0* L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1* L L H H SELB0* L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16
= Low-to-High Transition = High-to-Low Transition X = Don't Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.
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NB6N239S
Table 5. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Value 75 kW 75 kW > 1500 V > 100 V > 1000 V Pb-Free Pkg Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) QFN-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 370
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol VCC VI ISC Input Voltage Output Short Circuit Current TIA/EIA - 644 Compliant IBBAC TA Tstg qJA qJC Tsol VBBAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board Line-to-Line Line-to-GND Parameter Positive Mode Power Supply Condition 1 GND = 0 V GND = 0 V GND v VI v VCC Condition 2 Rating 3.6 3.6 12 24 0.5 -40 to +85 -65 to +150 41.6 35.2 4.0 265 265 Unit V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NB6N239S
Table 7. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
(VCC = 3.0 V to 3.465 V, GND = 0 V)
-405C Symbol ICC Characteristic Power Supply Current (Inputs and Outputs OPEN) Output HIGH Voltage (Notes 2) Output LOW Voltage (Notes 2) Differential Output Voltage (Figure 21) VOD Magnitude Change Offset Voltage (Figure 21) VOS Magnitude Change 900 1600 900 450 50 1375 50 250 0 1125 0 450 50 1375 50 Min Typ Max Min 35 255C Typ 45 Max 55 Min 85C Typ Max Unit mA
VOH VOL VOD DVOD VOS DVOS
1600 900 250 0 1125 0
1600
mV mV
250 0 1125 0
450 50 1375 50
mV mV mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 7, 10)
Vth Input Threshold Reference Voltage (Note 3) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Output Voltage Reference @ 100 mA (Note 6) VCC = 3.3 V 100 VCC - 100 100 VCC - 100 100 VCC - 100 mV
VIH VIL VBBAC
Vth + 100 GND VCC-1460 1840 VCC- 1330 1970
VCC Vth - 100 VCC-1200 2100
Vth + 100 GND VCC-1460 1840 VCC- 1340 1960
VCC Vth - 100 VCC-1200 2100
Vth + 100 GND VCC-1460 1840 VCC- 1350 1950
VCC Vth - 100 VCC-1200 2100
mV mV mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 5)
VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross-point Voltage) (Note 4) Differential Input Voltage (VIHD(CLK) - VILD(CLK)) and (VIHD(CLK) - VILD(CLK)) Internal Input Termination Resistor 100 GND 50 VCC VCC - 100 VCC - 50 100 GND 50 VCC VCC - 100 VCC - 50 100 GND 50 VCC VCC - 100 VCC - 50 mV mV mV
VID
100
VCC - GND
100
VCC - GND
100
VCC - GND
mV
RTIN
45
50
55
45
50
55
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Outputs loaded with 100 W across LVDS outputs. 3. Vth is applied to the complementary input when operating in single-ended mode. 4. VCMRMIN varies 1:1 with GND, VCMRMAX varies 1:1 with VCC. 5. Input and output voltage swing is a single-ended measurement operating in differential mode. 6. VBBAC used to rebias capacitor-coupled inputs only (see Figures 16 and 17).
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NB6N239S
Table 8. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 3.0 V to 3.465 V, GND = 0 V, TA = -40C to +85C)
Symbol VIH VIL IIH IIL Characteristic Input HIGH Voltage (LVCMOS/LVTTL) Input LOW Voltage (LVCMOS/LVTTL) Input HIGH Current Input LOW Current Min 2.0 GND -150 -150 Typ Max VCC 0.8 150 150 Unit V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 9. AC CHARACTERISTICS VCC = 3.0 V to 3.465 V; GND = 0 V (Note 7)
-40C Symbol finMAX Characteristic Maximum Input CLOCK Frequency QA/QB = (B2, B4, B8, B16) QA = (B1) Output Voltage Amplitude (Notes 9, 10) QA(B2, 4, 8), QB(Bn) fin v 3.0 GHz QA(B1), QB(Bn) fin v 1.5 GHz Propagation Delay to Output Differential @ 50 MHz Reset Recovery Setup Time @ 50 MHz Hold Time @ 50 MHz Within-Device Skew @ 50 MHz Device-to-Device Skew Duty Cycle Skew Minimum Pulse Width RMS Random Clock Jitter Input Voltage Swing (Differential Configuration) (Note 9) Output Rise/Fall Times @ 50 MHz (20% - 80%) Qn, Qn 100 70 120 EN, CLK SELA/B, CLK CLK, EN CLK, SELA/B (Note 8) (Note 8) (Note 8) MR 550 2 VCC -GND 190 100 70 120 CLK, Qn MR, Qn Min 3.0 1.5 200 200 550 420 0 0 0 150 700 -90 -60 -300 65 200 5 25 25 30 80 40 550 2 VCC -GND 190 100 70 120 350 350 450 450 780 660 Typ Max Min 3.0 1.5 200 200 550 420 0 0 0 150 700 -90 -60 -300 65 200 5 30 30 30 90 45 550 2 VCC -GND 190 350 350 450 450 780 660 25C Typ Max Min 3.0 1.5 200 200 550 420 0 0 0 150 700 -90 -60 -300 65 200 6 30 30 35 90 45 350 350 450 450 780 660 85C Typ Max Unit GHz
VOUTPP
mV
tPLH, tPHL tRR ts th tskew
ps ps ps ps ps
tPW tJITTER VINPP tr tf
ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured using a 750 mV, 50% duty cycle clock source. All loading with 100 W across LVDS outputs. 8. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 9. Input and output voltage swing is a single-ended measurement operating in differential mode. 10. Output Voltage Amplitude (VOHCLK - VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz.
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NB6N239S
Application Information single-ended input capacitor-coupled CLOCK signals. For The NB6N239S is a high-speed, low skew clock divider the capacitor-coupled CLK and/or CLK inputs, VBBAC with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider should be connected to the VT pin and bypassed to ground circuits drive differential LVDS compatible outputs. The with a 0.01 mF capacitor. Inputs CLK and CLK must be internal dividers are synchronous to each other. Therefore, signal driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6N239S clock inputs can be driven by a variety of internal divider flip-flops will only be enabled/disabled differential signal level technologies including LVDS, when the internal clock is in the LOW state. This avoids any LVPECL, HSTL, or CML. The differential clock input chance of generating a runt pulse on the internal clock when buffer employs a pair of internal 50 W termination resistors the device is enabled/disabled, as can happen with an asynchronous control. The internal enable flip-flop is in a 100 W center-tapped configuration and accessible via clocked on the falling edge of the input clock. Therefore, all the VT pin. This feature provides transmission line associated specification limits are referenced to the negative termination on-chip, at the receiver end, eliminating edge of the clock input. external components. The VBBAC reference output is recommended to be used to rebias differential or
MR
CLK Q (/1) Q (/2) Q (/4) Q (/8) Q (/16)
Figure 4. Timing Diagram
CLK tRR MR tRR
Q (/n)
NOTE:
On the rising edge of MR, Q goes HIGH after the first rising edge of CLK.
Figure 5. Master Reset Timing Diagram
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NB6N239S
Internal Clock Disabled CLK Q (/n) EN Internal Clock Enabled
Figure 6. Output Enable Timing Diagrams
The EN signal will "freeze" the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip-flops will "unfreeze" and continue to their next state count with proper phase relationships.
CLK
VIH VIL Vth
CLK
Figure 7. Differential Input Driven Single-Ended
CLK CLK VID = |VIHD(CLK) - VILD(CLK)| VIHD VILD
Vth
CLK
CLK
Figure 8. Differential Inputs Driven Differentially
Figure 9. Differential Inputs Driven Differentially
VCC Vthmax CLK Vth Vthmin GND VIHmin CLK VILmin VCC VCMmax
VIHmax VILmax
VIHDmax VILDmax
VCMR
VCMmin GND
VIHDmin VILDmin
Figure 10. Vth Diagram
Figure 11. VCMR Diagram
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NB6N239S
VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V
Zo = 50 W LVPECL Driver VT = VCC - 2.0 V
NB6N239S CLK 50 W 50 W LVDS Driver
Zo = 50 W VT = OPEN
NB6N239S CLK 50 W 50 W
Zo = 50 W
CLK
Zo = 50 W
CLK
GND
GND
GND
GND
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
Zo = 50 W CML Driver VT = VCC
NB6N239S CLK 50 W 50 W HSTL Driver
Zo = 50 W VT = GND
NB6N239S CLK 50 W 50 W
Zo = 50 W
CLK
Zo = 50 W
CLK
GND
GND
GND
GND
Figure 14. Standard 50 W Load CML Interface
Figure 15. Standard 50 W Load HSTL Interface
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 3.3 V
Zo = 50 W Differential Driver VT = VBBAC*
NB6N239S CLK 50 W 50 W Single-Ended Driver
Zo = 50 W VT = VBBAC*
NB6N239S CLK 50 W 50 W CLK
Zo = 50 W
CLK
VEE
VEE
VEE
VEE
Figure 16. Capacitor-Coupled Differential Interface (VT Connected to VBBAC)
Figure 17. Capacitor-Coupled Single-Ended Interface (VT Connected to VBBAC)
*VBBAC bypassed to ground with a 0.01 mF capacitor.
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NB6N239S
VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 400
300
200
100
0
0
0.5
1.0
1.5
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 18. Output Voltage Amplitude (VOUTPP) versus Output Clock Frequency at 255C (Typical) fout (QA/QB) = fin B n; For n = 2, 4, 8, 16; fin v 3.0 GHz For n = 1; fin v 1.5 GHz
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q Q tPHL tPLH VOUTPP = VOH(Q) - VOL(Q)
Figure 19. AC Reference Measurement
NB6N239S Q Zo = 50 W 100 W Q Zo = 50 W D D
LVDS Driver Device
LVDS Receiver Device
Figure 20. Typical LVDS Termination for Output Driver and Device Evaluation, If Receiver Has On-chip Termination, 100 W Resistor is Not Needed
QN VOS QN VOD
VOH
VOL
Figure 21. LVDS Output http://onsemi.com
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NB6N239S
ORDERING INFORMATION
Device NB6N239SMN NB6N239SMNG NB6N239SMNR2 NB6N239SMNR2G Package QFN-16, 3 x 3 mm QFN-16, 3 x 3 mm (Pb-Free) QFN-16, 3 x 3 mm QFN-16, 3 x 3 mm (Pb-Free) Shipping 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB6N239S
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C 0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
0.10 C A B 0.05 C
NOTE 3
ECLinPS and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CCC CCC
TOP VIEW SIDE VIEW D2
5
E
(A3) A A1
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
C 0.575 0.022
EXPOSED PAD
e
8
EXPOSED PAD
9
E2
12
e
3.25 0.128
1.50 0.059
b BOTTOM VIEW 0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB6N239S/D

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