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MC74VHCT157A Quad 2-Channel Multiplexer
The MC74VHCT157A is an advanced high speed CMOS quad 2-channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It consists of four 2-input digital multiplexers with common select (S) and enable (E) inputs. When E is held High, selection of data is inhibited and all the outputs go Low. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V because it has full 5.0 V CMOS level output swings. The VHCT157A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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16 SOIC-16 D SUFFIX CASE 751B 1 1 VHCT157AG AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 1 VHCT 157A ALYWG G
* * * * * * * * * * * *
High Speed: tPD = 4.1 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 82 FETs or 20 Equivalent Gates Pb-Free Packages are Available*
16 SOEIAJ-16 M SUFFIX CASE 966 1 1 74VHCT157 ALYWG
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
Inputs E H L L S X L H Outputs Y0 - Y3 L A0 -A3 B0 -B3
A0 - A3, B0 - B3 = the levels of the respective Data-Word Inputs.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
December, 2005 - Rev. 2
Publication Order Number: MC74VHCT157A/D
MC74VHCT157A
S A0 B0 Y0 A1 B1 Y1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC E A3 B3 Y3 A2 B2 Y2
Figure 1. Pin Assignment
A0 B0 A1 B1 A2 B2 A3 B3 E S
2 3 5 6 11 10 14 13 15 1 12 Y3 9 Y2 7 Y1 DATA OUTPUTS 4 Y0
NIBBLE INPUTS
Figure 2. Expanded Logic Diagram
E S A0 B0 A1 B1 A2 B2 A3 B3
15 1 2 3 5 6 11 10 14 13
EN G1 1 1 MUX 4 7 9 12 Y0 Y1 Y2 Y3
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Figure 3. IEC Logic Symbol
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MC74VHCT157A
MAXIMUM RATINGS (Note 1)
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125C (Note 5) SOIC Package TSSOP SOIC Package TSSOP Output in 3-State High or Low State Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance
mA C/W
Thermal Resistance, Junction-to-Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22-A114-A 3. Tested to EIA/JESD22-A115-A 4. Tested to JESD22-C101-A 5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 5.0 V + 0.5 V Output in 3-State High or Low State Characteristics Min 4.5 0 0 -55 0 Max 5.5 5.5 VCC 125 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 4. Failure Rate vs. Time Junction Temperature
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MC74VHCT157A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 8 mA IIN ICC ICCT Input Leakage Current Maximum Quiescent Supply Current Additional Quiescent Supply Current (per Pin) VIN = 5.5 V or GND VIN = VCC or GND Any one input: VIN = 3.4 V All other inputs: VIN = VCC or GND VOUT = 5.5 V Condition (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 4.4 3.94 0.0 0.1 0.36 0.1 4.0 1.35 4.5 Min 2 0.8 TA = 25C Typ Max TA 85C Min 2 Max 0.8 0.8 -55C TA 125C Min 2 0.8 Max Unit V V V 4.4 3.8 0.1 0.44 1.0 40.0 1.5 4.4 3.66 V 0.1 0.52 1.0 40.0 1.5 mA mA mA
IOPD
Output Leakage Current
0
0.5
5
5
mA
II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III III III IIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I I IIII I I I I I IIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II IIIIIIIIIII I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I I II I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIII III III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I II I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Typ 5.6 8.0 4.1 5.6 6.1 8.5 5.3 6.8 6.1 8.5 5.6 7.1 4 TA = 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 7.7 11.0 7.5 9.5 -55C TA 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 7.7 11.0 7.5 9.5 Symbol tPLH, tPHL Parameter Test Conditions Min Max Unit ns Maximum Propagation Delay; A to B to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 7.0 10.0 6.4 8.4 tPLH, tPHL Maximum Propagation Delay; S to Y 7.5 10.5 8.1 10.1 7.5 10.5 8.6 10.6 10 8.2 11.5 9.5 11.5 8.2 11.5 8.2 11.5 9.5 11.5 8.2 11.5 ns tPLH, tPHL Maximum Propagation Delay; E to Y ns 10.0 12.0 10 10.0 12.0 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0 V 20 CPD Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 - 0.3 Max 0.8 - 0.8 2.0 0.8 Unit V V V V
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MC74VHCT157A
VCC A, B or S 50% tPLH Y 50% VCC tPHL GND A, B or S 50% tPLH Y 50% VCC tPHL VCC GND
Figure 5. Switching Waveform
Figure 6. Inverting Switching
TEST POINT OUTPUT DEVICE UNDER TEST C L*
INPUT
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device MC74VHCT157AD MC74VHCT157ADG MC74VHCT157ADR2 MC74VHCT157ADR2G MC74VHCT157ADT MC74VHCT157ADTG MC74VHCT157ADTR2 M74VHCT157ADTR2G MC74VHCT157AM MC74VHCT157AMG MC74VHCT157AMEL MC74VHCT157AMELG Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHCT157A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT157A
PACKAGE DIMENSIONS
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EEE CCC EEE CCC
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT157A/D

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