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MC74VHCT132A Quad 2-Input NAND Schmitt Trigger The MC74VHCT132A is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC74VHC00, but the inputs have hysteresis and, with its Schmitt trigger function, the VHCT132A can be used as a line receiver which will receive slow input signals. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT132A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features http://onsemi.com MARKING DIAGRAMS 14 SOIC-14 D SUFFIX CASE 751A 1 VHCT132AG AWLYWW 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 VHCT 132A ALYWG G 1 14 SOEIAJ-14 M SUFFIX CASE 965 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) VHCT132 ALYWG * * * * * * * * * * * * High Speed: tPD = 4.9 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates Pb-Free Packages are Available* 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 1 January, 2006 - Rev. 4 Publication Order Number: MC74VHCT132A/D MC74VHCT132A A1 1 3 B1 2 Y1 B3 10 A3 9 8 Y3 A2 4 6 Y2 A4 12 11 Y4 B2 5 B4 13 Figure 1. Logic Diagram VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8 FUNCTION TABLE Inputs A L L H H B L H L H Output Y H H H L 1 A1 2 B1 3 Y1 4 A2 5 B2 6 Y2 7 GND Figure 2. Pinout: 14-Lead Packages (Top View) ORDERING INFORMATION Device MC74VHCT132ADR2 MC74VHCT132ADR2G MC74VHCT132ADTR2 MC74VHCT132ADTRG MC74VHCT132AM MC74VHCT132AMG MC74VHCT132AMEL MC74VHCT132AMELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC74VHCT132A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I II I I I I I I I II I I I I I I III I I I IIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIII I I IIIIIIIIIII II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I IIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIII I III I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIII III IIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I II I I I I I I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIII I I I I IIIIIIIII IIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III I I III I I III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II II III I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II I I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS VCC Vin IIK Vout IOK Iout PD ICC SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage DC Input Voltage Value Unit V V V - 0.5 to + 7.0 - 0.5 to + 7.0 DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW Tstg - 65 to + 150III _C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin TA Vout Parameter Min 4.5 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage DC Output Voltage VCC Operating Temperature, All Package Types - 40 + 85 _C DC ELECTRICAL CHARACTERISTICS Symbol VT+ Parameter Test Conditions VCC V 3.0 4.5 5.5 3.0 4.5 6.0 3.0 4.5 5.5 2.0 3.0 4.5 4.5 5.5 2.0 3.0 4.5 4.5 5.5 TA = 25C Typ TA 85C TA 125C Min Max 1.7 2.0 2.0 Min Max 1.6 2.0 2.0 Min Max 1.6 2.0 2.0 Unit V Positive Threshold Voltage VT- Negative Threshold Voltage 0.35 0.5 0.6 0.30 0.40 0.50 1.9 2.9 4.4 0.35 0.5 0.6 0.30 0.40 0.50 1.9 2.9 4.4 0.35 0.5 0.6 0.30 0.40 0.50 1.9 2.9 4.4 V VH Hysteresis Voltage 1.20 1.40 1.60 1.20 1.40 1.60 1.20 1.40 1.60 V VOH Minimum High-Level Output Voltage IOH = -50mA VIN = VIH or VIL IOH = - 50mA IOH = - 4mA IOH = - 8mA 2.0 3.0 4.5 V 2.58 3.94 2.48 3.80 2.34 3.66 VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50mA IOL = 4mA IOL = 8mA 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 0.36 0.36 0.44 0.44 0.52 0.52 IIN Maximum Input Leakage Current VIN = 5.5V or GND VIN = VCC or GND 0 to 5.5 5.5 5.5 0.0 0.1 2.0 1.0 20 1.0 40 mA mA ICC Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current ICCT Input: VIN = 3.4V VOUT = 5.5V 1.35 0.5 1.50 5.0 1.65 10 mA mA IOPD http://onsemi.com 3 MC74VHCT132A IIII I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I IIII I I I I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIII IIIIIIIIIIIIIIIIIIII I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C Typ TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 Max TA 125C Symbol tPLH, tPHL Parameter Test Conditions Min Max Min Max Unit ns Maximum Propagation Delay, A or B to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF 7.6 10.1 4.9 6.4 4 11.9 15.4 7.7 9.7 10 14.0 17.5 9.0 11.0 10 16.5 20.0 11.0 13.0 10 Cin Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0 V 16 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V) TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 - 0.3 Max 0.8 - 0.8 3.5 1.5 Unit V V V V TEST POINT 3.0V A 1.5V GND tPLH Y 1.5V VOL *Includes all probe and jig capacitance tPHL VOH DEVICE UNDER TEST OUTPUT C L* Figure 3. Switching Waveforms Figure 4. Test Circuit (a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times VH Vin VCC VT+ VT- GND VOH Vout VOL Vout Vin VH (b) A Schmitt-Trigger Offers Maximum Noise Immunity VCC VT+ VT- GND VOH VOL Figure 5. Typical Schmitt-Trigger Applications http://onsemi.com 4 MC74VHCT132A PACKAGE DIMENSIONS SOIC-14 D SUFFIX CASE 751A-03 ISSUE G -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 -B- P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K 0.15 (0.006) T U S J J1 C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 5 CCC EEE CCC EEE CCC A -V- K1 SECTION N-N -W- DIM A B C D F G H J J1 K K1 L M MC74VHCT132A PACKAGE DIMENSIONS SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE A 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 6 MC74VHCT132A/D |
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