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| MC74VHC74 Dual D-Type Flip-Flop with Set and Reset The MC74VHC74 is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features http://onsemi.com MARKING DIAGRAMS 14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 M SUFFIX CASE 965 1 VHC74 ALYWG VHC 74 ALYWG G VHC74G AWLYWW 1 * * * * * * * * * * * * High Speed: fmax = 170MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 2mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 128 FETs or 32 Equivalent Gates Pb-Free Packages are Available* 13 12 11 10 9 8 Q2 Q2 1 1 A = Assembly Location WL, L = Wafer Lot Y, YY = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) RD1 D1 CP1 SD1 1 2 3 4 5 6 Q1 Q1 RD2 D2 CP2 SD2 FUNCTION TABLE Inputs SD L H L H H H H H RD H L L H H H H H CP X X X D X X X H L X X X Outputs Q Q H L L H H* H* H L L H No Change No Change No Change Figure 1. LOGIC DIAGRAM L H *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. March, 2006 - Rev. 5 1 Publication Order Number: MC74VHC74/D MC74VHC74 II I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I II I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I I I II I I II I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS VCC Vin IIK Vout IOK Iout PD SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage DC Input Voltage Value Unit V V V - 0.5 to + 7.0 - 0.5 to + 7.0 DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA Output Diode Current DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin TA Vout tr, tf Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage RD1 D1 CP1 Q1 1 2 3 4 5 6 7 14 13 12 11 10 VCC RD2 D2 CP2 Q2 Q2 SD1 DC Output Voltage VCC 100 20 SD2 Operating Temperature, All Package Types Input Rise and Fall Time - 40 0 0 + 85 _C Q1 9 8 VCC = 3.3V 0.3V VCC =5.0V 0.5V ns/V GND Figure 2. PIN ASSIGNMENT DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL Parameter Test Conditions VCC V TA = 25C Typ TA = - 40 to 85C Min Max Min Max Unit V V V Minimum High-Level Input Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 1.50 VCC x 0.7 1.50 VCC x 0.7 Maximum Low-Level Input Voltage Minimum High-Level Output Voltage 0.50 VCC x 0.3 0.50 VCC x 0.3 VOH Vin = VIH or VIL IOH = - 50mA 1.9 2.9 4.4 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = - 4mA IOH = - 8mA Vin = VIH or VIL IOL = 50mA 2.58 3.94 2.48 3.80 VOL Maximum Low-Level Output Voltage 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH or VIL IOL = 4mA IOL = 8mA Vin = 5.5V or GND Vin = VCC or GND 0.36 0.36 0.44 0.44 Iin Maximum Input Leakage Current 0 to 5.5 5.5 0.1 2.0 1.0 20.0 mA mA ICC Maximum Quiescent Supply Current http://onsemi.com 2 MC74VHC74 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II I I I I I I IIII I I IIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II II I I II II I I I I I I II IIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIII II II I I II I I II IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbol tPLH, tPHL Parameter TA = 25C 6.7 9.2 4.6 6.1 TA = - 40 to 85C 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 70 45 14.0 17.5 Test Conditions Min TypIIII MinIIII Max Max Unit 11.9 15.4 7.3 9.3 ns Maximum Propagation Delay, CP to Q or Q VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 8.5 10.5 tPLH, tPHL Maximum Propagation Delay, SD or RD to Q or Q 7.6 10.1 4.8 6.3 12.3 15.8 7.7 9.7 14.5 18.0 9.0 11.0 ns fmax Maximum Clock Frequency (50% Duty Cycle) 80 50 125 75 170 115 4 MHz 130 90 110 75 Cin Maximum Input Capacitance 10 10 pF Typical @ 25C, VCC = 5.0V 25 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip-flop). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. TIMING REQUIREMENTS (Input tr = tf = 3.0ns) II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIII I II Guaranteed Limit Symbol tw tw Parameter VCC V TA = 25_C 6.0 5.0 6.0 5.0 6.0 5.0 0.5 0.5 5.0 3.0 TA = - 40 to 85_C 7.0 5.0 7.0 5.0 7.0 5.0 0.5 0.5 5.0 3.0 Unit ns ns ns ns ns Minimum Pulse Width, CP 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 Minimum Pulse Width, RD or SD Minimum Setup Time, D to CP Minimum Hold Time, D to CP tsu th trec Minimum Recovery Time, SD or RD to CP ORDERING INFORMATION Device MC74VHC74DR2 MC74VHC74DR2G MC74VHC74DT MC74VHC74DTG MC74VHC74DTR2 MC74VHC74DTR2G MC74VHC74MEL MC74VHC74MELG Package Shipping SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 2000 Tape & Reel 2000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 3 MC74VHC74 tw SD or RD CP VCC 50% tw 1/fmax tPLH Q or Q 50% VCC tPHL Q or Q GND Q or Q 50% tPHL 50% VCC tPLH 50% VCC trec CP 50% VCC GND VCC GND Figure 3. Figure 4. Switching Waveforms TEST POINT VALID D 50% tsu 50% th VCC GND VCC GND *Includes all probe and jig capacitance OUTPUT DEVICE UNDER TEST CL* CP Figure 5. Figure 6. INPUT Figure 7. Input Equivalent Circuit http://onsemi.com 4 MC74VHC74 PACKAGE DIMENSIONS SOIC-14 D SUFFIX CASE 751A-03 ISSUE G -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 -B- P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V N S 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K 0.15 (0.006) T U S J J1 C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 5 EEE CCC EEE CCC EEE CCC A -V- K1 SECTION N-N -W- DIM A B C D F G H J J1 K K1 L M MC74VHC74 PACKAGE DIMENSIONS SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE A 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 6 MC74VHC74/D |
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