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ICL7665S
Data Sheet April 5, 2006 FN3182.8
CMOS Micropower Over/Under Voltage Detector
The ICL7665S Super CMOS Micropower Over/Under Voltage Detector contains two low power, individually programmable Voltage detectors on a single CMOS chip. Requiring typically 3A for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings, settable trip points, or fault monitoring and correction. The trip points and hysteresis of the two voltage detectors are individually programmed via external resistors. An internal bandgap-type reference provides an accurate threshold voltage while operating from any supply in the 1.6V to 16V range. The ICL7665S, Super Programmable Over/Under Voltage Detector is a direct replacement for the industry standard ICL7665B offering wider operating voltage and temperature ranges, improved threshold accuracy (ICL7665SA), and temperature coefficient, and guaranteed maximum supply current. All improvements are highlighted in the electrical characteristics section. All critical parameters are guaranteed over the entire commercial and industrial temperature ranges.
Features
* Guaranteed 10A Maximum Quiescent Current Over Temperature * Guaranteed Wider Operating Voltage Range Over Entire Operating Temperature Range * 2% Threshold Accuracy (ICL7665SA) * Dual Comparator with Precision Internal Reference * 100ppm/C Temperature Coefficient of Threshold Voltage * 100% Tested at 2V * Output Current Sinking Ability . . . . . . . . . . . . Up to 20mA * Individually Programmable Upper and Lower Trip Voltages and Hysteresis Levels * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Pocket Pagers * Portable Instrumentation * Charging Systems * Memory Power Back-Up
Pinout
ICL7665S (SOIC, PDIP) TOP VIEW
1 2 3 4 8 7 6 5
* Battery Operated Systems * Portable Computers * Level Detectors
V+ OUT 2 SET 2 HYST 2
OUT 1 HYST 1 SET 1 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright GE/Intersil 1983-84, GE/RCA 1987, Harris Corp. 1994, Intersil Americas Inc. 1999, 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ICL7665S Ordering Information
PART NUMBER ICL7665SACBA* ICL7665SACBAZ* (Note) ICL7665SACBAZA* (Note) ICL7665SACPA ICL7665SACPAZ (Nore) ICL7665SAIBA* ICL7665SAIBAZA* (Note) ICL7665SAIPA ICL7665SAIPAZ (Note) ICL7665SCBA* ICL7665SCBAZ* (Note) ICL7665SCBAZA* (Note) ICL7665SCPA ICL7665SCPAZ (Note) ICL7665SIBA* ICL7665SIBAZ* (Note) ICL7665SIBAZA* (Note) PART MARKING 7665SACBA 7665SACBAZ 7665SACBAZ 7665SACPA 7665SACPAZ 7665SAIBA 7665SAIBAZ 7665SAIPA 7665SAIPAZ 7665SCBA 7665SCBAZ 7665SCBAZ 7665SCPA 7665SCPAZ 7665SIBA 7665SIBAZ 7665SIBAZ TEMP. RANGE (C) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC (N) 8 Ld SOIC (N) (Pb-free) 8 Ld SOIC (N) (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC (N) 8 Ld SOIC (N) (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC (N) 8 Ld SOIC (N) (Pb-free) 8 Ld SOIC (N) (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC (N) 8 Ld SOIC (N) (Pb-free) 8 Ld SOIC (N) (Pb-free) PKG. DWG. # M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15
*Add "-T" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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ICL7665S
Absolute Maximum Ratings
Supply Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V Output Voltages OUT1 and OUT2 . . . . . . . . . . . . . . . . . -0.3V to 18V (with respect to GND) (Note 2) Output Voltages HYST1 and HYST2 . . . . . . . . . . . . . . -0.3V to +18V (with respect to V+) (Note 2) Input Voltages SET1 and SET2 . . . . . (GND -0.3V) to (V+ V- +0.3V) (Note 2) Maximum Sink Output OUT1 and OUT2 . . . . . . . . . . . . . . . . . 25mA Maximum Source Output Current HYST1 and HYST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . . 150C Maximum Junction Temperature (CERDIP). . . . . . . . . . . . . . . 175C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range ICL7665SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C ICL7665SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+ +0.3V) or less than (GND - 0.3V) may cause destructive device latchup. For these reasons, it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICL7665S be turned on first. If this is not possible, current into inputs and/or outputs must be limited to 0.5mA and voltages must not exceed those defined above.
Electrical Specifications
PARAMETER Operating Supply Voltage
The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = 25C, Test Circuit Figure 7. Unless Otherwise Specified SYMBOL V+ ICL7665S TEST CONDITIONS TA = 25C 0C TA 70C -25C TA 85C ICL7665SA 0C TA 70C -25C TA 85C MIN 1.6 1.8 1.8 1.8 1.8 TYP MAX 16 16 16 16 16 UNITS V V V V V
Supply Current
I+
GND VSET1, VSET2 V+, All Outputs Open Circuit 0C TA 70C V+ = 2V V+ = 9V V+ = 15V -40C TA 85C V+ = 2V V+ = 9V V+ = 15V 1.20 1.20 ICL7665SA 1.275 1.275 ICL7665S ICL7665SA ROUT1, ROUT2, RHYST1, R2HYST2 = 1M, 2V V+ 10V 2.5 2.6 2.9 2.5 2.6 2.9 1.30 1.30 1.30 1.30 200 100 0.03 10 10 10 10 10 10 1.40 1.40 1.325 1.325 A A A A A A V V V V ppm ppm %/V
Input Trip Voltage
VSET1 VSET2 VSET1 VSET2
ICL7665S
Temperature Coefficient of VSET Supply Voltage Sensitivity of VSET1, VSET2
VSET T VSET VS
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ICL7665S
Electrical Specifications
PARAMETER Output Leakage Currents of OUT and HYST The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = 25C, Test Circuit Figure 7. Unless Otherwise Specified (Continued) SYMBOL IOLK IHLK IOLK IHLK Output Saturation Voltages VOUT1 VSET1 = 2V, IOUT1 = 2mA V+ = 2V V+ = 5V V+ = 15V Output Saturation Voltages VHYST1 VSET1 = 2V, IHYST1 = -0.5mA V+ = 2V V+ = 5V V+ = 15V Output Saturation Voltages VOUT2 VSET2 = 0V, IOUT2 = 2mA V+ = 2V V+ = 5V V+ = 15V Output Saturation Voltages VHYST2 VSET2 = 2V V+ = 2V, IHYST2 = -0.2mA V+ = 5V, IHYST2 = -0.5mA V+ = 15V, IHYST2 = -0.5mA VSET Input Leakage Current Input for Complete Output Change ISET VSET GND VSET V+ ROUT = 4.7k, RHYST = 20k, VOUTLO = 1% V+, VOUTHI = 99% V+ ROUT, RHYST = 1mW ROUT, RHYST = 1mW ICL7665S ICL7665SA ICL7665S ICL7665SA V+ = 15V TEST CONDITIONS VSET = 0V or VSET 2V MIN TYP 10 -10 0.2 0.1 0.06 -0.15 -0.05 -0.02 0.2 0.15 0.11 -0.25 -0.43 -0.35 0.01 1.0 0.1 MAX 200 -100 2000 -500 0.5 0.3 0.2 -0.30 -0.15 -0.10 0.5 0.3 0.25 -0.8 -1.0 -0.8 10 UNITS nA nA nA nA V V V V V V V V V V V V nA mV mV
Difference in Trip Voltages Output/Hysteresis Difference NOTES:
VSET1 VSET2
-
5 1 0.1
50 -
mV mV mV
3. Derate above 25C ambient temperature at 4mW/C. 4. All significant improvements over the industry standard ICL7665 are highlighted.
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AC Electrical Specifications
PARAMETER OUTPUT DELAY TIMES Input Going HI t SO1D t SH1D t SO2D t SH2D Input Going LO t SO1D t SH1D t SO2D t SH2D Output Rise Times t O1R t O2R t H1R t H2R Output Fall Times t O1F t O2F t H1F t H2F VSET Switched between 1.0V to 1.6V ROUT = 4.7k, CL = 12pF RHYST = 20k, CL = 12pF VSET Switched between 1.0V to 1.6V ROUT = 4.7k, CL = 12pF RHYST = 20k, CL = 12pF VSET Switched between 1.6V to 1.0V ROUT = 4.7k, CL = 12pF RHYST = 20k, CL = 12pF VSET Switched between 1.0V to 1.6V ROUT = 4.7k, CL = 12pF RHYST = 20k, CL = 12pF 85 90 55 55 75 80 60 60 0.6 0.8 7.5 0.7 0.6 0.7 4.0 1.8 s s s s s s s s s s s s s s s s SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Functional Block Diagram
V+ SET1 + REF + OUT2 OUT1 GND HYST2 HYST1
SET2
CONDITIONS (Note 5) VSET1 > 1.3V, OUT1 Switch ON, HYST1 Switch ON VSET1 < 1.3V, OUT1 Switch OFF, HYST1 Switch OFF VSET2 > 1.3V, OUT2 Switch OFF, HYST2 Switch ON VSET2 < 1.3V, OUT2 Switch ON, HYST2 Switch OFF NOTE: 5. See Electrical Specifications for exact thresholds.
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ICL7665S Typical Performance Curves
2.0 V+ = 2V VOLTAGE SATURATION (V) 1.5 V+ = 5V 1.0 VOLTAGE SATURATION (V) 1.5 2.0 V+ = 2V
V+ = 9V
1.0 V+ = 5V V+ = 9V 0.5 V+ = 15V
0.5 V+ = 15V
0 0 5 10 IOUTOUT1 (mA) 15 20
0 0 5 10 IOUTOUT2 (mA) 15 20
FIGURE 1. OUT1 SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT
FIGURE 2. OUT2 SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT
-20
-16 TA = 25C V+ = 15V
-12
-8
-4
0
HYST1 OUTPUT SATURATION VOLTAGE (V)
TA = 25C -1.0 V+ = 15V -2.0 V+ = 9V -3.0
-0.4
-0.8
V+ = 9V
-1.2
-1.6 V+ = 5V V+ = 2V
-4.0 V+ = 5V V+ = 2V -5.0
-2.0
HYST1 OUTPUT CURRENT (mA)
HYST2 OUTPUT CURRENT (mA)
FIGURE 3. HYST1 OUTPUT SATURATION VOLTAGE vs HYST1 OUTPUT CURRENT
5.0 4.5 SUPPLY CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -25 0 +20 +40 +60 V+ = 2V V+ = 15V V+ = 9V 0V VSET1, VSET2 V+
FIGURE 4. HYST2 OUTPUT SATURATION VOLTAGE vs HYST2 OUTPUT CURRENT
5.0 4.5 SUPPLY CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 TA = 70C TA = 25C 0V VSET1, VSET2 V+ TA = -20C
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V+)
FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE
FIGURE 6. SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE
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HYST2 OUTPUT SATURATION VOLTAGE (V)
0
-5.0
-4.0
-3.0
-2.0
-1.0
0
0
ICL7665S Detailed Description
As shown in the Functional Diagram, the ICL7665S consists of two comparators which compare input voltages on the SET1 and SET2 terminals to an internal 1.3V bandgap reference. The outputs from the two comparators drive open-drain N-channel transistors for OUT1 and OUT2, and open-drain P-channel transistors for HYST1 and HYST2 outputs. Each section, the Undervoltage Detector and the Overvoltage Detector, is independent of the other, although both use the internal 1.3V reference. The offset voltages of the two comparators will normally be unequal so VSET1 will generally not quite equal VSET2. The input impedance of the SET1 and SET2 pins are extremely high, and for most practical applications can be ignored. The four outputs are open-drain MOS transistors, and when ON behave as low resistance switches to their respective supply rails. This minimizes errors in setting up the hysteresis, and maximizes the output flexibility. The operating currents of the bandgap reference and the comparators are around 100nA each.
V+ 4.7k
can be used to reduce the rate-of-rise of the supply voltage in battery applications. In line operated systems, the rate-ofrise of the supply is limited by other considerations, and is normally not a problem. If the SET voltages must be applied before the supply voltage V+, the input current should be limited to less than 0.5mA by appropriate external resistors, usually required for voltage setting anyway. A similar precaution should be taken with the outputs if it is likely that they will be driven by other circuits to levels outside the supplies at any time.
VSET1, VSET2 t SO1D t O1F t O1R t SO1D V+ (5V) GND t H1F t SH1D t SO2D t O2R OUT2 V+ (5V) GND V+ (5V) GND V+ (5V) GND 1.6V 1.0V
INPUT
OUT1
t SH1D t H1R HYST1 t SO2D t O2F
OUT1 HYST1 HYST2
t SH2D t H2R
t SH2D t H2F
1 OUT1 INPUT
V+ 8
4.7 k OUT2
FIGURE 8. SWITCHING WAVEFORMS
2 HYST1OUT2 7 3 SET1 SET2 6 HYST2 4 GND HYST2 5
Simple Threshold Detector
Figure 9 shows the simplest connection of the ICL7665S for threshold detection. From the graph 9B, it can be seen that at low input voltage OUT1 is OFF, or high, while OUT2 is ON, or low. As the input rises (e.g., at power-on) toward VNOM (usually the eventual operating voltage), OUT2 goes high on reaching VTR2. If the voltage rises above VNOM as much as VTR1, OUT1 goes low. The equation giving VSET1 and VSET2 are from Figure 9A:
R 11 V SET1 = V IN ------------------------------( R 11 + R 21 ) R 12 V SET2 = V IN ------------------------------( R 12 + R 22 )
20 k
20 k
12 pF
12 pF
12 pF
12 pF
1.6V 1.0V
FIGURE 7. TEST CIRCUITS
Precautions
Junction isolated CMOS devices like the ICL7665S have an inherent SCR or 4-layer PNPN structure distributed throughout the die. Under certain circumstances, this can be triggered into a potentially destructive high current mode. This latchup can be triggered by forward-biasing an input or output with respect to the power supply, or by applying excessive supply voltages. In very low current analog circuits, such as the ICL7665S, this SCR can also be triggered by applying the input power supply extremely rapidly ("instantaneously"), e.g., through a low impedance battery and an ON/OFF switch with short lead lengths. The rate-of-rise of the supply voltage can exceed 100V/s in such a circuit. A low impedance capacitor (e.g., 0.05F disc ceramic) between the V+ and GND pins of the ICL7665S
Since the voltage to trip each comparator is nominally 1.3V, the value VIN for each trip point can be found from
( R 11 + R 21 ) ( R 11 + R 21 ) V TR1 = V SET1 --------------------------------- = 1.3 --------------------------------- for detector 1 R R
11 11
and
( R 12 + R 22 ) ( R 12 + R 22 ) V TR2 = V SET2 --------------------------------- = 1.3 --------------------------------- for detector 2 R R
12 12
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ICL7665S
VIN VOUT OFF RP2 R21 OUT1 SET1 R11 V+ OUT2 SET2 R12 ON VTR2 DETECTOR 2 VNOM VTR1 DETECTOR 1 RP1 R22
FIGURE 9A. CIRCUIT CONFIGURATION
FIGURE 9B. TRANSFER CHARACTERISTICS
FIGURE 9. SIMPLE THRESHOLD DETECTOR
VIN
OUT ON
R31 HYST1 R21 SET1 OUT1 OVERVOLTAGE R11
V+ HYST2
R32
R22 SET2 OUT2 OVERVOLTAGE R12 DETECTOR 2 OFF VL2 VU2 VNOM DETECTOR 1 VL1 VU1 VIN
FIGURE 10A. CIRCUIT CONFIGURATION
FIGURE 10B. TRANSFER CHARACTERISTICS
FIGURE 10. THRESHOLD DETECTOR WITH HYSTERESIS
Either detector may be used alone, as well as both together, in any of the circuits shown here. When VIN is very close to one of the trip voltage, normal variations and noise may cause it to wander back and forth across this level, leading to erratic output ON and OFF conditions. The addition of hysteresis, making the trip points slightly different for rising and falling inputs, will avoid this condition.
becomes controlled by only R1N and R2N, a lower value. The input will then have to fall to this new point to restore the initial comparator state, but as soon as this occurs, the trip point will be raised again. An alternative circuit for obtaining hysteresis is shown in Figure 11. In this configuration, the HYST pins put the extra resistor in parallel with the upper setting resistor. The values of the resistors differ, but the action is essentially the same. The governing equations are given in Table 1. These ignore the effects of the resistance of the HYST outputs, but these can normally be neglected if the resistor values are above about 100k.
( R 12 + R 22 ) ( R 12 + R 22 ) V TR2 = V SET2 --------------------------------- = 1.3 --------------------------------- for detector 2 R R
12 12
Threshold Detector with Hysteresis
Figure 10A shows how to set up such hysteresis, while Figure 10B shows how the hysteresis around each trip point produces switching action at different points depending on whether VIN is rising or falling (the arrows indicated direction of change. The HYST outputs are basically switches which short out R31 or R32 when VIN is above the respective trip point. Thus if the input voltage rises from a low value, the trip point will be controlled by R1N, R2N, and R3N, until the trip point is reached. As this value is passed, the detector changes state, R3N is shorted out, and the trip point 8
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ICL7665S
VIN
Applications
Single Supply Fault Monitor
RP OUT2 R32 HYST2 SET2 R12 +5V SUPPLY R22
RP R21 R31 HYST1 SET1 R11 OUT1
V+
Figure 12 shows an over/under voltage fault monitor for a single supply. The overvoltage trip point is centered around 5.5V and the undervoltage trip point is centered around 4.5V. Both have some hysteresis to prevent erratic output ON and OFF conditions. The two outputs are connected in a wired OR configuration with a pullup resistor to generate a power OK signal.
FIGURE 11. AN ALTERNATIVE HYSTERESIS CIRCUIT
R21
324k HYST1 13M 5% R31 VSET1 R11
V+ HYST2 R32 VSET2 R12
249k 7.5M 5%
R22
TABLE 1. SET-POINT EQUATIONS NO HYSTERESIS Overvoltage VTRIP = Overvoltage VTRIP = R11 + R21 R11 R12 + R22 R12 x VSET1 x VSET2
100k
100k OPEN VOLTAGE DETECTOR VU = 4.55V VL = 4.45V POWER OK
OUT1 OPEN VOLTAGE DETECTOR VU = 5.55V VL = 5.45V
OUT2 V+ 1M
HYSTERESIS PER FIGURE 10A VU1 = R11 + R21 + R31 R11 R11 + R21 R11 R12 x VSET1
Overvoltage VTRIP VL1 = VU2 = x VSET1 x VSET2
FIGURE 12. FAULT MONITOR FOR A SINGLE SUPPLY
Multiple Supply Fault Monitor
The ICL7665S can simultaneously monitor several supplies when connected as shown in Figure 13. The resistors are chosen such that the sum of the currents through R21A, R21B, and R31 is equal to the current through R11 when the two input voltage are at the desired low voltage detection point. The current through R11 at this point is equal to 1.3V/R11. The voltage at the VSET input depends on the voltage of both supplies being monitored. The trip voltage of one supply while the other supply is at the nominal voltage will be different that the trip voltage when both supplies are below their nominal voltages. The other side of the ICL7665S can be used to detect the absence of negative supplies. The trip points for OUT1 depend on both the negative supply voltages and the actual voltage of the +5V supply.
R12 + R22 + R32
Undervoltage VTRIP VL2 = R12 + R22 R12 R11 + R21 R11 x VSET2
HYSTERESIS PER FIGURE 11 VU1 = x VSET1
Overvoltage VTRIP R11 + R21R31 R21 + R31 x VSET1 R11 VU2 = R12 + R22 R12 x VSET2
VL1 =
Overvoltage VTRIP VL2 = R12 + R22R32 R22 + R32 x VSET2 R12
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+5V V+ HYST1 22M R21 VSET1 +15V 1.02M R21B 49.9k R11 OUT1 VSET2 OUT2 301 k 787 k +5V HYST2 22 M 100k
274k R21A +5V
VSET1 is greater than 1.3V, OUT1 is low, but when VSET1 drops below 1.3V, OUT1 goes high shutting off the ICL7663S. OUT2 is used for low battery warning. When VSET2 is greater than 1.3V, OUT2 is high and the low battery warning is on. When VSET2 drops below 1.3V, OUT2 is low and the low battery warning goes off. The trip voltage for low battery warning can be set higher than the trip voltage for shutdown to give advance low battery warning before the battery is disconnected.
1M
-5V
-15V
Power Fail Warning and Powerup/Powerdown Reset
Figure 15 shows a power fail warning circuit with powerup/powerdown reset. When the unregulated DC input is above the trip point, OUT1 is low. When the DC input drops below the trip point, OUT1 shuts OFF and the power fail warning goes high. The voltage on the input of the 7805 will continue to provide 5V out at 1A until VIN is less than 7.3V, this circuit will provide a certain amount of warning before the 5V output begins to drop. The ICL7665S OUT2 is used to prevent a microprocessor from writing spurious data to a CMOS battery backup memory by causing OUT2 to go low when the 7805 5V output drops below the ICL7665S trip point.
POWER OK
FIGURE 13. MULTIPLE SUPPLY FAULT MONITOR
Combination Low Battery Warning and Low Battery Disconnect
When using rechargeable batteries in a system, it is important to keep the batteries from being over discharged. The circuit shown in Figure 14 provides a low battery warning and also disconnects the low battery from the rest of the system to prevent damage to the battery. OUT1 is used to shutdown the ICL7663S when the battery voltage drops to the value where the load should be disconnected. As long as
R31 V+ HYST1 + R21 SET1 R11 ICL7665S SET2 HYST2
R32 1M V+ R22 V+ R12 1M OUT1 ICL7663S SHUTDOWN GND
100
+5V 1A
OUT2 SENSE VSET
OUT1
GND
OUT2
LOW BATTERY SHUTDOWN
LOW BATTERY WARNING
FIGURE 14. LOW BATTERY WARNING AND LOW BATTERY DISCONNECT
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UNREGULATED DC INPUT 7805 5V REGULATOR
4700F
470F BACKUP BATTERY
V+ HYST1 5.86k VSET1 130k OUT1 HYST2 22M VSET2 2.2M OUT2 1M 1M RESET OR WRITE ENABLE POWER FAIL WARNING
ICL7665S
715k
1M
FIGURE 15. POWER FAIL WARNING AND POWERUP/POWERDOWN RESET
Simple High/Low Temperature Alarm
Figure 16 illustrates a simple high/low temperature alarm which uses the ICL7665S with an NPN transistor. The voltage at the top of R1 is determined by the VBE of the transistor and the position of R1's wiper arm. This voltage has a negative temperature coefficient. R1 is adjusted so that VSET2 equals 1.3V when the NPN transistor's temperature reaches the temperature selected for the high temperature alarm. When this occurs, OUT2 goes low. R2 is adjusted so that VSET1 equals 1.3V when the NPN transistor's temperature reaches the temperature selected for the low temperature alarm. When the temperature drops below this limit, OUT1 goes low.
AC Power Fail and Brownout Detector
Figure 17 shows a circuit that detects AC undervoltage by monitoring the secondary side of the transformer. The capacitor, C1, is charged through R1 when OUT1 is OFF. With a normal 100 VAC input to the transformer, OUT1 will discharge C1 once every cycle, approximately every 16.7ms. When the AC input voltage is reduced, OUT1 will stay OFF, so that C1 does not discharge. When the voltage on C1 reaches 1.3V, OUT2 turns OFF and the power fail warning goes high. The time constant, R1C1, is chosen such that it takes longer than 16.7ms to charge C1 1.3V.
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+ 5V -
TEMPERATURE SENSOR (GENERAL PURPOSE NPN TRANSISTOR)
470k R3 HYST1 27k R5 OUT1 22k R4 VSET1
V+ HYST2 R6 VSET2 22M
LOW TEMPERATURE LIMIT ADJUST
ICL7665S
R2 1M
OUT2 V+
R7
1.5M
R1
10k HIGH TEMPERATURE LIMIT ADJUST
1M
ALARM SIGNAL FOR DRIVING LEDS, BELLS, ETC.
FIGURE 16. SIMPLE HIGH/LOW TEMPERATURE ALARM
7805 5V REGULATOR 20V CENTERED TAPPED TRANS. 4700F 5V, 1A
110VAC 60Hz
+5V 601k HYST1 HYST2 R1 1M VSET2 POWER FAIL WARNING
ICL7665S VSET1 100k
1M
OUT1
OUT2
1M
C1
FIGURE 17. AC POWER FAIL AND BROWNOUT DETECTOR
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ICL7665S Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
13
FN3182.8 April 5, 2006
ICL7665S Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN3182.8 April 5, 2006

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