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| STF8NK100Z STP8NK100Z N-CHANNEL 1000V - 1.60 - 6.5A - TO-220 - TO-220FP Zener-Protected SuperMESHTM MOSFET General features Type VDSS RDS(on) ID Pw STF8NK100Z 1000 V <1.85 6.5 ANote 1 40 W STP8NK100Z 1000 V <1.85 6.5 A 160 W EXTREMELY HIGH dv/dt CAPABILITY 3 3 1 2 100% AVALANCHE RATED IMPROVED ESD CAPABILITY VERY LOW INTRINSIC CAPACITANCE TO-220 1 2 TO-220FP Description The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products. Internal schematic diagram Applications HIGH CURRENT,SWITCHING APPLICATION IDEAL FOR OFF-LINE POWER SUPPLIES Order codes Sales Type STF8NK100Z STP8NK100Z Marking F8NK100Z P8NK100Z Package TO-220FP TO-220 Packaging TUBE TUBE November 2005 Rev 1 1/13 www.st.com 13 1 Electrical ratings STF8NK100Z - STP8NK100Z 1 Table 1. Electrical ratings Absolute maximum ratings Parameter TO-220 VDS VDGR VGS ID Note 1 ID Drain-source Voltage (VGS=0) Drain-gate Voltage Gate-Source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor VESD(G-S) Gate source ESD (HBM-C=100pF, R=1.5K) 6.5 4.3 16 160 1.28 4000 4.5 --55 to 150 2500 1000 1000 30 6.5 4.3 16 40 0.32 Value TO-220FP V V V A A A W W/C V V/ns V C Unit Symbol IDM Note 2 PTOT dv/dt Note 3 Peak Diode Recovery voltage slope VISO Tj Tstg Insulation Withstand Voltage (DC) Operating Junction Temperature Storage Temperature Table 2. Thermal data TO-220 TO-220FP 3.1 62.5 300 C/W C/W C Rthj-case Rthj-a Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.78 Table 3. Symbol IAR EAS Avalanche Characteristics Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj= 25C, ID=IAR, V DD=50V) Value 6.5 320 Unit A mJ 2/13 STF8NK100Z - STP8NK100Z 2 Electrical characteristics 2 Electrical characteristics (TCASE = 25 C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS On/off states Parameter Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate Body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-Source On Resistance Test Conditions ID = 1mA, V GS= 0 VDS = Max Rating, VDS = Max Rating,Tc = 125C VGS = 20V VDS= VGS, ID = 100 A VGS= 10 V, ID= 3.15 A 3 3.75 1.60 Min. 1000 1 50 10 Typ. Max. Unit V A A A V IGSS VGS(th) RDS(on) 4.5 1.85 Table 5. Symbol gfs Note 6 Ciss Coss Crss Coss eq. Note 5 Qg Qgs Qgd Dynamic Parameter Forward Transconductance Test Conditions VDS =15V, ID=3.15 A Min. Typ. 7 2180 174 36 83 73 12 40 102 Max. Unit S pF pF pF pF nC nC nC Input Capacitance VDS =25V, f=1 MHz, V GS=0 Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge VGS=0V, VDS=0 to 800V VDD=800V, ID = 6.3A VGS =10V (see Figure 17) 3/13 2 Electrical characteristics STF8NK100Z - STP8NK100Z Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on Delay Time Rise Time Test Conditions VDD=500 V, ID= 3.15 A, RG=4.7, VGS=10V (see Figure 18) VDD=500 V, ID=3.15 A, RG=4.7, VGS=10V (see Figure 18) Min. Typ. 28 19 Max. Unit ns ns Turn-off Delay Time FallTime 59 30 ns ns Table 7. Symbol ISD ISDM Note 3 VSDNote 2 trr Qrr IRRM trr Qrr IRRM Source drain diode Parameter Source-drain Current Source-drain Current (pulsed) Forward on Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD=6.3A, VGS=0 ISD=6.3A, di/dt = 100A/s, VDD=50 V, Tj=25C 620 5.3 17 840 7.5 18 Test Conditions Min. Typ. Max. 6.5 26 1.6 Unit A A V ns C A ns C A ISD=6.3A, di/dt = 100A/s, VDD=50 V, Tj=150C Table 8. Symbol BVGSO Note 4 Gate-source zener diode Parameter Gate-Source Breakdown Voltage Test Conditions Igs = 1mA (Open Drain) Min. 30 Typ. Max. Unit V (1) Limited only by maximum temperature allowed (2)ISD 6.5 A, di/dt 200A/s, VDS V(BR)DSS, Tj Tjmax (3) Pulse width limited by safe operating area (4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device's ESD capability, but also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. (5) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (6) Pulsed: pulse duartion = 300s, duty cycle 1.5% 4/13 STF8NK100Z - STP8NK100Z 2 Electrical characteristics 2.1 Electrical characteristics (curves) Safe Operating Area for TO-220 Figure 2. Thermal Impedance for TO-220 Figure 1. Figure 3. Safe Operating Area for TO-220FP Figure 4. Thermal Impedance for TO-220FP Figure 5. Output Characteristics Figure 6. Transfer Characteristics 5/13 2 Electrical characteristics STF8NK100Z - STP8NK100Z Figure 7. Transconductance Figure 8. Static Drain-source on Resistance Figure 9. Gate Charge vs Gate-source Volatge Figure 10. Capacitance Variations Figure 11. Normalized Gate Threshold Voltage Figure 12. Normalized On Resistance vs. vs. Temperature Temperature 6/13 STF8NK100Z - STP8NK100Z 2 Electrical characteristics Figure 13. Source-drain Diode Forward Characteristics Figure 14. Normalized BVDSS vs Temperature Figure 15. Maximum Avalanche Energy vs Temperature 7/13 3 Test circuits STF8NK100Z - STP8NK100Z 3 Test circuits Figure 17. Gate Charge Test Circuit Figure 16. Switching Times Test Circuit For Resistive Load Figure 18. Test Circuit For Indictive Load Switching and Diode Recovery Times Figure 20. Unclamped Inductive Load Test Circuit Figure 19. Unclamped Inductive Waveform 8/13 STF8NK100Z - STP8NK100Z 4 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13 4 Package mechanical data STF8NK100Z - STP8NK100Z TO-220FP MECHANICAL DATA mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7 O A B L3 L6 L7 F1 F D G1 H F2 L2 L5 E 123 L4 10/13 G STF8NK100Z - STP8NK100Z 4 Package mechanical data TO-220 MECHANICAL DATA DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154 oP Q 11/13 5 Revision History STF8NK100Z - STP8NK100Z 5 Revision History Date 04-Nov-2005 Revision 1 First release Changes 12/13 STF8NK100Z - STP8NK100Z 5 Revision History Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13 |
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