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19-3871; Rev 0; 10/05
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
General Description
The MAX5550 dual, 10-bit, digital-to-analog converter (DAC) features high-output-current capability. The MAX5550 sources up to 30mA per DAC, making it ideal for PIN diode biasing applications. Outputs can also be paralleled for high-current applications (up to 60mA typ). Operating from a single +2.7V to +5.25V supply, the MAX5550 typically consumes 1.5mA per DAC in normal operation and less than 1A (max) in shutdown mode. The MAX5550 also features low output leakage current in shutdown mode (1A max) that is essential to ensure that the external PIN diodes are off. Additional features include an integrated +1.25V bandgap reference, and a control amplifier to ensure high accuracy and low-noise performance. A separate reference input (REFIN) allows for the use of an external reference source, such as the MAX6126, for improved gain accuracy. A pin-selectable I2C*-/SPITM-compatible serial interface provides optimum flexibility for the MAX5550. The maximum programmable output current value is set using software and an adjustment resistor. The MAX5550 is available in a (3mm x 3mm) 16-pin thin QFN package, and is specified over the extended (-40C to +85C) temperature range. Pin-Selectable I2C-
Features
or SPI-Compatible Interface Guaranteed Low Output Leakage Current in Shutdown (1A max) Guaranteed Monotonic over Extended Temperature Range Dual Outputs for Balanced Systems Current Outputs Source Up to 30mA per DAC Parallelable Outputs for 60mA Applications Output Stable with RF Filters Internal or External Reference Capability Digital Output (DOUT) Available for Daisy Chaining in SPI Mode +2.7V to +5.25V Single-Supply Operation 16-Pin (3mm x 3mm) Thin QFN Package Programmable Output Current Range Set by Software and Adjustment Resistor
MAX5550
Ordering Information
PART MAX5550ETE TEMP RANGE -40C to +85C PINPACKAGE PKG CODE TOP MARK ACZ
Applications
PIN Diode Biasing RF Attenuator Control VCO Tuning
16 Thin QFN T1633F-3
Functional Diagram
REFIN VDD
+1.25V REF
BUFFER
P 10-BIT CURRENT-STEERING DAC A OUTA
FSADJA VDD
MAX5550
*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SPI is a trademark of Motorola, Inc.
SPI/I2C DAC REGISTER A DAC REGISTER B
P 10-BIT CURRENT-STEERING DAC B OUTB FSADJB
16-BIT INPUT REGISTER
Pin Configuration appears at end of data sheet.
SCLK/SCL DIN/SDA
CS/A0
DOUT/A1
GND
________________________________________________________________ Maxim Integrated Products
1
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V OUTA, OUTB to GND .................................-0.3V to (VDD + 0.3V) REFIN, CS/AO, DOUT/AI, SPI/I2C, FSADJA, FSADJB to GND ......................................-0.3V to (VDD + 0.3V) SCLK/SCL, DIN/SDA ................................................-0.3V to +6V Continuous Power Dissipation (TA = +85C) 16-Pin Thin QFN (derate 17.5mW/C above +70C) ..1398.6mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity Offset Zero-Scale Error Full-Scale Error REFERENCE Internal Reference Range Internal Reference Tempco External Reference Range External Reference Input Current DAC OUTPUTS Full-Scale Current Output Current Leakage in Shutdown Output Capacitance Current Source Dropout Voltage (VDD - VOUT_) Output Impedance at Full-Scale Current Capacitive Load to Ground Series Inductive Load Maximum FSADJ_ Capacitive Load DYNAMIC PERFORMANCE Settling Time Digital Feedthrough tS CLOAD = 24pF, LLOAD = 27nH (Note 4) 30 2 s nVs CLOAD LLOAD CFSADJ_ IOUT_ = 30mA IOUT_ = 20mA TA = +25C TA = -40C to +85C 1 0.55 0.6 100 10 100 75 k nF nH pF V 10 (Note 3) 1 30 1 mA A pF 0.5 108 1.21 1.25 30 1.5 225 1.29 V ppm/C V A INL DNL IOS IOUT_ = 1mA to 30mA, code = 0x000 IOUT_ = 1mA to 30mA, code = 0x3FF, includes offset -16 IOUT_ = 1mA to 30mA (Note 2) Guaranteed monotonic -50 -16 1 SYMBOL CONDITIONS MIN 10 2 1 TYP MAX UNITS Bits LSB LSB LSB A LSB
STATIC PERFORMANCE--ANALOG SECTION
2
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER Digital-to-Analog Glitch Impulse DAC-to-DAC Current Matching Wake-Up Time POWER SUPPLIES Supply Voltage Supply Current Shutdown Current LOGIC AND CONTROL INPUTS Input High Voltage (Note 5) Input Low Voltage Input Hysteresis Input Capacitance Input Leakage Current Output Low Voltage Output High Voltage VIH VIL VHYS CIN IIN VOL VOH ISINK = 3mA ISOURCE = 2mA VDD 0.5 400 600 600 130 600 100 0 20 + 0.1 x CB 20 + 0.1 x CB 20 + 0.1 x CB 20 + 0.1 x CB 70 300 300 300 300 +2.7V VDD +3.4V +3.4V < VDD +5.25V (Note 5) 0.1 x VDD 10 1 0.6 0.7 x VDD 2.4 0.8 V V pF A V V V VDD IDD VDD = +5.25V, no load +2.70 3 +5.25 6 1.2 V mA A VDD = +3V VDD = +5V SYMBOL CONDITIONS MIN TYP 40 2 400 10 MAX UNITS nVs % s
MAX5550
I2C TIMING CHARACTERISTICS (Figure 2) SCL Clock Frequency Setup Time for START Condition Hold Time for START Condition SCL Pulse-Width Low SCL Pulse-Width High Data Setup Time Data Hold Time SCL Rise Time SCL Fall Time SDA Rise Time SDA Fall Time fSCL tSU:STA tHD:STA tLOW tHIGH tSU:DAT tHD:DAT tRCL tFCL tRDA tFDA kHz ns ns ns ns ns ns ns ns ns ns
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k; compliance voltage = (VDD - 0.6V), VSCLK/SCL = 0, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25C.) (Note 1)
PARAMETER Bus Free Time Between a STOP and START Condition Setup Time for STOP Condition Maximum Capacitive Load for Each Bus Line SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Fall to DOUT Transition CS Fall to DOUT Enable CS Rise to DOUT Disable SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Fall to DOUT Transition CS Fall to DOUT Enable CS Rise to DOUT Disable SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High SYMBOL tBUF tSU:STO CB CONDITIONS MIN 1.3 160 400 TYP MAX UNITS s ns pF
SPI TIMING CHARACTERISTICS (Figure 6) tCP tCH tCL tCSS tCSH tDS tDH tDO1 tCSE tCSD tCS0 tCS1 tCSW tCP tCH tCL tCSS tCSH tDS tDH tDO1 tCSE tCSD tCS0 tCS1 tCSW CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF 50 40 100 CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF 50 40 100 200 80 80 25 50 40 0 40 40 40 100 40 40 25 50 40 0 40 40 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
Note 1: Note 2: Note 3: Note 4: Note 5:
100% production tested at TA = +25C. Limits over temperature are guaranteed by design. INL linearity is guaranteed from code 60 to code 1024. Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section. Settling time is measured from (0.25 x full scale) to (0.75 x full scale). The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
Typical Operating Characteristics
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted).
INL vs. CODE
MAX5550 toc01
MAX5550
DNL vs. CODE
MAX5550 toc02
INL vs. TEMPERATURE
3.5 3.0 INL (LSB) 2.5 2.0 1.5 1.0 0.5 0
MAX5550 toc03
2.0 1.5 1.0
1.00 0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
4.0
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 0 128 256 384 512 640 768 896 1024 CODE
0
128 256 384 512 640 768 896 1024 CODE
-40
-15
10 35 TEMPERATURE (C)
60
85
DNL vs. TEMPERATURE
MAX5550 toc04
MAXIMUM INL ERROR vs. OUTPUT CURRENT RANGES
MAX5550 toc05
ZERO-SCALE OUTPUT CURRENT vs. TEMPERATURE
4.0 ZERO-SCALE CURRENT (nA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VDD = 3V VDD = 5V
MAX5550 toc06
0.40 0.35 0.30 DNL (LSB)
3.0 2.5 2.0 INL (LSB) 1.5 1.0 0.5 0
4.5
0.25 0.20 0.15 0.10 0.05 0 -40 -15 10 35 TEMPERATURE (C) 60 85
0 1-2 2-5 8-16 15-30 1.5-3 4.5-9 OUTPUT CURRENT RANGE (mA) -40 -15 10 35 60 85 TEMPERATURE (C)
FULL-SCALE CURRENT vs. TEMPERATURE
29.86 FULL-SCALE CURRENT (mA) 29.84 29.82 29.80 29.78 29.76 29.74 29.72 -40 -15 10 35 TEMPERATURE (C) 60 85 VDD = 3V VDD = 5V
MAX5550 toc07
SETTLING TIME (FULL-SCALE POSITIVE STEP)
MAX5550 toc08
SETTLING TIME (FULL-SCALE NEGATIVE STEP)
MAX5550 toc09
29.88
CS 2V/div RLOAD = 65 CLOAD = 24pF
CS 2V/div
RLOAD = 65 CLOAD = 24pF 10s/div
VOUT_ 1V/div
VOUT_ 1V/div
10s/div
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
Typical Operating Characteristics (continued)
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted).
GLITCH IMPULSE
MAX5548 toc10
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
NO LOAD, CODE = 0x00 SHUTDOWN CURRENT (nA)
MAX5550 toc11
620
CS 1V/div
520
420
VOUT_ AC-COUPLED 10mV/div RLOAD = 65 CLOAD = 24pF
320
220 40ns/div 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5550 toc12
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
NO LOAD, CODE = 0x00 INTERNAL REFERENCE VOLTAGE (V)
MAX5550 toc13
620 NO LOAD, CODE = 0x00 SHUTDOWN CURRENT (nA)
1.25100
520 VDD = 5V 420 VDD = 3V 320
1.25075
1.25050
1.25025
220 -40 -15 10 35 60 85 TEMPERATURE (C)
1.25000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
NO LOAD, CODE = 0x00 INTERNAL REFERENCE VOLTAGE (V) 1.251 1.250 1.249 1.248 1.247 1.246 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX5550 toc14
1.252
6
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
Typical Operating Characteristics (continued)
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k, TA = +25C. unless otherwise noted).
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5550 toc15
MAX5550
SUPPLY CURRENT vs. TEMPERATURE
NO LOAD, CODE = 0x00 2.755 SUPPLY CURRENT (mA) VDD = 5V 2.750 2.745 2.740 2.735 2.730 VDD = 3V
MAX5550 toc16
2.80 NO LOAD, CODE = 0x00
2.760
SUPPLY CURRENT (mA)
2.75 INTERNAL REFERENCE 2.70
2.65 EXTERNAL REFERENCE 2.60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (C)
WAKE-UP TIME
MAX5550 toc17
IOUT vs. VOUT
30
CS 2V/div
MAX5550 toc18
35
25 IOUT (mA) 20 VDD = 3V 15 10 VDD = 5V
VOUT_ 1V/div RLOAD = 65 CLOAD = 24pF 400s/div
5 0 0 1 2 3 VOUT (V) 4 5
SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
NO LOAD, CODE = 0x00 SUPPLY CURRENT (mA)
MAX5550 toc19
DIGITAL FEEDTHROUGH
MAX5550 toc20
10
VDD = 5V
SCLK 2V/div
VDD = 3V
VOUT_ AC-COUPLED 10mV/div RLOAD = 65 CLOAD = 24pF
1 0 1 2 3 4 DIGITAL INPUT VOLTAGE (V) 5
400s/div
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
Pin Description
PIN 1 2 3 4 NAME SCLK/SC DIN/SDA CS/A0 SPI/I2C FUNCTION Serial Clock Input. Connect SCL to VDD through a 2.4k resistor in I2C mode. Serial Data Input. Connect SDA to VDD through a 2.4k resistor in I2C mode. Chip-Select Input in SPI Mode/Address Select 0 in I2C Mode. CS is an active-low input. Connect A0 to VDD or GND to set the device address in I2C mode. SPI/I2C Select Input. Connect SPI/I2C to VDD to select SPI mode, or connect SPI/I2C to GND to select I2C mode. Serial Data Output in SPI Mode/Address Select 1 in I2C Mode. Use DOUT to daisy chain the MAX5550 to other devices or to read back in SPI mode. The digital data is clocked out on SCLK's falling edge. Connect A1 to VDD or GND to set the device address in I2C mode. No Connection. Leave unconnected or connect to GND. Reference Input. Drive REFIN with an external reference source between +0.5V and +1.5V. Leave REFIN unconnected in internal reference mode. Bypass with a 0.1F capacitor to GND as close to the device as possible. Ground DACB Output. OUTB provides up to 30mA of output current. DACB Full-Scale Adjust Input. For maximum full-scale output current, connect a 20k resistor between FSADJB and GND. For minimum full-scale current, connect a 40k resistor between FSADJB and GND. DACA Full-Scale Adjust Input. For maximum full-scale output current, connect a 20k resistor between FSADJA and GND. For minimum full-scale current, connect a 40k resistor between FSADJA and GND. DACA Output. OUTA provides up to 30mA of output current. Power Supply Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1F capacitor as close to the device as possible.
5 6, 13, 15 7 8, 16 9 10 11 12 14
DOUT/A1 N.C. REFIN GND OUTB FSADJB FSADJA OUTA VDD
Detailed Description
Architecture
The MAX5550 10-bit, dual current-steering DAC (see the Functional Diagram) operates with DAC update rates up to 10Msps in SPI mode and 400ksps in I2C mode. The converter consists of a 16-bit shift register and input DAC registers, followed by a current-steering array. The current-steering array generates full-scale currents up to 30mA per DAC. An integrated +1.25V bandgap reference, control amplifier, and an external resistor determine each data converter's full-scale output range.
for the current outputs of the DAC. This device has a software-selectable full-scale current range (see the command summary in Table 4). After selecting a current range, an external resistor (RFSADJ_) sets the fullscale current. See Table 1 for a matrix of I FS and RFSADJ selections. During startup, when the power is first applied, the MAX5550 defaults to the external reference mode, and to the 1mA-2mA full-scale current-range mode.
DAC Data
The 10-bit DAC data is decoded as offset binary, MSB first, with 1 LSB = IFS / 1024, and converted into the corresponding current as shown in Table 2.
Reference Architecture and Operation
The MAX5550 provides an internal +1.25V bandgap reference or accepts an external reference voltage source between +0.5V and +1.5V. REFIN serves as the input for an external low-impedance reference source. Leave REFIN unconnected in internal reference mode. Internal or external reference mode is software selectable through the SPI/I2C serial interface. The MAX5550's reference circuit (Figure 1) employs a control amplifier to regulate the full-scale current (IFS)
8
Serial Interface
The MAX5550 features a pin-selectable SPI/I2C serial interface. Connect SPI/I2C to GND to select I2C mode, or connect SPI/I2C to VDD to select SPI mode. SDA and SCL (I2C mode) and DIN, SCLK, and CS (SPI mode) facilitate communication between the MAX5550 and the master. The serial interface remains active in shutdown.
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Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
I2C Compatibility (SPI/I2C = GND)
The MAX5550 is compatible with existing I2C systems (Figure 2). SCL and SDA are high-impedance inputs; SDA has an open-drain output that pulls the data line low during the ninth clock pulse. SDA and SCL require pullup resistors (2.4k or greater) to VDD. Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals. The communication protocol supports standard I2C 8-bit communications. The device's address is compatible with 7-bit I2C addressing protocol only. Ten-bit address formats are not supported. Only write commands are accepted by the MAX5550. Note: I2C readback is not supported. Bit Transfer One data bit transfers during each SCL rising edge. The MAX5550 requires nine clock cycles to transfer data into or out of the DAC register. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). Both SDA and SCL idle high. START and STOP Conditions The master initiates a transmission with a START condition (S), (a high-to-low transition on SDA with SCL high). The master terminates a transmission with a STOP condition (P), (a low-to-high transition on SDA while SCL is high) (Figure 3). A START condition from the master signals the beginning of a transmission to the MAX5550. The master terminates transmission by issuing a STOP condition. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active.
MAX5550
Table 1. Full-Scale Output Current and RFSADJ_ Selection Based on a +1.25V (typ) Reference Voltage
FULL-SCALE OUTPUT CURRENT (mA)* 1mA-2mA 1.00 1.25 1.50 1.75 2.00 1.5mA-3mA 1.500 1.875 2.250 2.625 3.000 2.5mA-5mA 2.500 3.125 3.750 4.375 5.000 4.5mA-9mA 4.500 5.625 6.750 7.875 9.000 8mA-16mA 8.00 10.00 12.00 14.00 16.00 15mA-30mA 15.00 18.75 22.50 26.25 30.00 40 35 30 25 20 RFSADJ (k) Calculated 1% EIA Std 40.2 34.8 30.1 24.9 20.0
*See the command summary in Table 4.
Table 2. DAC Output Code Table
DAC CODE
VDD
IOUT_
+1.25V REFERENCE
11 1111 1111
I 1023 x FS - | IOS | 1024 I I 1023 x FS - | IOS | 1024 I 1023 x FS - | IOS | 1024
IFSADJ RFSADJ
FSADJ_ CURRENT-SOURCE ARRAY DAC
OUT_
10 0000 0000
00 0000 0001*
GND
00 0000 0000
0
Figure 1. Reference Architecture and Output Current Adjustment *Negative output current values = 0 _______________________________________________________________________________________ 9
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
S Sr tRDA SDA P
tFDA tHD:DAT
tSU:STA
tHD:STA
tSU:STO
tSU:DAT SCL tFCL tRCL tHIGH tLOW tFCL tLOW tHIGH tRCL
Figure 2. I2C Serial-Interface Timing Diagram
Early STOP Conditions The MAX5550 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 4). This condition is not allowed in the I2C format. Repeated START Conditions A repeated START (Sr) condition is used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5550's serial interface supports continuous write operations with an Sr condition separating them. Acknowledge Bit (ACK) Successful data transfers are acknowledged with an acknowledge bit (ACK). Both the master and the MAX5550 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledgerelated clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 5). Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
S SDA
Sr
P
SCL
Figure 3. START and STOP Conditions
SCL SDA STOP START
LEGAL STOP CONDITION
SCL SDA
START
ILLEGAL STOP
ILLEGAL EARLY STOP CONDITION
Figure 4. Early STOP Conditions 10 ______________________________________________________________________________________
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
S SDA ACKNOWLEDGE SCL 1 2 8 9
Figure 5. Acknowledge Condition
Table 3. Write Operation
S T A R T Master SDA Slave SDA S 0 1 ADDRESS BYTE R/ W* 1 0 0 A1 A0 0 A C K C5 C4 C3 C2 C1 C0 D9 D8 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P P
COMMAND/DATA BYTE
DATA BYTE
*Read operation not supported.
Slave Address A master initiates communication with a slave device by issuing a START condition followed by a slave address (see Table 3). The slave address consists of 7 address bits and a read/write bit (R/W). When idle, the device continuously waits for a START condition followed by its slave address. When the device recognizes its slave address, it acquires the data and executes the command. The first 5 bits (MSBs) of the slave address have been factory programmed and are always 01100. Connect A1 and A0 to VDD or GND to program the remaining 2 bits of the slave address. Set the least significant bit (LSB) of the address byte (R/W) to zero to write to the MAX5550. After receiving the address, the MAX5550 (slave) issues an acknowledge by pulling SDA low for one clock cycle. I2C read commands (R/W = 1) are not acknowledged by the MAX5550. Write Cycle The write command requires 27 clock cycles. In write mode (R/W = 0), the command/data byte that follows the address byte controls the MAX5550 (Table 3). The registers update on the rising edge of the 26th SCL
pulse. Prematurely aborting the write cycle does not update the DAC. See Table 4 for a command summary.
SPI Compatibility (SPI/I2C = VDD)
The MAX5550 is compatible with the 3-wire SPI serial interface (Figure 6). This interface mode requires three inputs: chip-select (CS), data clock (SCLK), and data in (DIN). Drive CS low to enable the serial interface and clock data synchronously into the shift register on each SCLK rising edge. The MAX5550 requires 16 clock cycles to clock in 6 command bits (C5-C0) and 10 data bits (D9-D0) (Figure 7). After loading data into the shift register, drive CS high to latch the data into the appropriate DAC register and disable the serial interface. Keep CS low during the entire serial data stream to avoid corruption of the data. See Table 4 for a command summary.
Shutdown Mode
The MAX5550 has a software shutdown mode that reduces the supply current to less than 1A. Shutdown mode disables the DAC outputs. The serial interface remains active in shutdown. This provides the flexibilty to update the registers while in shut down. Recycling the power supply resets the device to the default settings.
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11
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
tCSW CS tCSO SCLK tCH tDS DIN tCSE DOUT MSB MSB tDO1 tDH LSB tCSD tCL tCSS tCP tCSH tCS1
Figure 6. SPI-Interface Timing Diagram
CS
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DIN
C5
C4
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7. SPI-Interface Format
Applications Information
Daisy Chaining (SPI/I2C = VDD)
In standard SPI-/QSPITM-/MICROWIRETM-compatible systems, a microcontroller (C) communicates with its slave devices through a 3- or 4-wire serial interface. The typical interface includes a chip-select signal (CS), a serial clock (SCLK), a data input signal (DIN), and sometimes a data signal output (DOUT). In this system, the C allots an independent slave-select signal (SS_) to each slave device so that they can be addressed individually. Only the slaves with their CS inputs asserted low acknowledge and respond to the activity on the serial clock and data lines. This is simple to implement when there are very few slave devices in the system. An alternative method is daisy chaining. Daisy
chaining, in serial-interface applications, is the method of propagating commands through devices connected in series (see Figure 8). Daisy chain devices by connecting the DOUT of one device to the DIN of the next. Connect the SCLK of all devices to a common clock and connect the CS of all devices to a common slave-select line. Data shifts out of DOUT 16.5 clock cycles after it is shifted into DIN on the falling edge of SCLK. In this configuration, the C only needs three signals (SS, SCK, and MOSI) to control all of the slaves in the network. The SPI-/QSPI-/MICROWIREcompatible serial interface normally works at up to 10MHz, but must be slowed to 5MHz if daisy chaining. DOUT is high impedance when CS is high.
QSPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 12 ______________________________________________________________________________________
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
Table 4. Command Summary
SERIAL DATA INPUT C5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 C4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 C2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 C1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 D9-D0 XXXXXXXXXX 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data 10-bit DAC data XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX No operation. Load DAC data to both DAC registers and both input registers from the shift register. Load DAC register A and input register A from the shift register. Load DAC register B and input register B from the shift register. Load both channel input registers from the shift register, both DAC registers are unchanged. Load input register A from the shift register; DAC register A is unchanged. Load input register B from the shift register; DAC register B is unchanged. Update both DAC registers from their corresponding input registers. Update DAC register A from input register A. Update DAC register B from input register B. Internal reference mode. External reference mode (default mode at power-up). Shut down both DACs. Shut down DACA. Shut down DACB. DACA 1mA-2mA full-scale current range mode (default mode at power-up) DACA 1.5mA-3mA full-scale current range mode. DACA 2.5mA-5mA full-scale current range mode. DACA 4.5mA-9mA full-scale current range mode. DACA 8mA-16mA full-scale current range mode. DACA 15mA-30mA full-scale current range mode. Power up both DACs. Power up DACA. Power up DACB. DACB 1mA-2mA full-scale current range mode (default mode at power-up) DACB 1.5mA-3mA full-scale current range mode. DACB 2.5mA-5mA full-scale current range mode. DACB 4.5mA-9mA full-scale current range mode. DACB 8mA-16mA full-scale current range mode. DACB 15mA-30mA full-scale current range mode. FUNCTIONS
______________________________________________________________________________________
13
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC MAX5550
Pin Configuration
FSADJA
CONTROLLER DEVICE MAX5550 DIN(0) SCLK DOUT(0) CS
OUTA
12 N.C. 13
11
10
OUTB 9 8 7 GND REFIN N.C. DOUT/A1 6 5 4 SPI/I2C
TOP VIEW
MAX5550 DIN(1) SCLK DOUT(1) CS
VDD 14 N.C. 15 GND 16 1 SCLK/SCL 2 DIN/SDA 3 CS/AO
MAX5550
MAX5550 DIN(2) SCLK DOUT(2) CS
THIN QFN (3mm x 3mm)
Figure 8. Daisy-Chain Configuration
Power Sequencing
Ensure that the voltage applied to REFIN does not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFIN and VDD to ensure compliance with the absolute maximum ratings. PROCESS: BiCMOS
Chip Information
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND create noise at the analog output. Return GND to the highest quality ground plane available. For extremely noisy environments, bypass REFIN and VDD to GND with 1F and 0.1F capacitors with the 0.1F capacitor as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
14
______________________________________________________________________________________
FSADJB
Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX5550
MARKING
E E/2
(ND - 1) X e
(NE - 1) X e
D2/2
D/2 D
AAAA
C L
e D2
k
b E2/2
0.10 M C A B
C L
L
E2
C L
0.10 C 0.08 C A A2 A1 L
C L
L
e
e
PACKAGE OUTLINE 12, 16L THIN QFN, 3x3x0.8mm
21-0136
F
1 2
PKG REF. A b D E e L N ND NE A1 A2 k 0 MIN. 0.70 0.20 2.90 2.90 0.45
12L 3x3 NOM. 0.75 0.25 3.00 3.00 0.50 BSC. 0.55 12 3 3 0.02 0.05 0 0.25 0.20 REF 0.25 0.65 0.30 MAX. 0.80 0.30 3.10 3.10 MIN. 0.70 0.20 2.90 2.90
16L 3x3 NOM. 0.75 0.25 3.00 3.00 0.50 BSC. 0.40 16 4 4 0.02 0.20 REF 0.05 0.50 MAX. 0.80 0.30 3.10 3.10 PKG. CODES T1233-1 T1233-3 T1233-4 T1633-1 T1633-2 T1633F-3 T1633FH-3 T1633-4
EXPOSED PAD VARIATIONS
D2 MIN. 0.95 0.95 0.95 0.95 0.95 0.65 0.65 0.95 NOM. 1.10 1.10 1.10 1.10 1.10 0.80 0.80 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 MIN. 0.95 0.95 0.95 0.95 0.95 0.65 0.65 0.95 E2 NOM. MAX. 1.10 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.225 x 45 0.225 x 45 0.35 x 45 JEDEC WEED-1 WEED-1 WEED-1 WEED-2 WEED-2 WEED-2 WEED-2 WEED-2
DOWN BONDS ALLOWED
NO YES YES NO YES N/A N/A NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C. 10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY 11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY PACKAGE OUTLINE 12, 16L THIN QFN, 3x3x0.8
21-0136
F
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Freed 7/13/05

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