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ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Data Sheet February 28, 2006 FN6046.8
5V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers
The Intersil RS-485/RS-422 devices are BiCMOS 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Unlike competitive devices, this Intersil family is specified for 10% tolerance supplies (4.5V to 5.5V). The ISL8483, ISL8488, and ISL8489 utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Data rates up to 5Mbps are achievable by using the ISL8485, ISL8490, or ISL8491, which feature higher slew rates. All devices present a "single unit load" to the RS-485 bus, which allows up to 32 transceivers on the network. Receiver (Rx) inputs feature a "fail-safe if open" design, which ensures a logic high Rx output if Rx inputs are floating. Driver (Tx) outputs are short circuit protected, even for voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. The ISL8488 - 91 are configured for full duplex (separate Rx input and Tx output pins) applications. The ISL8488 and ISL8490 are offered in space saving 8 lead packages for applications not requiring Rx and Tx output disable functions (e.g., point-to-point). Half duplex configurations (ISL8483, ISL8485) multiplex the Rx inputs and Tx outputs to allow transceivers with Rx and Tx disable functions in 8 lead packages.
Features
* Specified for 10% Tolerance Supplies * Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV * High Data Rates. . . . . . . . . . . . . . . . . . . . . . up to 5Mbps * Slew Rate Limited Versions for Error Free Data Transmission at 250kbps (ISL8483, ISL8488, ISL8489) * Single Unit Load Allows up to 32 Devices on the Bus * 1nA Low Current Shutdown Mode (ISL8483) * Low Quiescent Current: - 160A (ISL8483, ISL8488, ISL8489) - 500A (ISL8485, ISL8490, ISL8491) * -7V to +12V Common Mode Input Voltage Range * Three State Rx and Tx Outputs (Except ISL8488, ISL8490) * 30ns Propagation Delays, 5ns Skew (ISL8485, ISL8490, ISL8491) * Full Duplex and Half Duplex Pinouts * Operate from a Single +5V Supply (10% Tolerance) * Current Limiting and Thermal Shutdown for driver Overload Protection * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Factory Automation * Security Networks * Building Environmental Control Systems * Industrial/Process Control Networks * Level Translators (e.g., RS-232 to RS-422) * RS-232 "Extension Cords"
TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL8483 ISL8485 ISL8488 ISL8489 ISL8490 ISL8491 HALF/FULL DUPLEX Half Half Full Full Full Full NO. OF DEVICES DATA RATE ALLOWED ON BUS (Mbps) 32 32 32 32 32 32 0.25 5 0.25 0.25 5 5 SLEW-RATE RECEIVER/ QUIESCENT LIMITED? DRIVER ENABLE? ICC (A) Yes No Yes Yes No No Yes Yes No Yes No Yes 160 500 160 160 500 500 LOW POWER SHUTDOWN? Yes No No No No No PIN COUNT 8 8 8 14 8 14
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Ordering Information
PART NUMBER ISL8483CPZ (Note) ISL8483IB ISL8483IBZ (Note) ISL8483IB-T ISL8483IBZ-T (Note) ISL8483IP ISL8483IPZ (Note) ISL8485CB ISL8485CBZ (Note) ISL8485CB-T ISL8485CBZ-T (Note) ISL8485CP ISL8485CPZ (Note) ISL8485IB ISL8485IBZ (Note) ISL8485IB-T ISL8485IBZ-T (Note) ISL8485IP ISL8485IPZ (Note) ISL8488IB ISL8488IBZ (Note) ISL8488IB-T ISL8488IBZ-T (Note) ISL8488IP ISL8488IPZ (Note) ISL8489IB ISL8489IB-T ISL8489IP ISL8490IB ISL8490IBZ (Note) ISL8490IB-T ISL8490IBZ-T (Note) ISL8490IP ISL8491IB ISL8491IBZ (Note) ISL8491IB-T ISL8491IBZ-T (Note) ISL8491IP PART MARKING ISL8483CPZ 8483IB 8483IBZ 8483IB 8483IBZ ISL8483IP ISL8483IPZ 8485CB 8485CBZ 8485CB 8485CBZ ISL8485CP ISL8485CPZ 8485IB 8485IBZ 8485IB 8485IBZ ISL8485IP ISL8485IPZ 8488IB 8488IBZ 8488IB 8488IBZ ISL8488IP ISL8488IPZ ISL8489IB ISL8489IB ISL8489IP 8490IB 8490IBZ 8490IB 8490IBZ ISL8490IP ISL8491IB 8491IBZ ISL8491IB 8491IBZ ISL8491IP TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 0 to 70 0 to 70 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) 0 to 70 0 to 70 -40 to 85 -40 to 85 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 -40 to 85 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 8 Ld PDIP* (Pb-free) 14 Ld SOIC 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC(Pb-free) PACKAGE 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M14.15 M14.15 E14.3 M8.15 M8.15 M8.15 M8.15 E8.3 M14.15 M14.15 M14.15 M14.15 E14.3
14 Ld SOIC Tape and Reel -40 to 85 -40 to 85 -40 to 85 8 Ld SOIC Tape and Reel 8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 14 Ld SOIC 14 Ld SOIC (Pb-free) 14 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free)
14 Ld SOIC Tape and Reel 14 Ld SOIC Tape and Reel (Pb-free) -40 to 85 14 Ld PDIP
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Pinouts
ISL8483, ISL8485 (PDIP, SOIC) TOP VIEW
RO 1 RE 2 DE 3 DI 4 D 8 7 6 5 VCC B/Z A/Y GND
ISL8488, ISL8490 (PDIP, SOIC) TOP VIEW
VCC 1 RO 2 DI 3 GND 4 D 8 7 6 5 A B Z Y
ISL8489, ISL8491 (PDIP, SOIC) TOP VIEW
NC 1 RO 2 R RE 3 DE 4 DI 5 GND 6 GND 7 D 12 A 11 B 10 Z 9Y 8 NC 14 VCC 13 NC
R
R
Truth Tables
TRANSMITTING INPUTS RE X X 0 1 DE 1 1 0 0 DI 1 0 X X Z 0 1 High-Z High-Z * OUTPUTS Y 1 0 0 0 High-Z 0 High-Z * 1 *Shutdown Mode for ISL8483 (see Note 7) 1 1 1 X High-Z *Shutdown Mode for ISL8483 (see Note 7) 0 0 X High-Z * 0 X Inputs Open 1 0 X 0 X RE RECEIVING INPUTS DE DE Half Duplex Full Duplex A-B +0.2V -0.2V OUTPUT RO 1 0
Pin Descriptions
PIN RO RE DE DI GND A/Y B/Z A B Y Z VCC NC FUNCTION Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. Ground connection. Noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1. Inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. Noninverting receiver input. Inverting receiver input. Noninverting driver output. Inverting driver output. System power supply input (4.5V to 5.5V). No Connection.
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Typical Operating Circuits
ISL8483, ISL8485
+5V + 0.1F 8 VCC 1 2 3 4 RO RE DE DI D GND 5 GND 5 R R B/Z A/Y 7 6 RT RT 7 6 B/Z A/Y 0.1F 8 VCC D DI DE RE RO 4 3 2 1 + +5V
ISL8488, ISL8490
+5V + 0.1F 1 VCC A 2 RO R B 8 7 RT 5 6 Y Z D DI 3 0.1F 1 VCC + +5V
Z 3 DI D GND 4 Y
6 5
RT
7 8
B A GND 4 R RO 2
ISL8489, ISL8491
+5V + 0.1F 14 VCC 2 3 4 5 RO RE DE Z DI D GND 6, 7 Y 10 9 RT 11 12 B A GND 6, 7 R RO 2 R A B 12 11 RT 0.1F 14 9 10 Y Z VCC DI D DE RE 4 3 5 + +5V
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Absolute Maximum Ratings
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Input/Output Voltages A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Short Circuit Duration Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >7kV
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
Operating Conditions
Temperature Range ISL84XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C ISL84XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . 140 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 120 14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25C, Note 2 SYMBOL TEST CONDITIONS TEMP (C) MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Driver Differential VOUT (no load) Driver Differential VOUT (with load)
VOD1 VOD2 R = 50 (RS-422), Figure 1 R = 27 (RS-485), Figure 1
Full Full Full Full
2 1.5 -
3 2.3 0.01
VCC 5 0.2
V V V V
Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Logic Input High Voltage Logic Input Low Voltage Logic Input Current
VOD
R = 27 or 50, Figure 1
VOC VOC
R = 27 or 50, Figure 1 R = 27 or 50, Figure 1
Full Full
-
0.01
3 0.2
V V
VIH VIL IIN1 IIN1 IIN1
DE, DI, RE DE, DI, RE DE, DI, RE (ISL8483) DI (ISL8485 - ISL8491) DE, RE (ISL8485, ISL8489, ISL8491) DE = 0V, VCC = 0V or 4.5 to 5.5V -7V VCM 12V VCM = 0V IO = -4mA, VID = 200mV IO = -4mA, VID = 200mV 0.4V VO 2.4V VIN = 12V VIN = -7V
Full Full Full Full Full Full Full Full 25 Full Full Full
2 -2 -2 -25 -0.2 3.5 -
70 -
0.8 2 2 25 1 -0.8 0.2 0.4 1
V V A A A mA mA V mV V V A
Input Current (A, B), Note 10
IIN2
Receiver Differential Threshold Voltage Receiver Input Hysteresis Receiver Output High Voltage Receiver Output Low Voltage Three-State (high impedance) Receiver Output Current
VTH VTH VOH VOL IOZR
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25C, Note 2 (Continued) SYMBOL RIN ICC TEST CONDITIONS -7V VCM 12V ISL8488, ISL8489, DE, DI, RE = 0V or VCC ISL8490, ISL8491, DE, DI, RE = 0V or VCC ISL8485, DI, RE = 0V or DE = VCC VCC DE = 0V ISL8483, DI, RE = 0V or DE = VCC VCC DE = 0V Shutdown Supply Current Driver Short-Circuit Current, VO = High or Low Receiver Short-Circuit Current ISHDN IOSD1 IOSR ISL8483, DE = 0V, RE = VCC, DI = 0V or VCC DE = VCC, -7V VY or VZ 12V, Note 4 0V VO VCC TEMP (C) Full Full Full Full Full Full Full Full Full Full MIN 12 35 7 TYP 160 500 700 500 470 160 1 MAX 250 565 900 565 650 250 50 250 85 UNITS k A A A A A A nA mA mA
PARAMETER Receiver Input Resistance No-Load Supply Current, Note 3
SWITCHING CHARACTERISTICS (ISL8485, ISL8490, ISL8491) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable from Output High Driver Disable from Output Low Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | Receiver Enable to Output High Receiver Enable to Output Low Receiver Disable from Output High Receiver Disable from Output Low Maximum Data Rate tPLH, tPHL RDIFF = 54, CL = 100pF, Figure 2 tSKEW tR, tF tZH tZL tHZ tLZ RDIFF = 54, CL = 100pF, Figure 2 RDIFF = 54, CL = 100pF, Figure 2 CL = 100pF, SW = GND, Figure 3 CL = 100pF, SW = VCC, Figure 3 CL = 15pF, SW = GND, Figure 3 CL = 15pF, SW = VCC, Figure 3 Full Full Full Full Full Full Full Full 25 Full Full Full Full Full 18 3 30 5 30 2 11 17 14 19 13 40 5 9 9 9 9 50 10 25 70 70 70 70 150 50 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns Mbps
tPLH, tPHL Figure 4 tSKD tZH tZL tHZ tLZ fMAX Figure 4 CL = 15pF, SW = GND, Figure 5 CL = 15pF, SW = VCC, Figure 5 CL = 15pF, SW = GND, Figure 5 CL = 15pF, SW = VCC, Figure 5 Note 11
SWITCHING CHARACTERISTICS (ISL8483, ISL8488, ISL8489) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable from Output High Driver Disable from Output Low Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | Receiver Enable to Output High Receiver Enable to Output Low Receiver Disable from Output High tPLH, tPHL RDIFF = 54, CL = 100pF, Figure 2 tSKEW tR, tF tZH tZL tHZ tLZ RDIFF = 54, CL = 100pF, Figure 2 RDIFF = 54, CL = 100pF, Figure 2 CL = 100pF, SW = GND, Figure 3, Note 5 CL = 100pF, SW = VCC, Figure 3, Note 5 CL = 15pF, SW = GND, Figure 3 CL = 15pF, SW = VCC, Figure 3 Full Full Full Full Full Full Full Full 25 Full Full Full 250 250 250 250 300 300 250 800 160 800 350 25 10 10 10 2000 800 2000 2000 2000 3000 3000 2000 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns
tPLH, tPHL Figure 4 tSKD tZH tZL tHZ Figure 4 CL = 15pF, SW = GND, Figure 5, Note 6 CL = 15pF, SW = VCC, Figure 5, Note 6 CL = 15pF, SW = GND, Figure 5
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25C, Note 2 (Continued) SYMBOL tLZ fMAX tSHDN TEST CONDITIONS CL = 15pF, SW = VCC, Figure 5 Note 11 Note 7 TEMP (C) Full Full Full Full Full Full Full MIN 250 50 TYP 10 200 MAX 50 600 2000 2000 2500 2500 UNITS ns kbps ns ns ns ns ns
PARAMETER Receiver Disable from Output Low Maximum Data Rate Time to Shutdown (ISL8483 only) Driver Enable from Shutdown to Output High (ISL8483 only) Driver Enable from Shutdown to Output Low (ISL8483 only) Receiver Enable from Shutdown to Output High (ISL8483 only) Receiver Enable from Shutdown to Output Low (ISL8483 only) NOTES:
tZH(SHDN) CL = 100pF, SW = GND, Figure 3, Notes 7, 8 tZL(SHDN) CL = 100pF, SW = VCC, Figure 3, Notes 7, 8
tZH(SHDN) CL = 15pF, SW = GND, Figure 5, Notes 7, 9 tZL(SHDN) CL = 15pF, SW = VCC, Figure 5, Notes 7, 9
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 3. Supply current specification is valid for loaded drivers when DE = 0V. 4. Applies to peak current. See "Typical Performance Curves" for more information. 5. When testing the ISL8483, keep RE = 0 to prevent the device from entering SHDN. 6. When testing the ISL8483, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN. 7. The ISL8483 is put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See "Low-Power Shutdown Mode" section. 8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN. 9. Set the RE signal high time >600ns to ensure that the device enters SHDN. 10. Devices meeting these limits are denoted as "single unit load (1 UL)" transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus. 11. Guaranteed by characterization, but not tested.
Test Circuits and Waveforms
R VCC DE Z DI D Y R VOC VOD
FIGURE 1. DRIVER VOD AND VOC
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Test Circuits and Waveforms (Continued)
3V DI 1.5V 1.5V 0V DE DI D Y SIGNAL GENERATOR OUT (Z) Z RDIFF CL = 100pF tPHL 50% tPLH VOH 50% VOL +VOD -VOD CL = 100pF tPLH OUT (Y) 50% tPHL VOH 50% VOL
VCC
DIFF OUT (Y - Z) tR
90% 10%
90% 10% tF
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE DI D SIGNAL GENERATOR Y CL SW Z 500 VCC GND 3V DE NOTE 7 tZH, tZH(SHDN) NOTE 7 OUT (Y, Z) 1.5V 1.5V 0V tHZ VOH - 0.5V VOH 0V tZL, tZL(SHDN) NOTE 7 OUT (Y, Z) 2.3V OUTPUT LOW tLZ VCC VOL + 0.5V V OL
OUTPUT HIGH 2.3V
(SHDN) for ISL8483 only
PARAMETER OUTPUT tHZ tLZ tZH tZL tZH(SHDN) tZL(SHDN) Y/Z Y/Z Y/Z Y/Z Y/Z Y/Z
RE X X 0 (Note 5) 0 (Note 5) 1 (Note 8) 1 (Note 8)
DI 1/0 0/1 1/0 0/1 1/0 0/1
SW GND VCC GND VCC GND VCC
CL (pF) 15 15 100 100 100 100 FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
RE +1.5V B A R 15pF RO tPLH SIGNAL GENERATOR RO 50% tPHL A 1.5V 1.5V
3V 0V
VCC 50% 0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Test Circuits and Waveforms (Continued)
RE B R SIGNAL GENERATOR A 15pF tZH, tZH(SHDN) NOTE 7 (SHDN) for ISL8483 only. RO OUTPUT HIGH 1.5V 0V tZL, tZL(SHDN) NOTE 7 RO 1.5V OUTPUT LOW tLZ VCC VOL + 0.5V V
OL
RO
1k SW
NOTE 7 VCC GND 3V RE 1.5V 1.5V 0V tHZ VOH - 0.5V VOH
PARAMETER tHZ tLZ tZH (Note 6) tZL (Note 6) tZH(SHDN) (Note 9) tZL(SHDN) (Note 9)
DE 0 0 0 0 0 0
A +1.5V -1.5V +1.5V -1.5V +1.5V -1.5V
SW GND VCC GND VCC GND VCC FIGURE 5B. MEASUREMENT POINTS
FIGURE 5A. TEST CIRCUIT
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
Application Information
RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 spec requires that drivers must handle bus contention without sustaining any damage. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000', so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields.
Receivers easily meet the data rates supported by the corresponding driver. ISL8483/85/89/91 receiver outputs are three-statable via the active low RE input.
Driver Features
The RS-485/422 driver is a differential output device that delivers at least 1.5Vacross a 54 load (RS-485), and at least 2V across a 100 load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. Drivers of the ISL8483/85/89/91 are three-statable via the active high DE input. The ISL8483/88/89 driver outputs are slew rate limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Data rate on these slew rate limited versions is a maximum of 250kbps. Outputs of ISL8485/90/91 drivers are not limited, so faster output transition times allow data rates of at least 5Mbps.
Data Rate, Cables, and Terminations
RS-485/422 are intended for network lengths up to 4000', but the maximum system data rate decreases as the transmission length increases. Devices operating at 5Mbps are limited to lengths less than 100', while the 250kbps versions can operate at full data rates with lengths in excess of 1000'. Twisted pair is the cable of choice for RS-485/422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. Proper termination is imperative, when using the 5Mbps devices, to minimize reflections. Short networks using the 250kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern.
FN6046.8 February 28, 2006
Receiver Features
These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is 200mV, as required by the RS422 and RS-485 specifications. Receiver input impedance surpasses the RS-422 spec of 4k, and meets the RS-485 "Unit Load" requirement of 12k minimum. Receiver inputs function with common mode voltages as great as 7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages are a realistic concern. All the receivers include a "fail-safe if open" function that guarantees a high level receiver output if the receiver inputs are unconnected (floating).
9
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. In the event of a major short circuit condition, ISL84XX devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically reenable after the die temperature drops about 15 degrees. If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown.
Built-In Driver Overload Protection
As stated previously, the RS-485 spec requires that drivers survive worst case bus contentions undamaged. The ISL84XX devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-485 spec, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply.
Low Power Shutdown Mode (ISL8483 Only)
These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but the ISL8483 includes a shutdown feature that reduces the already low quiescent ICC to a 1nA trickle. The ISL8483 enters shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a period of at least 600ns. Disabling both the driver and the receiver for less than 50ns guarantees that the ISL8483 will not enter shutdown. Note that receiver and driver enable times increase when the ISL8483 enables from shutdown. Refer to Notes 5-8, at the end of the Electrical Specification table, for more information.
Typical Performance Curves
90 DRIVER OUTPUT CURRENT (mA) 80 70 60 50 40 30 20 10 0 0 1 2 3
VCC = 5V, TA = 25C, ISL8483 thru ISL8491; Unless Otherwise Specified
3.6 DIFFERENTIAL OUTPUT VOLTAGE (V) 3.4 3.2 3 2.8 2.6 2.4 RDIFF = 54 2.2 2 -40 -25 0 25 50 75 85 RDIFF = 100
4
5
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (C)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Typical Performance Curves
160 140 120 100 OUTPUT CURRENT (mA) 80 60 ICC (A) 40 20 0 -20 -40 -60 Y OR Z = HIGH Y OR Z = LOW
VCC = 5V, TA = 25C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
700 650 600 550 500 450 400 350 300 250 200 ISL8483, DE = GND, RE = GND; ISL8488/89, DE = RE = X -25 0 25 50 75 85 ISL8485, DE = GND, RE = X, ISL8490/91, GND, RE X ISL8485, DE =DE = RE == X ISL8483, DE = VCC, RE = X ISL8485, DE = VCC, RE = X
-80 -100 -120 -7 -6 -4 -2 0 2 4 6 OUTPUT VOLTAGE (V) 8 10 12
150 -40
TEMPERATURE (C)
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE
1200 1100 PROPAGATION DELAY (ns) 1000 900 800 700 600 500 -40 SKEW (ns) tPHLY tPHLZ tPLHY tPLHZ
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
400
300 |tPHLY - tPLHZ| 200 |tPLHY - tPHLZ|
100 |CROSS PT. OF Y & Z - CROSS PT. OF Y & Z| 0 -40
-25
0
25
50
75
85
-25
0
25
50
75
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 10. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL8483, ISL8488, ISL8489)
FIGURE 11. DRIVER SKEW vs TEMPERATURE (ISL8483, ISL8488, ISL8489)
40
3
PROPAGATION DELAY (ns)
35 tPHLY 30 SKEW (ns) tPHLZ tPLHZ tPLHY 25
2.5
|tPHLY - tPLHZ|
2
|tPLHY - tPHLZ|
1.5 |CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z|
20 -40
-25
0
25
50
75
85
1 -40
-25
0
25
50
75
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 12. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL8485, ISL8490, ISL8491)
FIGURE 13. DRIVER SKEW vs TEMPERATURE (ISL8485, ISL8490, ISL8491)
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FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Typical Performance Curves
RECEIVER OUTPUT (V)
VCC = 5V, TA = 25C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
DRIVER INPUT (V) RECEIVER OUTPUT (V) RDIFF = 54, CL = 100pF 5 DI 0 5 RO 0 DRIVER INPUT (V)
RDIFF = 54, CL = 100pF DI 5 0 5 RO 0
DRIVER OUTPUT (V)
4 3 2 1 0 TIME (400ns/DIV) B/Z
DRIVER OUTPUT (V)
4 3 2 1 0 TIME (400ns/DIV) A/Y B/Z
A/Y
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8483, ISL8488, ISL8489)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL8483, ISL8488, ISL8489)
RECEIVER OUTPUT (V)
DRIVER INPUT (V)
RECEIVER OUTPUT (V)
RDIFF = 54, CL = 100pF DI 5 0 5 0 RO
RDIFF = 54, CL = 100pF 5 DI 0 5 0 RO
DRIVER OUTPUT (V)
DRIVER OUTPUT (V)
4 3 2 1 0 TIME (10ns/DIV) B/Z A/Y
4 3 2 1 0 TIME (10ns/DIV) A/Y B/Z
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8485, ISL8490, ISL8491)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL8485, ISL8490, ISL8491)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 518 PROCESS: Si Gate CMOS
12
FN6046.8 February 28, 2006
DRIVER INPUT (V)
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
13
FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
14
FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
15
FN6046.8 February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E
A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6046.8 February 28, 2006

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