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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
IDTCV123
FEATURES:
DESCRIPTION:
* One high precision PLL for CPU, with SSC and N programmable * One high precision PLL for SRC/PCI/SATA, SSC and N programmable * One high precision PLL for 96MHz/48MHz * Band-gap circuit for differential outputs * Supports spread spectrum modulation, down spread 0.5% * Supports SMBus block read/write, index read/write * Selectable output strength for REF * Allows for CPU frequency to change to a higher frequency for maximum system computing power * Available in SSOP package
IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.
OUTPUTS:
* 2*0.7V current -mode differential CPU CLK pair * 8*0.7V current -mode differential SRC CLK pair, one dedicated for SATA * One CPU_ITP/SRC selectable CLK pair * 8*PCI, 3 free running, 33.3MHz * 1*96MHz, 1*48MHz * 2*REF
KEY SPECIFICATION:
* * * * *
CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1 SSC N Programmable
CPU CLK Output Buffers Stop Logic
CPU[1:0]
X1
XTAL Osc Amp
CPU_ITP/SRC6 IREF REF[0:1] ITP_EN
X2
SDATA SCLK SM Bus Controller PLL2 SSC N Programmable SRC CLK Output Buffer Stop Logic SRC[6:0] SATA_SRC PCI[5:0], PCIF[2:0] IREF VTT_PWRGD#/PD Control Logic FSA.B.C PLL3 48MHz/96MHz Output BUffer DOT96
48MHz
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
MAY 2004
DSC-6538/4
IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0 PCI1 VDD_PCI GND_PCI
PCI2 PCI3 PCI4 PCI5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDA Description 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage GND - 0.5 Storage Temperature Ambient Operating Temperature Case Temperature Input ESD Protection Human Body Model
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Min
Max 4.6 4.6 +150 +70 +115
Unit V V C C C V
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9
VDD_REF REF0/FSC REF1/FSA GND_REF X 1 X 2 SDAT SCL GND_CPU
CPU0 CPU0#
VDDIN TSTG TAMBIENT TCASE ESD Prot
-65 0 2000
GND_PCI VDD_PCI *TEST_SEL/PCIF0 ITP_EN/PCIF1 VDD48
USB48/FSB
VDD_CPU
CPU1 CPU1#
GND48
DOT96 DOT96#
IREF GND_A VDD_A
CPU_ITP/SRC6 CPU_ITP#/SRC6#
ITP_EN 1 0
pin 38 CPUC2_ITP SRCC6
pin 39 CPUT_ITP SRCT6
VTT_PWRGD#/PD
SRC0 SRC0# SRC1 SRC1#
VDD_SRC
SRC5 SRC5#
TEST CLARIFICATION TABLE
HW SW TEST_SEL/ TEST SELECT PCICLK_F0 BIT B6b6 OUTPUT 0 0 Normal 1 X Hi-Z Comments Normal Operation Power-up with TEST_SEL =1 to enter test mode. Cycle power with TEST_SEL = 0 to disable test mode If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B6b6. Cycle power with TEST_SEL = 0 to disable test mode.
VDD_SRC
GND_SRC SRC2 SRC2# SATA_SRC SATA_SRC#
GND_SRC
SRC4 SRC4# SRC3 SRC3#
0
1
Hi-Z
VDD_SRC
* = Internal pull down
SSOP TOP VIEW
FREQUENCY SELECTION TABLE
FSC, B, A 101 001 011 010 000 100 110 111 CPU Mode, MHz 100 133 166 200 266 333 400 Reserve SRC4 100 100 100 100 100 100 100 100 SRC[3:1], SRC[7:5] 100 100 100 100 100 100 100 100 2 PCI 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 USB 48 48 48 48 48 48 48 48 DOT96 96 96 96 96 96 96 96 96 REF 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Name PCI0 PCI1 VDD_PCI VSS_PCI PCI2 PCI3 PCI4 PCI5 VSS_PCI VDD_PCI TEST_SEL/PCIF0 ITP_EN/PCIF1 VDD48 USB48 /FS_B VSS48 DOT96T DOT96C VTT_PWRGD#/PD Type OUT OUT PWR GND OUT OUT OUT OUT GND PWR I/O OUT PWR I/O GND OUT OUT I/O Description PCI clock PCI clock 3.3V GND PCI clock PCI clock PCI clock PCI clock GND 3.3V Test Select (sampled at VTT_PWRGD# assertion), see TEST_SEL table. PCI clock afterward, free running. Pin38, 39, CPU_ITP/SRC6 select (sampled on VTT_PWRGD# assertion), HIGH = CPU_2PCI clock. PCI clock afterward, running. 3.3V 48MHz clock/ FS_B input GND 96MHz 0.7V current mode differential clock output 96MHz 0.7V current mode differential clock output 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C, TEST_SEL and ITP_EN inputs, VTT_PWRGD# is low assertion/ After VTT_PWRGD# assertion, becomes a real-time input for asserting power down (active HIGH). Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock 3.3V GND Differential Serial reference clock Differential Serial reference clock SATA clock SATA clock 3.3V Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock GND Differential Serial reference clock Differential Serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCC6. Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRCT6. 3.3V GND Reference current for differential output buffer
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SRCT0 SRCC0 SRCT1 SRCC1 VDD_SRC VSS_SRC SRCT2 SRCC2 SRCT_SATA SRCC_SATA VDD_SRC SRCC3 SRCT3 SRCC4 SRCT4 VSS_SRC SRCC5 SRCT5 VDD_SRC CPUC2_ITP/ SRCC6 CPUT2_ITP/ SRCT6 VDD_A VSS_A IREF
OUT OUT OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT OUT OUT GND OUT OUT PWR OUT OUT PWR GND OUT
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Name CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 VSS_CPU SCL SDA XTAL_OUT XTAL_IN VSS_REF REF1/ FSA REF0/ FSC VDD_REF Type OUT OUT PWR OUT OUT GND IN I/O OUT IN GND I/O I/O PWR Description Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output 3.3V Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output GND SM bus clock SM bus data Xtal output Xtal input GND 14.318 MHz reference clock output. CPU frequency selection at VTT_PWRGD# assertion. 14.318 MHz reference clock output. CPU frequency selection at VTT_PWRGD# assertion. 3.3V
INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N, (0 is not valid Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop
INDEX BLOCK READ PROTOCOL
Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave
Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37).
Description Start D2H Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3H Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop
Master Slave Master
INDEX BYTE WRITE
INDEX BYTE READ
Setting bit[11:18] = starting address, bit[20:27] = 01h.
Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
* *
Use Index byte write. For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. 2. 3. Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
* * *
Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming.
Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don't write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes.
SSC MAGNITUDE CONTROL, SMC
SMC[2:0] 000 001 010 011 100 101 110 111 -0.25 -0.5 -0.75 -1 0.125 0.25 0.375 0.5
FREQUENCY SELECTION TABLE
FS_C, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 RESERVE
RESOLUTION
CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 0
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPUT2, CPUC2/ SRCT6, SRCC6 SRCT5, SRCT4, SRCT3, SATAT, SRCT2, SRCT1, SRCT0, SRCC5 SRCC4 SRCC3 SATAC SRCC2 SRCC1 SRCC0 Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 1
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserved DOT96T, DOT96C USB48 REF0 REF1 CPUT1, CPUC1 CPUT0, CPUC0 Spread Spectrum Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Spread Spectrum Enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Off 1 Enable Enable Enable Enable Enable Enable On Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 0
BYTE 2
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF1 PCIF0 Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 3
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPUT2, CPUC2/ SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 SRCT3, SRCC3 SATAT, SATAC SRCT2, SRCC2 SRCT1, SRCC1 SRCT0, SRCC0 Description / Function 0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running 1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0
Free running, not affected by PCI/SRC_Stop bit (Byte6, bit3)
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 4
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserved DOT96 PCIF1 PCIF0 Reserved Reserved Reserved Reserved Description / Function DOT96 power down drive mode Free running, not affected by PCI/SRC_Stop bit (Byte6, bit3) 0 Driven in power down Free-Running Free-Running 1 Tristate Stoppable Stoppable Type RW RW RW Power On 1 0 0 0 1 1 1 1
BYTE 5
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Stopped SRC Reserved Reserved Reserved SRC CPU_ITP CPU1 CPU0 Description / Function Drive Mode in PCI_Stop 0 Driven 1 Tristate Type RW Power On 0 0 0 0 0 0 0 0
SRC PWRDWN drive mode CPUT2 PWRDWN drive mode CPUT1 PWRDWN drive mode CPUT0 PWRDWN drive mode
Driven in power down Driven in power down Driven in power down Driven in power down
Tristate in power down Tristate in power down Tristate in power down Tristate in power down
RW RW RW RW
BYTE 6
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserved Test Select REF1 REF0 PCI/SRC_STOP Description / Function Test Select Strength Select Strength Select Stop all stoppable PCI/SRCT clocks FS_C latch read back FS_B latch read back FS_A latch read back 0 normal 1x 1x stop 1 All CLK outputs Hi-Z 2x 2x running R R R Type Power On 0 0 1 1 1
BYTE 7
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 0 1 Type Power On 0 0 0 0 0 1 0 1
7
IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 8
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRC SSC enable Description / Function Only valid when Byte1 bit0 is 1 CPU PLL power down SRC PLL power down USB PLL power down USB 48 Strength control N Programming enable One cycle read 0 disable normal normal normal 1x Disable disable 1 enable Power down Power down Power down 2x enable enable Type RW RW RW RW RW RW RW RW Power On 1 0 0 0 0 0 0 0
USB48 Reserve
BYTE 9
Bit 7 6 5 4 3 2 1 0 CPU SMC2 CPU SMC1 CPU SMC0 Reserve SRC SMC2 SRC SMC1 SRC SMC0 Output(s) Affected Description / Function Must be 0 0 Must be 0 1 Type RW RW RW RW RW RW RW RW Power On 0 (Must be 0) 0 0 1 0 0 0 1
see SMC table CPU PLL SSC control
see SMC table SRC/PCI SSC control
BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 17
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPU_N7, MSB CPU_N6 CPU_N5 CPU_N4 CPU_N3 CPU_N2 CPU_N1 CPU_N0, LSB Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On
see Resolution table CPU CLK = N* Resolution
BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 25
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRC_N7, MSB SRC_N6 SRC_N5 SRC_N4 SRC_N3 SRC_N2 SRC_N1 SRC_N0, LSB Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On
100MHz N= 150 Resolution = 0.666667 SRC f = N*SRC Resolution
BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol VIH VIL VIH_FS VIL_FS IIL IDD3.3OP IDD3.3PD FI LPIN CIN COUT CINX TSTAB Clock Stabilization(2,3) Modulation Frequency(2) TDRIVE_SRC(2) TDRIVE_PD#(2) TFALL_PD#(2) TRISE_PD#(3) TDRIVE_CPU_Stop#(2) TFALL_CPU_Stop#(2) TRISE_CPU_Stop#(3) Input Capacitance(2) Parameter Input HIGH Voltage Input LOW Voltage LOW Voltage, HIGH Threshold LOW Voltage, LOW Threshold Input LeakageCurrent Operating Supply Current Powerdown Current Input Frequency(1) Pin Inductance(2) Logic inputs Output pin capacitance X1 and X2 pins From VDD power-up or de-assertion of PD# to first clock Triangular modulation SRC output enable after PCI_Stop# de-assertion CPU output enable after PD# de-assertion Fall time of PD# Rise time of PD# CPU output enable after CPU_Stop# de-assertion Fall time of PD# Rise time of PD# 3.3V 5% 3.3V 5% For FSA.B.C test_mode For FSA.B.C test_mode 0< VIN < VDD, no internal pull-up or pull-down Full active, CL = full load All differential pairs driven All differential pairs tri-stated VDD = 3.3V Test Conditions Min. 2 VSS - 0.3 0.7 VSS - 0.3 -5 -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- 14.31818 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD + 0.3 0.8 VDD + 0.3 0.35 +5 400 70 12 -- 7 5 6 5 1.8 33 15 300 5 5 10 5 5 ms KHz ns us ns ns us ns ns pF MHz nH Unit V V V V mA mA mA
NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol ZO VOH3 VOL3 VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm Parameter Current Source Output Impedance(2) Output HIGH Voltage Output LOW Voltage Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Long Accuracy(2,3)
Variation of crossing over all edges
Test Conditions VO = VX IOH = -1mA IOL = 1mA Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value
Min. 3000 2.4 -- 660 -150 -- -300 250 -- -300 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 10.4135 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.912 10.1635 175 175 -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- 0.4 850 150 1150 -- 550 140 300 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.003 10.4198 -- -- -- -- -- -- -- -- 700 700 125 125 55 100 85
Unit V V mV mV mV mV ppm
See TPERIOD Min. - Max. values 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread
TPERIOD
Average Period(3)
200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 96MHz nominal 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 96MHz nominal
ns
TABSMIN
Absolute Min Period(2,3)
ns
tR tF d-tR d-tF dT3 tSK3 tJCYC-CYC
Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2) Cycle(2)
VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V
ps ps ps ps % ps ps
Measurement from differential waveform VT = 50% Measurement from differential waveform
45 -- --
Skew(2) Jitter, Cycle to
NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tSK1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Skew(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 33.33MHz output nominal 33.33MHz output spread IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 29.991 29.991 2.4 -- -33 -- 30 -- 1 1 0.5 0.5 45 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 30.009 30.1598 -- 0.55 -- -33 -- 38 4 4 2 2 55 500 250 V/ns V/ns ns ns % ps ps mA V V mA Unit ppm ns
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS, 48MHZ, USB
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 Rise Time(1) Fall Time(1) Duty Cycle(1) Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Min. -- 20.8257 2.4 -- -29 -- 29 -- 1 1 1 1 45 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 20.834 -- 0.55 -- -23 -- 27 2 2 2 2 55 V/ns V/ns ns ns % mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol ppm TPERIOD VOH VOL IOH IOL tR1 tF1 tSK1 dT1 tJCYC-CYC Parameter Long Accuracy(1) Clock Period Output HIGH Voltage(1) Output LOW Voltage(1) Output HIGH Current(1) Output LOW Current(1) Rise Time(1) Fall Time(1) Skew(1) Duty Cycle(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 14.318MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V, VOH at Max. = 3.135V VOL at Min. = 1.95V, VOL at Max. = 0.4V VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 69.827 2.4 -- -33 30 1 1 -- 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. 300 69.855 -- 0.4 -33 38 2 2 500 55 1000 Unit ppm ns V V mA mA ns ns ps % ps
NOTE: 1. This parameter is guaranteed by design, but not 100% production tested.
PCI STOP FUNCTIONALITY
PCI_STOP (Byte 6 bit 3) 1 0 CPU Normal Normal CPU# Normal Normal
If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.
SRC Normal IREF * 6 or float SRC# Normal Low PCIF/PCI 33MHz Low USB 48MHz 48MHz DOT96 Normal Normal DOT96# Normal Normal REF 14.318MHz 14.318MHz
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches.
PD, POWER DOWN
PWRDWN 0 1
CPU Normal IREF * 2 or float
CPU# Normal Float
SRC Normal IREF * 2 or float
SRC# Normal Float
PCIF/PCI 33MHz Low
USB 48MHz Low
DOT96 Normal IREF * 2 or float
DOT96# Normal Float
REF 14.318MHz Low
PD ASSERTION
PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
14
IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to `1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300s of PD deassertion.
tSTABLE <1.8mS PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818 tDRIVE_PWRDWN <300S, <200mV
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IDTCV123 PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDTCV XXX Device Type XX Package X Grade Blank Commercial Temperature Range (0C to +70C) Small Shrink Outline Package
PV
123
Programmable FlexPCTM Clock for P4 Processor
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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