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Logic-Level Gate Drive Advanced Process Technology l Surface Mount (IRL2505S) l Low-profile through-hole (IRL2505L) l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description
l l
HEXFET Power MOSFET
D
IRL2505LPBF IRL2505SPbF (R)
VDSS = 55V RDS(on) = 0.008
PD - 95577
G
ID = 104A
S
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL2505L) is available for lowprofile applications.
D 2 Pak
TO-262
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C V GS EAS IAR EAR dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
104 74 360 3.8 200 1.3 16 500 54 20 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.

Max.
0.75 40
Units
C/W 07/19/04
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1
IRL2505S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V (BR)DSS RDS(on) V GS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 55 1.0 59 Typ. Max. Units Conditions V VGS = 0V, ID = 250A 0.035 V/C Reference to 25C, ID = 1mA 0.008 VGS = 10V, ID = 54A 0.010 VGS = 5.0V, ID = 54A 0.013 VGS = 4.0V, ID = 45A 2.0 V VDS = VGS, ID = 250A S VDS = 25V, ID = 54A 25 VDS = 55V, VGS = 0V A 250 VDS = 44V, VGS = 0V, T J = 150C 100 VGS = 16V nA -100 VGS = -16V 130 ID = 54A 25 nC VDS = 44V 67 VGS = 5.0V, See Fig. 6 and 13 12 VDD = 28V 160 ID = 54A ns 43 RG = 1.3, VGS = 5.0V 84 RD = 0.50, See Fig. 10 Between lead, 7.5 nH and center of die contact 5000 VGS = 0V 1100 pF VDS = 25V 390 = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 104 showing the A G integral reverse 360 S p-n junction diode. 1.3 V TJ = 25C, IS = 54A, VGS = 0V 140 210 ns TJ = 25C, IF = 54A 650 970 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25C, L = 240H RG = 25, IAS = 54A. (See Figure 12) ISD 54A, di/dt 230A/s, VDD V(BR)DSS, TJ 175C
Pulse width 300s; duty cycle 2%. Uses IRL2505 data and test conditions Caculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the package refer to Design Tip # 93-4
** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
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IRL2505S/LPbF
1000
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
100
2.5V
10
10
2.5V 20s PULSE WIDTH T J = 25C
1 10
1 0.1
A
100
1 0.1
20s PULSE WIDTH T J = 175C
1 10
A
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 90A
I D , Drain-to-Source Current (A)
TJ = 25C
100
2.5
TJ = 175C
2.0
1.5
10
1.0
0.5
1 2.5 3.5 4.5
V DS= 25V 20s PULSE WIDTH
5.5 6.5 7.5
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRL2505S/LPbF
10000
8000
VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
15
I D = 54A VDS = 44V VDS = 28V
12
C, Capacitance (pF)
Ciss
6000
9
4000
Coss
6
2000
Crss
A
1 10 100
3
0
0 0 40 80
FOR TEST CIRCUIT SEE FIGURE 13
120 160
A
200
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10s
I D , Drain Current (A)
100 100s
100
TJ = 175C TJ = 25C
1ms 10 10ms
10 0.4 0.8 1.2 1.6 2.0
VGS = 0V
2.4
A
1 1
TC = 25C TJ = 175C Single Pulse
10
A
100
2.8
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRL2505S/LPbF
120
LIMITED BY PACKAGE
100
V GS RG 5.0V
Pulse Width 1 s Duty Factor 0.1 %
D.U.T.
+
ID , Drain Current (A)
-V DD
80
60
40
Fig 10a. Switching Time Test Circuit
VDS 90%
20
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
1
Thermal Response (Z thJC )
D = 0.50
0.20 0.1 0.10 0.05 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t2
0.01 0.00001
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL2505S/LPbF
L VDS D.U.T. RG + V - DD
10 V
EAS , Single Pulse Avalanche Energy (mJ)
1200
TOP
1000
BOTTOM
ID 22A 38A 54A
800
IAS tp
0.01
600
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp VDD VDS
400
200
0
VDD = 25V
25 50 75 100 125 150
A
175
Starting TJ , Junction Temperature (C)
IAS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
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IRL2505S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ V DD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRL2505S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF 530S WIT H LOT CODE 8024 AS S E MBL E D ON WW 02, 2000 IN T H E AS S E MB LY L INE "L" Note: "P" in as s embly line pos ition indicates "Lead-F ree" INT E RNAT IONAL RE CT IF IE R LOGO PART NUMB E R F 530S DAT E CODE YE AR 0 = 2000 WE E K 02 LINE L
AS S E MB LY LOT CODE
OR
INT ERNAT IONAL RECT IF IER L OGO AS S EMB LY LOT CODE PART NUMB ER F 530S DAT E CODE P = DES IGNAT E S LEAD-F REE PRODUCT (OPT IONAL) YEAR 0 = 2000 WEEK 02 A = AS S EMB LY S IT E CODE
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IRL2505S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPL E: T HIS IS AN IRL3103L L OT CODE 1789 AS S E MB L ED ON WW 19, 1997 IN T HE AS S E MB L Y LINE "C" Note: "P" in as sembly line pos ition indicates "L ead-F ree" INT ERNAT IONAL RE CT IF IER L OGO AS S EMB LY L OT CODE PART NUMB ER
DAT E CODE YE AR 7 = 1997 WEE K 19 LINE C
OR
INT E RNAT IONAL RE CT IFIE R L OGO AS S E MBL Y LOT CODE PART NUMBE R DAT E CODE P = DES IGNAT ES L E AD-F RE E PRODUCT (OPT IONAL) YE AR 7 = 1997 WE E K 19 A = AS S E MB L Y S IT E CODE
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9
IRL2505S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197) MAX.
26.40 (1.039) 24.40 (.961) 3
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/04
10
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