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PD - 95203
Generation V Technology Ultra Low On-Resistance l P-Channel Mosfet l Surface Mount l Available in Tape & Reel l Dynamic dv/dt Rating l Fast Switching l Lead-Free Description
l l
HEXFET(R) Power MOSFET
S
1 2 3 4 8 7
IRF7404PBF
A D D D D
S
S G
VDSS = -20V RDS(on) = 0.040
6 5
Top View
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques. Power dissipation of greater than 0.8W is possible in a typical PCB mount application.
SO-8
Absolute Maximum Ratings
Parameter
ID @ TA = 25C ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C VGS dv/dt TJ, TSTG 10 Sec. Pulsed Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range
Max.
-7.7 -6.7 -5.4 -27 2.5 0.02 12 -5.0 -55 to + 150
Units
A W W/C V V/ns C
Thermal Resistance Ratings
Parameter
RJA Maximum Junction-to-Ambient
Typ.
Max.
50
Units
C/W
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1
9/30/04
IRF7404PBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Min. -20 -0.70 6.8
Typ. Max. Units Conditions V V GS = 0V, ID = -250A -0.012 V/C Reference to 25C, ID = -1mA 0.040 V GS = -4.5V, ID = -3.2A 0.060 V GS = -2.7V, ID = -2.7A V V DS = VGS, ID = -250A S V DS = -15V, ID = -3.2A -1.0 V DS = -16V, VGS = 0V A -25 V DS = -16V, VGS = 0V, TJ = 125C -100 V GS = -12V nA 100 V GS = 12V 50 I D = -3.2A 5.5 nC V DS = -16V 21 V GS = -4.5V, See Fig. 6 and 12 14 V DD = -10V 32 I D = -3.2A ns 100 R G = 6.0 65 R D = 3.1, See Fig. 10 2.5 4.0 nH pF
D
Between lead tip and center of die contact V GS = 0V V DS = -15V = 1.0MHz, See Fig. 5
G S
1500 730 340
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units 69 71 -3.1 A -27 -1.0 100 110 V ns C
Conditions D MOSFET symbol showing the G integral reverse p-n junction diode. S TJ = 25C, IS = -2.0A, VGS = 0V TJ = 25C, I F = -3.2A di/dt = 100A/s
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%.
ISD -3.2A, di/dt -65A/s, VDD V(BR)DSS,
TJ 150C
Surface mounted on FR-4 board, t 10sec.
2
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IRF7404PBF
1000
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V TOP
1000
-I D , Drain-to-Source Current (A)
-ID , Drain-to-Source Current (A)
100
100
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V TOP
10
10
-1.5V
1
1
-1.5V
0.1 0.01
20s PULSE WIDTH TJ = 25C A
0.1 1 10 100
0.1 0.01
20s PULSE WIDTH TJ = 150C
0.1 1 10
100
A
-VDS , Drain-to-Source Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
TJ = 25C TJ = 150C
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = -5.3A
-ID , Drain-to-Source Current (A)
1.5
10
1.0
0.5
1 1.5 2.0 2.5 3.0
VDS = -15V 20s PULSE WIDTH
3.5 4.0 4.5 5.0
A
0.0 -60 -40 -20 0 20 40 60 80
VGS = -4.5V
100 120 140 160
A
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7404PBF
3000
-VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
10
I D = -3.2A VDS = -16V
8
C, Capacitance (pF)
2000
Ciss Coss
6
4
1000
Crss
2
0 1 10 100
A
0 0 10 20 30
FOR TEST CIRCUIT SEE FIGURE 12
40 50 60
A
-VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
-I SD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
TJ = 25C
-ID , Drain Current (A) I
TJ = 150C
10
1ms
1
10ms
0.1 0.2 0.4 0.6 0.8 1.0 1.2
VGS = 0V
1.4 1.6
1 0.1
TA = 25 C TJ = 150 C Single Pulse
1 10 100
-V SD , Source-to-Drain Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF7404PBF
8.0
V DS V GS
RD D.U.T.
V + DD
-ID , Drain Current (A)
6.0
RG -4.5V
A
4.0
Pulse Width 1s Duty Factor 0.1%
Fig 10a. Switching Time Test Circuit
2.0
VDS 90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Ambient Temperature
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJA )
D = 0.50 0.20 0.10 0.05 0.02 1 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.01 0.1 1 10 100
10
0.1 0.0001
0.001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7404PBF
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
VG
VGS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
6
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+
QGS
QGD
D.U.T.
-
-4.5 V
VDS
IRF7404PBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG VGS*
**
* dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ -
VDD
*
*
Reverse Polarity for P-Channel ** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive P.W. Period D= P.W. Period VGS=10V
[
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
] ***
Re-Applied Voltage Inductor Curent
[
Body Diode Forward Drop
VDD
]
Ripple 5%
[
ISD
]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 13. For P-Channel HEXFETS
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7
IRF7404PBF
SO-8 Package Outline
Dimensions are shown in milimeters (inches)
D A 5 B
DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMET ERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
c D E e e1 H
1
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
K L y
e1
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
A1 CAB
8X L 7
8X c
NOT ES : 1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010]. 7 DIMENS ION IS T HE LENGT H OF LEAD FOR S OLDERING T O A SUBS T RAT E. 3X 1.27 [.050] 6.46 [.255]
FOOT PRINT 8X 0.72 [.028]
8X 1.78 [.070]
SO-8 Part Marking Information (Lead-Free)
EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) Y = LAST DIGIT OF T HE YEAR WW = WEEK A = AS SEMBLY S IT E CODE LOT CODE PART NUMBER
INT ERNAT IONAL RECT IFIER LOGO
XXXX F 7101
8
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IRF7404PBF
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/04
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