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MGCT04
Transmit Circuit for TDMA/AMPS and CDMA/AMPS Preliminary Information
Features
* * * * * * Dual RF Ports for 900MHz and 1900MHz AGC Amplifier with 90dB of Variable Gain, Fully Compensated for Temperature On-chip Active Filter. Removes the Requirement for External IF SAW Filter High Power 900MHz and 1900MHz Output Stages Quadrature Modulator Small Scale MLF Package
DS5424 ISSUE 1.1 March 2001
Ordering Information MGCT04/KG/LH1S MGCT04/KG/LH1T
Applications
* * Transmit Modulator and Up-converter in TDMA/ AMPS Mobile Phones Transmit Up-converter in CDMA/AMPS Mobile Phones
mobile phones. It can be used for both TDMA/AMPS or CDMA/AMPS systems. The MGCT04 is compatible with baseband and mixed signal interface circuits from Zarlink Semiconductor and other manufacturers. System costs have been kept to a minimum by removing the requirement for an additional SAW filter in the transmit IF path. The AGC has been split between RF and IF sections to reduce noise and a low pass filter has been included before the IF variable gain amplifier to remove spurious products produced in the modulator.
The MGCT04 circuit is designed for use in dual band, dual mode cellular 900MHz/PCS1900MHz
CP2
8
CP1
23
CP0
5
LO 2GHz
19 UHF OSCILLATOR INPUT SELECT
LO 1GHz
21
CONTROL LOGIC
1900 MHz OUTPUT DRIVER
Q IN Q IN
13 14
27 26
POWER CONTROL
RF190 RF190 RFDEG1 RFDEG2 RF900 RF900
/2/4 AND
15 16 PHASE SHIFT
IF VGA
ALL PASS PHASE SHIFT NETWORK
RF VGA 28 1 3 2 SSB MIXER 900 MHz OUTPUT DRIVER
I IN I IN
DIV 7 OUT
VCO BUFFER
/8
OSC BUFFER VREF 9 BIAS BUFFER 10
VGA CONTROL
22
VHF OSC IN
VHF OSC BIAS
AGC
Figure 1 - MGCT04 Block Diagram
1
MGCT04
Preliminary Information
21
15
22
14
28
8
Note: Corner Pads are connected to ground
1
7
Figure 2 - Pin Connections - top view
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Signal Name RF DEG2 RF 900B RF 900 RF GND CP0 VCO GND DIV OUT CP2 VHF OSC IN VHF OSC BIAS VCO VCC GND Q IN Q INB I IN I INB VCC UHF VCC LO 2GHZ GND UHF LO 1GHZ AGC CP1 RF VCC RF GND RF 1900B RF 1900 RF DEG1
Function Connection to external inductor to control gain of power amplifiers Inverse output from 900MHz differential output driver Output from 900MHz differential output driver Ground to RF circuits Control pin 0. See tables 2 & 3 for function Ground for VHF oscillator Output from VHF oscillator divided by 8 Control pin 2. See tables 2 & 3 for function Input from external VHF oscillator Switched bias voltage for external VHF oscillator Positive supply to VHF oscillator Ground Q +input Q -input I +input I -input Positive supply Positive supply to UHF LO input buffers 2GHz local oscillator input Ground to UHF oscillator input buffers 1GHz local oscillator input Control voltage for IF and RF variable gain amplifiers Control pin 1. See tables 2 & 3 for function Positive supply to RF circuits Ground to RF circuits Inverse output from 1900MHz differential output driver Output from 1900MHz differential output driver Connection to external inductor to control gain of power amplifiers
Table 1 - Pin Assignments
2
Preliminary Information
Absolute Maximum Ratings
Supply voltage (VCC) Control input voltage Storage temperature, TSTG 4V -0.6V to VCC + 0.6V -55C to +125C Operating temperature Max Junction Temperature (TJ)
MGCT04
-40C to 100C 150C
Electrical Characteristics
Test conditions (unless otherwise stated): Tamb = -30C to +70C, VCC = 2*7V to 3*6V. UHF LO level = -15dBm (both bands), I, Q input = 1.4 volts p.p, test frequency = 849MHz (900 output) and 1910MHz (1900 output).These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristics Min. Supply current Sleep current Standby mode Standby Mode - Prescaler disabled Total supply current Standby to operating mode switching time Logic inputs Logic high voltage Logic low voltage Typ. Max. 75 10 A mA mA mA s All circuits off See Tables 4 and 5 Pin 7 connected to VCC Maximum power PCS mode Units Conditions
8 4 118
160 10
VCC -0.6 0
VCC 0*8
V V
Table 2 - DC Characteristics
Value Characteristics Min. I and Q modulator I and Q input voltage level I and Q common mode voltage I and Q differential input resistance I and Q input bandwidth IF Vector offset SSB rejection VHF oscillator input and divider Input drive level VHF oscillator bias voltage Output level from prescaler Prescaler divide ratio 400 8 22 40 1.2 70 mVrms V mVpp 6pF load Drive output for synthesiser From external VHF osc. via matching network 13.5 2.5 25 30 1.0 1.4 1.2 2.0 Vpp V k MHz dB dB Pout = +8dBm Pout = + 8dBm Differential Typ. Max. Units Conditions
Table 3 - AC Characteristics
3
MGCT04
Preliminary Information
Value
Characteristics Min. Variable gain amplifiers IF amp. operating frequency range RF amp. operating frequency range Overall gain control range Control voltage for minimum gain Control voltage for maximum gain AGC control voltage slope SSB mixer and UHF oscillator inputs Cellular band LO input level PCS band LO input level Cellular band local oscillator input frequency. (LO 1GHz) PCS band local oscillator input frequency (LO 2GHz) 900MHz RF output stage -15 -15 850 1500 -10 -10 -5 -5 1100 2150 33 50 750 84 0.1 2.6 60 90 200 2000 Typ. Max.
Units
Conditions
MHz MHz dB V V dB/V Voltage gain
dBm dBm MHz MHz
From external UHF osc. via matching network From external UHF osc. via matching network
Specifications assume 50 ohm load driven via a matching network (Fig. 6) 824 +8 -66 -45 -90 849 +19 -52 -30 -60 +14 -128 -123 121 +19 MHz dBm dBc dBc dBc dBm dBm/ Hz dBm/ Hz Note 1 Pout = +3dBm Vcc = 3V Pout = +8dBm, Offset = 30kHz Vcc = 3V Pout = +8dBm, Offset = 60kHz Vcc = 3V Note 2 At duplex frequency, offset 45MHz Pout = +3dBm ftx = 849 MHz Pout = +8dBm
RF amplifier operating frequency range Output power ACPR (CDMA) ACPR (TDMA)
Output power AMPS Receive band noise Receive band noise (869 - 894MHz) Spurious Outputs LO Leakage Image Rejection Other Spurii
+10
-30 -30
-20 -20 -20
dBc dBc dBm
Pout = +8dBm Pout = +8dBm Note 3
Table 3 - AC Characteristics (continued)
4
Preliminary Information
Value Characteristics Min. 1900MHz RF output stage (PCS) Typ. Max. Units
MGCT04
Conditions Specifications assume 50 ohm load driven via a matching network (Fig. 5)
RF amplifier operating frequency range Output power ACPR (CDMA) ACPR (TDMA)
1850 +8 -66 -45 -90
1910 +18 -52 -30 -60 -128 -123 -121
MHz dBm dBc dBc dBc dBm/ Hz dBm/ Hz Note 1 Pout = +3dBm Vcc = 3V Pout = +8dBm, Offset = 30kHz Vcc = 3V Pout = +8dBm, Offset = 60kHz Vcc = 3V At duplex frequency, offset 80MHz Pout = +3dBm ftx = 1910MHz, Pout = +8dBm
Receive band noise Receive band noise (1930 - 1990 MHz) Spurious Outputs LO Leakage Image Rejection Other Spurii
-30 -30
-20 -20 -20
dBc dBc dBm
Pout = +8dBm Pout = +8dBm Note 3
Table 3 - AC Characteristics (continued)
Notes: 1. V (I/Q) = 1.4V differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6volts 2. V (I/Q) = 1.4 V dc differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6 volts 3. Frequency range 10MHz to 10*ftx except Rx and Tx bands
Circuit Description General
The MGCT04 circuit is designed to provide the transmit function in dual band dual mode CDMA/ AMPS IS136/AMPS mobile phones. The circuit contains the following blocks: 1. Quadrature modulator 2. VHF voltage controlled oscillator buffer and divide by 8 prescaler 3. Active IF low pass filter 4. IF variable gain amplifier 5. Single sideband mixer with external UHF oscillator inputs 6. RF variable gain amplifier 7. 900MHz and 1900MHz high power output driver stages 8. Power and mode control logic
is applied to the I and Q inputs of the quadrature modulator to produce the intermediate frequency by mixing with the local oscillator frequency from the VHF VCO. The control inputs can select either a divide by two or divide by four function between the VHF VCO and the quadrature modulator giving a choice of possible intermediate frequencies.
VHF Oscillator Input Oscillator Bias and Divider
An external VHF oscillator circuit is AC coupled to the VHF oscillator input. The oscillator drives the quadrature modulator and an internal divide by eight circuit to reduce the frequency of the output signal to be sent off chip to the frequency synthesiser. This reduces the power required in the output buffer circuit and also allows a low frequency low power CMOS synthesiser to be used. The divider can be disabled if not required by connecting the output pin (DIV OUT - pin 7) to the positive power supply. This reduces the total supply current by typically 4mA. An oscillator bias circuit is included on the chip so that the external VHF oscillator transistor can be switched off using the control inputs. The bias voltage is
5
Quadrature Modulator
I and Q data from a baseband circuit such as the Zarlink Semiconductor MGCM02 or MGCM03 circuit
MGCT04
Preliminary Information
filter to be used for both 900MHz and 1900MHz bands.
switched off in either of the sleep conditions shown in Tables 4 and 5.
Active Low Pass Filter
The output from the quadrature modulator is passed to the active low pass filter which attenuates wide band noise and spurious outputs.
RF Variable Gain Amplifier
The SSB mixer is followed by the RF variable gain amplifier stage which provides about 23dB of the total gain variation. An additional SAW filter in the transmit path is avoided by providing the gain variation after the mixer. The variable gain amplifier control circuit ensures that the attenuation from maximum power is initially controlled by the RF variable gain stage thus reducing the noise contribution from the RF mixer.
IF Variable Gain Amplifier
The filtered IF signal is passed to the IF variable gain amplifier which in turn drives the single sideband mixer. An externally applied AGC control voltage allows the total circuit gain to be varied over a minimum 84dB range. The AGC action is split between the IF and RF portions of the circuit and an internal AGC control circuit processes the external AGC control voltage to drive both IF and RF variable gain amplifiers and provides a near linear control characteristic over the entire AGC range.
Output Drivers
Separate output drive stages are provided for 900MHz and 1900MHz operation. A differential design is used for both amplifiers to improve power efficiency and to ease power supply decoupling problems. The 900MHz output stage provides a linear output of 3 to 5 dBm for CDMA and 8 dBm for TDMA operation, but is over-driven in AMPS mode to obtain a typical output of 11dBm. In both power driver stages the DC current is backed off as the RF and IF gain is reduced, improving efficiency when less than maximum output power is required.
Single Sideband Mixer
The modulated IF signal is fed to the single sideband mixer which up-converts the IF to the RF frequency to be transmitted by mixing with an RF signal from one of two external UHF oscillator input pins, seiected by an on chip multiplexer. When 1900MHz mode is programmed with the VHF oscillator in divide by four mode (Tables 4 and 5), the polarity of the quadrature oscillator drive signals to the single sideband mixer are reversed, thus selecting a low side LO for 1900MHz PCS and high side for 900MHz. This technique allows a common IF and CP2 0 0 0 0 CP1 0 0 1 1 CP0 0 1 0 1
Control Inputs
Three control inputs are provided to select different operating modes for the chip; the various modes selected by the control pins are shown in Tables 4 and 5.
Function Sleep mode. All circuits powered down Quadrature modulator on. 1900MHz mode. Low side UHF LO. IF = VHF VCO / 4 Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO / 4 Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other circuits powered down
Table 4 - Control pin functions; VHF LO in divide-by-four mode
CP2 1 1 1 1 CP1 0 0 1 1 CP0 0 1 0 1 Function Sleep mode. All circuits powered down Quadrature modulator on. 1900MHz mode. High side UHF LO. IF = VHF VCO / 2 Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO / 2 Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other circuits powered down
Table 5 - Control pin functions; VHF LO in divide-by-two mode
6
Preliminary Information
VCC VCC INPUT 800k VREF 1.2V 400k 600 OSC BIAS 2.5mA 1.85k 1.85k
MGCT04
VCC
DIV OUT 0.5mA
Figure 3a - Control inputs CP0, CP1 and CP2
VCC
Figure 3b - Oscillator bias buffer
Figure 3c - Divider ouput circuit
VCC
550 2.7k 2.7k VBIAS 10k VHF OSC INPUT 4p 540A 1.6mA 10k LO2GHz LO1GHz 4k5 100 100
550 VOUT- VOUT+ VBIAS 4k5
Figure 3d - VHF oscillator input buffer
RF900
Figure 3e - LO2GHz and LO1GHz oscillator inputs
RF1900
V CC
RF900
VCC
RF1900
VBIAS
VBIAS
RFDEG2 RFDEG1
Figure 3f - 900MHz and 1900MHz outputs
10k I IN/Q IN VCC 80k TO QUAD MOD AGC IN 27k 80k I IN/Q IN 10k TO QUAD MOD 44k VBIAS 2 2.0p
VCC 27k VBIAS 1
Figure 3g - I and Q inputs
Figure 3h - AGC input
7
MGCT04
Preliminary Information
1900MHz power amplifier
1GHz LO 1900MHz SAW filter 1900MHz matching network Vcc CONTROL MICROPROCESSOR
2GHz LO
1900MHz diplexer
AGC
900MHz diplexer 900MHz power amplifier 900MHz SAW filter Oscillator control
900MHz matching network
1
28
22 21
External VHF oscillator
MGCT04
7 8 15 14
VHF SYNTHESISER Oscillator out
MIXED SIGNAL INTERFACE CIRCUIT
Oscillator bias Vee
Figure 4 - Typical application circuit
VCC 50 SAW FILTER 50 SAW FILTER PIN 27 L5 5.6n C4 1.2p L4 5.6n L3 3.9n PIN 26 C2 1.2p C4 1.5p C2 100p L5 22n L4 22n
VCC
C3 1.2p
C1 1.2p
L1 15n
L2 15n
C3 1.5p
C1 100p
L1 68n L3 22n
L2 68n PIN 3
PIN 2
NOTE L1 and L2 are required to provide a DC feed to the output pins and do not form part of the matching network
NOTE L1 and L2 are required to provide a DC feed to the output pins and do not form part of the matching network
Figure 5 - Typical 1900MHz output matching network
Figure 6 - Typical 900MHz output matching network
8
Preliminary Information
MGCT04
MGCT04
VCO control voltage
Frequency Synthesizer
VHF OSC IN (9) VHF OSC BIAS (10) DIV OUT (7)
Vee
Figure 7 - Typical circuit showing connection of external VHF oscillator
10n
68p
3n3
5p6
2n2
Pin 21
2p
Pin 19
a) UHF LO 1GHz
b) UHF LO 2GHz
4n7
39n Pin 9 8P
Note: Test signal generator impedance is 50 ohms in each case
c) VHF LO
Figure 8 - LO Input Test Circuits
9
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