View HV7151SP_648810.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
CMOS Image Sensor with Image Signal Processing HV7151SP
Hynix Semiconductor Inc.
Preliminary Release Version 0.7
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -12003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Revision History
Revision 0.0 0.1 0.2 0.5 0.6 0.7 Script Date 2003-June 2003-June 2003-July 2003-August 2003-November 2004-January Comments HV7151SP Preliminary is released HV7151SP version 0.1 is released HV7151SP version 0.2 is released HV7151SP version 0.5 is released Frame rate Calculation is added ENB Setting Guide Information and Recommend Circuit Information is Added
Copyright by Hynix Semiconductor Inc., all right reserved 2003
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -22003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Contents
General Description ....................................................................................................................5 Features ....................................................................................................................................5 Block Diagram ...........................................................................................................................6 Pixel Structure ...........................................................................................................................7 Pin Diagram...............................................................................................................................8 Pin Diagram...............................................................................................................................9 Functional Description .............................................................................................................. 10 Pixel Architecture .............................................................................................................. 10 Sensor Imaging Operation .................................................................................................. 10 On-chip Frequency Synthesizer .......................................................................................... 11 11bit on-chip ADC.............................................................................................................. 11 Gamma Correction............................................................................................................. 11 Color Interpolation.............................................................................................................. 12 Sub-sampling Mode ........................................................................................................... 12 Scaling Mode .................................................................................................................... 12 Color Correction................................................................................................................. 12 Color Space Conversion & Reverse Color Space Conversion .................................................. 13 Luminance Processing - Contrast, Brightness adjustment .................................................... 14 Chrominance Processing - Saturation adjustment ................................................................ 14 Edge Enhancement ........................................................................................................... 14 Chroma Suppression.......................................................................................................... 14 Automatic Flicker Cancellation............................................................................................ 14 Output Formatting.............................................................................................................. 15 Auto Exposure Control ....................................................................................................... 15 Auto White Balance........................................................................................................... 15 Register Description ................................................................................................................. 16 Anti-Banding Configuration ........................................................................................................ 60 Frame Timing........................................................................................................................... 60 Output Data according to Video Mode ........................................................................................ 66 Bayer Data Format ................................................................................................................... 79 I2C Chip Interface..................................................................................................................... 80 AC/DC Characteristics.............................................................................................................. 82 Electro-Optical Characteristics .................................................................................................. 85 This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -32003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Package information ................................................................................................................. 86 Reference Circuit Information ..................................................................................................... 88 MEMO .................................................................................................................................... 89
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -42003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
General Description
HV7151SP is a highly integrated single chip CMOS color image sensor implemented by proprietary Hynix 0.18um CMOS sensor process realizing high sensitivity and wide dynamic range. Active pixel array is 1164x886. Each active pixel composed of 4 transistors, it has a micro-lens to enhance sensitivity, and converts photon energy to analog pixel voltage. On-chip 11bit Analog to Digital Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. The integration of sensor function and image processing functions make HV7151SP especially very suitable for mobile imaging systems such as digital still camera, PC input camera and IMT-2000 phone's video part that requires very low power and system compactness.
Features
n n n Optical Format : 1/4 inch / Pixel Size : 3.2m x 3.2m Active Pixel Array : 1170 x 886 Multiple Video Modes : 1152x864(MEGA), 640x480(VGA), 576x432(1/4 MEGA), 352x288(CIF), 320x240(QVGA), 288x216(1/16 MEGA), 176x144(QCIF) n n n n n n n n n n n n Bayer RGB Color filter array / Micro-lens for high sensitivity
On-chip Frequency Synthesizer On-chip 11 bit Analog to Digital Converter Correlated Double Sampling (CDS) for reduction of Fixed Pattern Noise (FPN) Automatic Flicker Cancellation (AFC) Automatic Black Level Calibration (ABLC) Gamma Correction by programmable piecewise linear approximation 5x5 Color Interpolation Color Correction by programmable 3x3 matrix operation Color Space Conversion from RGB to YCbCr and Reverse Conversion from YCbCr to RGB Image adjustment :Contrast, Brightness, Saturation, Edge Enhancement, Chroma Suppression Various Output Formats: CCIR-601, CCIR-656 Compatible YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, RGB 565, Bayer
n n n
8bit/16bit Data Bus Mode Automatic Exposure Control and Automatic White Balance Control Power Save Mode
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -52003 Hynix Semiconductor Inc.
Confidential
n n n
HV7151SP CMOS Image Sensor With Image Signal Processing
Typical Supply Voltage: Internal 1.8V and I/O 2.5V Operation Temperature : -10 ~ +50 degrees Celsius Package Types: CLCC 40 PIN, COB(Chip-on-Board), COF(Chip-on-Flex)
Block Diagram
Pixel Array 1170x886
RESETB MCLK ENB Timing Control Config Registers I2C Slave SCK SDA
Analog Signal Processing
11bit ADC
Digital Signal Processing
VCLK VSYNC HSYNC Y[7:0] C[7:0]
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -62003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Pixel Structure
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -72003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Pin Diagram
DGNDI 4 DVDDI 5 DVDDC DGNDC C[7] C[6] 6 7 8 9 Y[0] 3 Y[1] 2 Y[2] 1 Y[3] 40 Y[4] Y[5] Y[6] Y[7] 35 DGNDI 34 DVDDIH 33 MCLK 32 VCLK
39 38 37 36
C[5] 10 C[4] 11
HV7151SP
CLCC 40 PIN Top View
31 HSYNC 30 VSYNC 29 AINP 28 AINN 27 AVDD 26 AGND
C[3] 12 C[2] 13 C[1] 14 C[0] 15 16 DVDDIH 17 18 19 DGNDIH SDA SCK
20 STROBE
21 22 23 24 25 RESETB ENB DGNDI DVDDI AVDDH
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -82003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Pin Diagram
C[7:0] should be set up as pull-up or pull-down when 8bit output mode is used. Pin 36-40, 1-3 4 5 6 7 8-15 16 17 18 19 20 21 22 Type B G P P G B PH G B I O I I Symbol Y[7:0] DGNDI DVDDI DVDDC DGNDC C[7:0] DVDDIH DGNDIH SDA SCK STROBE RESETB ENB Description Video Luminance Data[7:0] Digital Ground for I/O Driver 1.8V Digital Power for I/O Driver 1.8V Power for Internal Digital Block Ground for Internal Digital Block Video Chrominance Data[7:0] 2.5V Digital Power for I/O Driver Digital Ground for I/O Driver I2C Standard data I/O port I2C Clock Input Strobe Signal Output Sensor Reset, Low Active Sensor sleep mode is controlled externally by this pin when sleep mode register bit is low. ENB low : sleep mode, ENB high : normal mode 23 24 25 26 27 28 29 30 G P PH G P AI AI B DGNDI DVDDI AVDDPH AGND AVDD AINN AINP VSYNC Digital Ground for I/O Driver 1.8V Digital Power for I/O Driver 2.5V Analog Power for Pixel Block Analog Ground for Analog Block 1.8V Power for Internal Analog Block Analog Input Minus for Test ADC Analog Input Plus for Test ADC Video Frame Synchronization signal. VSYNC is active at start of image data frame. 31 B HSYNC Video Horizontal Line Synchronization signal. Image data is valid, when HSYNC is high. 32 33 34 35 B I PH G VCLK MCLK DVDDIH DGNDI Video Output Clock Master Input Clock 2.5V Digital Power for I/O Driver Digital Ground for I/O Driver
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. -92003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Functional Description
Pixel Architecture
Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved.
ENB Setting guide information for normal stand-by mode
It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7151SP after system power on
System power On More than 4cycle
Sensor operation sequence
Sensor Power down sequence
DVDD/AVDD
RESETB
Low
MCLK
Low 1' VSYNC out st
VSYNC
Low 2.56 [ Mcycle] for 1'st VSYNC out
ENB
Low 2.68 [ Mcycle for logic stable time ] 1ms
I2C Video stream Don't care Initialization sequence Don' care t Camera Mode
ex) If MCLK = 19.2[Mhz] and PLL 2x, => 2.68[Mcycle] / 38.4[MHz] = 69.79 ms The time period of ENB high value have to keep for 69.79[ms] or more
Sensor Imaging Operation
Imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 10 2003 Hynix Semiconductor Inc.
Confidential
Time
HV7151SP CMOS Image Sensor With Image Signal Processing
Integration Plane Frame 0 Scan Integration Plane Frame 1 Scan Plane Frame 1 Plane Frame 0
Integration Time
Frame 0 Time
Frame 1 Time
On-chip Frequency Synthesizer
On-chip Frequency Synthesizer generates variable frequency according to the proportion of Reference(PREFDIV) to Feedback(PFDDIV) Divisor. Operating frequency is fully programmable and output range is 5MHz to 100MHz.
11bit on-chip ADC
On-chip ADC converts analog pixel voltage to 11bit digital data.
Gamma Correction
Piecewise linear approximation method is implemented. Ten piece linear segments are supported and user-programmable.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 11 2003 Hynix Semiconductor Inc.
Confidential
Out Start 9 : :
HV7151SP CMOS Image Sensor With Image Signal Processing
Start 2
Start 1 Start 0 0 8 3 2 64 128 256 384 512 1024 1536 2047 In
G a m m a Transfer Function
Color Interpolation
5x5 linear color interpolation is used to interpolate missing R, G, or B for mosaic image data from pixel array. Interpolation is done by moving 5x5 interpolation window by one pixel horizontally and vertically.
Sub-sampling Mode
The sub-sampling modes such as 1/4 sub-sampling and 1/16 sub-sampling are supported. The subsampling sequence is as below. For example 1/4 sub-sampling, Row data are picked out from R,G,B bayer raw data by the rate of four to two. And after 5x5 linear color interpolation, column data also are picked out the rate of two to one. 1/16 sub-sampling is similar to 1/4 sub-sampling.
Scaling Mode
In addition to the sub-sampling mode, HV7151SP supports the scaling modes, such as 5/9 scaling VGA, 5/18 scaling QVGA, 1/3 scaling CIF and 1/6 QCIF. Because HV7151SP normal image size(1152x864) is not a multiple proportion of VGA/QVGA or CIF/QCIF image size, output data and output clock of scaling mode are asymmetry.
Color Correction
Generally, the color spread effect is mainly caused by color filter characteristics. The effect is compensated by 3x3 color correction operation. Color correction matrix may be resolved by measuring sensor' color spread characteristics for primary color source and calculating the inverse s This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 12 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
matrix of color spread matrix. Nine registers for matrix coefficients are used in color correction operation to get the optimal pure color. The relationship between input color and color-corrected color is defined as below formula.
R G = B
where
CRCM 11 CRCM 12 CRCM 13 R CRCM 21 CRCM 22 CRCM 23 * G CRCM 31 CRCM 32 CRCM 33 B
R,G,B = Sensor color output R' ,B' = Color-corrected output ,G'
Coefficients CRCMxx are programmable from -127/64 ~ 127/64. Programming register value for intended color correction matrix coefficients should be resolved by the following equations. For positive values, CRCMxx = Integer(Real Coefficient Value x 64); For negative values, CRCMxx = Two' Complement(Integer(Real Coefficient Value x 64)); s Real Coefficient Value values from -127/64 ~ 127/64 can be programmed.
Color Space Conversion & Reverse Color Space Conversion
Both of color space conversion and reverse color space conversion are implemented by 3x3 matrix operation. Output ranges of color space conversion and reverse conversion are existed two modes. One is 16 Y 235, 16 Cb,Cr 240 & 16 reverse-R,G,B 235 and Another is 0 Y,Cb,Cr 255 & 0 reverse-R,G,B 255. These different modes are selected by control register. For color space conversion and reverse conversion matrix, the equation from CCIR-601 standard is normally used.
< Conversion Equation > Mode 1 :
0.587 0.114 R 0 Y 0.299 Cb = - 0.169 - 0.331 0.500 * G + 128 Cr 0.500 - 0.419 - 0.081 B 128
Range : 0 ~ 255 Range : 0 ~ 255 Range : 0 ~ 255
Mode 2 :
0.504 0.098 R 16 Y 0.257 Cb = - 0.148 - 0.291 0.439 * G + 128 Cr 0.439 - 0.368 - 0.071 B 128
Range : 16 ~ 235 Range : 16 ~ 240 Range : 16 ~ 240
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 13 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
In the above equations, R, G, and B are gamma-corrected values. < Reverse Conversion Equation >
R 1.402 G = - 0.714 B 0
1 1 1
Cr - 128 - 0.344 * Y 1.772 Cb - 128 0
Range : 0 ~ 255 or 16 ~ 235 Range : 0 ~ 255 or 16 ~ 235 Range : 0 ~ 255 or 16 ~ 235
Same matrix equations are applied to mode1 and mode2 in the reverse color space conversion. And previously, output ranges 0 ~ 255 or 16 ~ 235 are decided by input ranges of Y,Cb,Cr.
Luminance Processing - Contrast, Brightness adjustment
For contrast adjustment, Y digital channels are scaled by the contrast factor. Contrast factor resolution is 1/128 and its range is 0 ~ 255/128. For brightness adjustment, there is added a brightness factor to Y digital channels. Brightness factor range is -128 ~ 127 and register value for brightness adjustment is following below. For positive values, Brightness factor = Integer; For negative values, Brightness factor = Two' Complement(Integer); s For example, if brightness factor is 3, register value is 8h03 and if brightness factor is -3, register ' value is 8' hfd.
Chrominance Processing - Saturation adjustment
For saturation adjustment, Cb,Cr digital Channels are scaled by the saturation factor. Saturation factor resolution is 1/128 and its range is 0 ~ 255/128.
Edge Enhancement
Edge enhancement is performed for increasing sharpness of image. Edge weight factor is userprogrammable and its range is 0.3 ~ 1.0.
Chroma Suppression
Chroma suppression is performed in the dark environment for suppressing the color and decreasing dark bad pixel effect. Suppression level is varied in accordance with amplifier gain and saturation level is user-programmable.
Automatic Flicker Cancellation
Banding noise, caused by difference between frequency of light sources and frequency of integration time of pixel, is always generated in CMOS image sensor. For Automatic Flicker Cancellation, integration time is adjusted automatically in accordance with frequency of light sources. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 14 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Output Formatting
The output formats such as YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, RGB 5:6:5 and Bayer Raw Data are supported. Possible output bus widths are 8 bits and 16bits, and the sequence of Cb and Cr or R and B are programmable. The output formats are compatible with Recommendation CCIR-601, CCIR656.
Auto Exposure Control
Y mean value is continuously calculated every frame, and the integration time or amp gain value are increased or decreased according to difference between target Y mean value and current frame Y mean value.
Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 15 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Register Description
Addres s (Hex) DEVID SCTRA SCTRB SCTRC RSAU RSAL CSAU CSAL WIHU WIHL WIWU WIWL HBLU HBLL VBLU VBLL RGAIN GGAIN BGAIN AMPGAIN AMPMIN AMPMAX AMPNOM AMPBIAS RSTCLMP 00 01 02 03 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C Default Description (Hex) 50 13 00 01 00 02 00 02 03 60 04 80 00 D0 00 08 08 08 08 08 10 28 18 13 07 Device ID Sensor Control A Sensor Control B Sensor Control C Row Start Address Upper Row Start Address Lower Column Start Address Upper Column Start Address Lower Window Height Upper Window Height Lower Window Width Upper Window Width Lower Horizontal Blank Time Upper Horizontal Blank Time Lower Vertical Blank Time Upper Vertical Blank Time Lower Red Color Gain Green Color Gain Blue Color Gain Amp Gain for Pixel Output Amp Gain Minimum Value Amp Gain Maximum Value Amp Gain Normal Value CDS Bias , Amplifier Bias Reset Level Clamp Enable, Reset Value
Symbol
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 16 2003 Hynix Semiconductor Inc.
Confidential
ADCBIAS OREDI OGRNI OBLUI BLKTH ISPFUN OUTFMT OUTINV EDGEWT CRCM11 CRCM12 CRCM13 CRCM21 CRCM22 CRCM23 CRCM31 CRCM32 CRCM33 GMAP0 GMAP1 GMAP2 GMAP3 GMAP4 GMAP5 GMAP6 GMAP7 GMAP8 GMAP9 GMAS0 GMAS1 20 21 22 23 27 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 40 41 42 43 44 45 46 47 48 49 50 51 2 7F 7F 7F FF FF 31 00 02 4C EC 08 F0 76 DB FE E8 5A 00 04 1C 34 54 78 90 A4 E0 F4 40 80 ADC Bias Control
HV7151SP CMOS Image Sensor With Image Signal Processing
ADC Initial Offset Value for Optical Black Red ADC Initial Offset Value for Optical Black Green ADC Initial Offset Value for Optical Black Blue Black Level Threshold Value Image Signal Processing Functions Enable Image Data Output Format Output Signal Inversion Edge Enhancement Weight Color Correction matrix coefficient 11 Color Correction matrix coefficient 12 Color Correction matrix coefficient 13 Color Correction matrix coefficient 21 Color Correction matrix coefficient 22 Color Correction matrix coefficient 23 Color Correction matrix coefficient 31 Color Correction matrix coefficient 32 Color Correction matrix coefficient 33 Start point for gamma line segment 0 Start point for gamma line segment 1 Start point for gamma line segment 2 Start point for gamma line segment 3 Start point for gamma line segment 4 Start point for gamma line segment 5 Start point for gamma line segment 6 Start point for gamma line segment 7 Start point for gamma line segment 8 Start point for gamma line segment 9 Slope value for gamma line segment 0 Slope value for gamma line segment 1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 17 2003 Hynix Semiconductor Inc.
Confidential
GMAS2 GMAS3 GMAS4 GMAS5 GMAS6 GMAS7 GMAS8 GMAS9 BRIGHTY SATCR SATCB EDTHLO EDTHHI CHSUPFNC AEMODE1 AEMODE2 CSCMODE INTH INTM INTL AETRGT AELFBND AEULBND ASFCON AESTEPH AESTEPM AESTEPL AEINTH AEINTM 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 60 40 24 18 14 0F 05 02 00 80 80 05 80 64 BD 5D 00 13 88 00 70 A2 2A 00 02 EE 00 3A 98
HV7151SP CMOS Image Sensor With Image Signal Processing
Slope value for gamma line segment 2 Slope value for gamma line segment 3 Slope value for gamma line segment 4 Slope value for gamma line segment 5 Slope value for gamma line segment 6 Slope value for gamma line segment 7 Slope value for gamma line segment 8 Slope value for gamma line segment 9 Brightness factor for brightness adjustment Saturation factor for Saturation adjustment Saturation factor for Saturation adjustment Edge Enhancement Vth Low Edge Enhancement Vth High Chroma Suppression Function Auto Exposure Control Mode 1 Auto Exposure Control Mode 2 Color Space Conversion Mode Select Integration Time High Integration Time Middle Integration Time Low Luminance Target Value Y frame mean value displacement boundary Y frame mean value displacement from AE target where AE update speed transits from 2x integration unit speed to 1x integration unit speed AE Speed and Frame Control AE Anti-Banding Step High AE Anti-Banding Step Middle AE Anti-Banding Step Low AE Integration Time Limit High AE Integration Time Limit Middle
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 18 2003 Hynix Semiconductor Inc.
Confidential
AEINTL AWBMODE1 AWBMODE2 CBTRGT CRTRGT AWBLBND AWBULBND AWBWBND AESTAT AWBSTAT LUMEAN CBMEAN CRMEAN BNDGMIN BNDGMAX AWBWHT AWBBLK AWBVALID DPCMODE DPCINTVALH DPCINTVALM DPCINTVALL DPCGTH DPCCTH DPCGAINVAL CONTY PCTRA PCTRB PFDDIVH 6F 70 71 73 74 75 76 77 7B 7C 7D 7E 7F 80 81 8A 8B 8C 90 91 92 93 94 95 96 97 A0 A1 A4 00 41 02 80 80 02 06 30 RO RO RO RO RO 08 18 C8 0A 02 01 29 DA 49 20 20 38 80 01 1D 00 AE Integration Time Limit Low
HV7151SP CMOS Image Sensor With Image Signal Processing
Auto White Balance Control Mode 1 Auto White Balance Control Mode 2 Cb Frame Mean Value for AWB. Cr Frame Mean Value for AWB. Cb, Cr Frame Mean Displacement from Cb Target and Cr Target where AWB goes into LOCK state Displacement from ideal white pixel where AWB release from LOCK state Displacement from ideal white pixel where AWB recognizes a pixel as a white pixel affected by light source Current AE Operation Status Current AWB Operation Status Active Y Frame Mean Value Active Cb Frame Mean Value Active Cr Frame Mean Value Minimum gain value with Anti-Banding enabled Maximum gain value with Anti-Banding enabled During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is larger than this register value. During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is smaller than this register value. AWB update when the number of valid color pixel is larger than (this minimum value x 64) Dark Bad Pixel Concealment Mode selection Integration Time Value High Byte where filtering operation gets active when dark bad pixel Concealment mode is enabled. Integration Time Value Middle Byte where filtering operation gets active when dark bad pixel Concealment mode is enabled. Integration Time Value Lower Byte where filtering operation gets active when dark bad pixel Concealment mode is enabled. Neighbor-differential threshold value that specify G dark bad pixel Neighbor-differential threshold value that specify R/B dark bad pixel Reference of Amp Gain which Dark Bad Pixel Concealment mode is enabled or disabled Contrast factor for Contrast Adjustment PLL Control Mode A PLL Control Mode B PLL Feedback Divisor High
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 19 2003 Hynix Semiconductor Inc.
Confidential
PFDDIVL PXNUMH PXNUML STTHVAL CHTHVAL AFCMODE INTEGT50H INTEGT50M INTEGT50L INTEGT60H INTEGT60M INTEGT60L A5 B9 BA BB BC BD C0 C1 C2 C3 C4 C5 02 04 00 30 20 00 02 EE 00 02 71 00 PLL Feedback Di visor Low Pixel Number High Pixel Number Low Stable Range Variation Frequency Change Variation AFC Mode Control 50Hz Integration Time High 50Hz Integ ration Time Middle 50Hz Integration Time Low 60Hz Integration Time High 60Hz Integration Time Middle 60Hz Integration Time Low
HV7151SP CMOS Image Sensor With Image Signal Processing
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 20 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Device ID [DEVID : 00h : 50h]
7 6 5 4 3 2 1 0
Product ID 0 1 0 1 0
Revision Number 0 0 0
High Nibble represents Sensor Resolution, Low Nibble represents Revision Number.
Sensor Control A [SCTRA : 01h : 13h]
7 6 5 4 3 2 1 0
Reserved 0 0 0
X-Flip 1
Y-Flip 0 0
Video Mode 1 1
X-Flip Y-Flip
Image is horizontally flipped Image is vertically flipped 111 110 101 100 1/6 scaling QCIF mode 1/3 scaling CIF mode 5/18 scaling QVGA mode 5/9 scaling VGA mode 5x5 linear color interpolation mode 1/4 sub-sampling mode 1/16 sub-sampling mode Bayer output mode
Video Mode 011 010 001 000
Sensor Control B [SCTRB : 02h : 00h]
7 6 5 4 3 2 1 0
AE/AWB Block Sleep 0
Datapath Block Sleep 0
Analog Block Sleep 0
Sleep Mode
Strobe Enable
Clock Division
0
0
0
0
0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 21 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE/AWB Block Sleep Datapath Block Sleep
AE/AWB block goes into sleep mode with this bit set to high. Image processing datapath block goes into sleep mode with this bit set to high.
Analog Block Sleep
all internal analog block goes into sleep mode with this bit set to high. With All Digital Block Sleep active, sensor goes into power down mode.
Sleep Mode Strobe Enable
all internal digital and analog block goes into sleep with this bit set to high. When strobe signal is enabled by this bit, STROBE pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image.
Clock Division
divides input master clock(IMC) for internal use. Internal divided clock frequency(DCF) is defined as master clock frequency(MCF) divided by specified clock divisor. Internal divided clock frequency(DCF) is as follows. 000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8
100 : MCF/16, 101 : MCF/32, 110 : MCF/64, 111 : MCF/128
Sensor Control C [SCTRC : 03h : 01h]
7 6 5 4 3 2 1 0
reserved
HSYNC in VBLANK
VBLANK Unit
Unified Gain
Black Level Data Enable
Black Level Compensation
0
0
0
0
0
0
0
1
HSYNC in VBLANK 0 : There are no valid HSYNC during valid VBLANK. 1 : There are valid HSYNC during valid VBLANK. At time, VBLANK unit must be Line unit.
VBLANK
HSYNC
VBLANK unit 0 : Line unit. VBLANK unit is based on multiple line period time of sensor. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 22 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
1 : Pixel unit. VBLANK unit is based on multiple pixel clock period time of sensor.
Unified Gain 1 : G analog gain is used for R,G and B analog gain. 0 : R,G and B analog gain is used individually.
Black Level Data Enable HSYNC is generated for light-shielded pixels in 4 lines.
Black Level Compensation Black level average values of light-shielded pixels are compensated when active image data is produced.
Row Start Address Upper [RSAU : 08h : 00h]
7 6 5 4 3 2 1 0
Reserved
Row Start Address Upper
0
0
0
0
0
0
0
0
Row Start Address Lower [RSAL : 09h : 02h]
7 6 5 4 3 2 1 0
Row Start Address Lower 0 0 0 0 0 0 1 0
Row Start Address register defines the row start address of image read out operation.
Column Start Address Upper [CSAU : 0ah : 00h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0
Column Start Address Upper 0 0 0
Column Start Address Lower [CSAL : 0bh : 02h]
7 6 5 4 3 2 1 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 23 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Column Start Address Lower 0 0 0 0 0 0 1 0
Column Start Address register defines the column start address of image read out operation.
Window Height Upper [WIHU : 0ch : 03h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0 0
Window Height Upper 1 1
Window Height Lower [WIHL : 0dh : 60h]
7 6 5 4 3 2 1 0
Window Height Lower 0 1 1 0 0 0 0 0
Window Height register defines the height of image to be read out.
Window Width Upper [WIWU : 0eh : 04h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0 1
Window Width Upper 0 0
Window Width Lower [WIWL : 0fh : 80h]
7 6 5 4 3 2 1 0
Window Width Lower 1 0 0 0 0 0 0 0
Window Width Address register defines the width of image to be read out.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 24 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Horizontal Blank Time Upper [HBLU : 10h : 00h]
7 6 5 4 3 2 1 0
Horizontal Blank Time Upper 0 0 0 0 0 0 0 0
Horizontal Blank Time Lower [HBLL : 11h : d0h]
7 6 5 4 3 2 1 0
Horizontal Blank Time Lower 1 1 0 1 0 0 0 0
HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit, and should be larger than 208(d0h).
Vertical Blank Time Upper [VBLU : 12h : 00h]
7 6 5 4 3 2 1 0
Vertical Blank Time Upper 0 0 0 0 0 0 0 0
Vertical Blank Time Lower [VBLL : 13h : 08h]
7 6 5 4 3 2 1 0
Vertical Blank Time Lower 0 0 0 0 1 0 0 0
VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames.
Each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrates internal sensing circuit in order to get optimal performance. Sensor characteristics adjustment registers are as below.
Red Color Gain [RGAIN : 14h : 08h]
7 6 5 4 3 2 1 0
Reserved
Red Amplifier Gain
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 25 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
0
0
0
0
1
0
0
0
Green Color Gain [GGAIN : 15h : 08h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 1
Green Amplifier Gain 0 0 0
Blue Color Gain [BGAIN : 16h : 08h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 1
Blue Amplifier Gain 0 0 0
There are three color gain registers for R, G, B pixels, respectively. Programmable range is from 0.5X ~ 2.5X. Effective Gain = 0.5 + B<4:0>/16. These registers may be used for white balance and color effect with independent R,G,B color control. Default gain is 1X.
Amp Gain [AMPGAIN : 17h : 08h]
7 6 5 4 3 2 1 0
Reserved
Amp Gain
0 0 0 0 1 0 0 0 Amp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 8.5X. Default gain is 1X. Gain = 0.5 + B<6:0>/16
Amp Gain Minimum Value [AMPMIN : 18h : 10h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 1
Amp Gain Minimum 0 0 0 0
Amp Gain Minimum Value is minimum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. Programmable range is same as Amp Gain. Recommended value is 1.5X.
Amp Gain Maximum Value [AMPMAX : 19h : 28h]
7 6 5 4 3 2 1 0
Reserved
Amp Gain Maximum
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 26 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
0
0
1
0
1
0
0
0
Amp Gain Maximum Value is maximum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. Programmable range is same as Amp Gain. Recommended value is 3X.
Amp Gain Normal Value [AMPNOM : 1ah : 18h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 1
Amp Gain Normal 1 0 0 0
Amp Gain Normal Value is reference value of amp gain when sensor adjusts amp gain for auto exposure control. First, sensor controls integration time before adjusting amp gain for auto exposure control. After integration time is changed to the minimum or maximum value, sensor adjusts amp gain from this register value. Refer to figure of AE mode1 register(60H). Programmable range is same as amp gain. Recommended value is 2X.
ASP Bias [ASPBIAS : 1bh : 13h]
7 6 5 4 3 2 1 0
Reserved
Pixel Bias 0 0 1 0
Amplifier Bias 0 1 1
0
Pixel Bias
controls the amount of current in internal pixel bias circuit to amplify pixel output effectively. The larger register value increases the amount of current. controls the amount of current in internal amplifier bias circuit to amplify pixel output effectively. The larger register value increases the amount of current.
Amplifier Bias
Reset Level Clamp [RSTCLMP : 1ch : 07h]
7 6 5 4 3 2 1 0
Reserved 0 0 0
Clamp On 0 0
Reset Level Clamp 1 1 1
Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 27 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level.
ADC Bias [ADCBIAS : 20h : 02h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0 0
ADC Bias 1 0
ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively.
ADC Initial Offset Value for Optical Black Red [OREDI : 21h : 7fh]
7 6 5 4 3 2 1 0
Red Pixel Black Offset 0 1 1 1 1 1 1 1
ADC Initial Offset Value for Optical Black Green [OGRNI : 22h : 7fh]
7 6 5 4 3 2 1 0
Green Pixel Black Offset 0 1 1 1 1 1 1 1
ADC Initial Offse t Value for Optical Black Blue [OBLUI : 23h : 7fh]
7 6 5 4 3 2 1 0
Blue Pixel Black Offset 0 1 1 1 1 1 1 1
These registers control the offset voltage of ADC that changes the black level value for light-shielded pixels, R,G,B respectively. Register bit functions are composed as follows.
Pixel Black Offset[7] Pixel Black Offset[6:0]
The bit specifies whether to subtract or add offset voltage in ADC input for light-shielded pixels. This value specifies the amount of offset voltage for light-shielded pixels.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 28 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 29 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Black Level Threshold Value [BLKTH : 27h : ffh]
7 6 5 4 3 2 1 0
Black Level Threshold 1 1 1 1 1 1 1 1
The register specifies the maximum value that determines whether light-shielded pixel output is valid. When light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 30 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
ISP Function Enable [ISPFUN : 30h : ffh]
7
Reserved
6
Contrast Adjustment
5
Chroma Suppression
4
Edge Enhancement
3
Color Space Conversion
2
Color Correction
1
Color Interpolation
0
Gamma Correction
0
1
1
1
1
1
1
1
Contrast Adjustment 0 : Disable. 1 : Enable. Y Output multiplied by Contrast factor
Chroma Suppression 0 : Disable. 1 : Enable. Chroma Suppressed Cb,Cr Output
Edge Enhancement 0 : Disable. 1 : Enable.
Color Space Conversion 0 : Disable. R,G,B Output 1 : Enable. Y,Cb,Cr Output
Color Correction 0 : Disable. 1 : Enable.
Color Interpolation 0 : Disable. 1 : Enable.
Gamma Correction 0 : Disable. Normal Bayer Output 1 : Enable. Gamma Corrected Bayer Output
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 31 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Output Format [OUTFMT : 31h : 31h]
7 6 5 4 3 2 1 0
GammaCorrected Bayer
Bayer 8bit Output
Cb/B First
Y First
YCbCr 4:4:4 / 4:2:2
RGB 4:4:4
RGB 565
8 bit Output
0
0
1
1
0
0
0
1
Gamma-Corrected Bayer Bayer 8bit Output
Gamma-corrected Bayer data are output when Bayer mode is set in SCTRA register. Bayer data is output with 8bit mode, two LSB of 11 bit Bayer data is stripped out.
Cb/B First Y First
Cb(B) pixel in front of Cr(R) pixel in 16bit or 8bit video data output modes. Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is meaningful only with YCbCr 4:2:2 8bit output mode.
YCbCr 4:4:4 / 4:2:2 RGB 4:4:4 RGB 565
This bit is high, output format is YCbCr 4:4:4 16bit mode, otherwise output format is YCbCr 4:2:2 8bit/16bit mode. R,G,B 24bit data for a pixel is produced with 16bit output mode. Data format of RGB 565 mode is composed with {R[7:3]/G[7:5]} , {G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. OUTFMT[5](Cb/B First) register affects above data form.
8 Bit Output
Image Data is produced only in Y[7:0]. C[7:0] should be discarded.
Default mode of Output Format is YCbCr 4:2:2 8bit mode.
Output Signal Inversion [OUTINV : 32h : 00h]
7 6 5 4 3 2 1 0
Reserved
Clocked HSYNC
VSYNC inversion
HSYNC inversion
VCLK inversion
0
0
0
0
0
0
0
0
Clocked HSYNC
In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNC time
VSYNC inversion HSYNC inversion
VSYNC output polarity is inverted HSYNC output polarity is inverted
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 32 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
VCLK inversion
VCLK output polarity is inverted
Edge Enhancement Weight [EDGEWT : 33h : 02h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0
Edge Enhancement Weight 0 1 0
Edge Enhancement Weight range is 0.3(3' h000) ~ 1(3' h111), and default value is 0.5(3' h010). As Edge Enhancement Weight is large, the effect of Edge Enhancement grows stronger.
Color Correction Matrix Coefficient 11 [CRCM11 : 34h : 4ch]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 11 0 1 0 0 1 1 0 0
Color Correction Matrix Coefficient 12 [CRCM 12 : 35h : ech]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 12 1 1 1 0 1 1 0 0
Color Correction Matrix Coefficient 13 [CRCM 13 : 36h : 08h]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 13 0 0 0 0 1 0 0 0
Color Correction Matrix Coefficient 21 [CRCM 21 : 37h : f0h]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 21 1 1 1 1 0 0 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 33 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Color Correction Matrix Coefficient 22 [CRCM 22 : 38h : 76h]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 22 0 1 1 1 0 1 1 0
Color Correction Matrix Coefficient 23 [CRCM 23 : 39h : dbh]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 23 1 1 0 1 1 0 1 1
Color Correction Matrix Coefficient 31 [CRCM 31 : 3ah : feh]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 31 1 1 1 1 1 1 1 0
Color Correction Matrix Coefficient 32 [CRCM 32 : 3bh : e8h]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 32 1 1 1 0 1 0 0 0
Color Correction Matrix Coefficient 33 [CRCM 33 : 3ch : 5ah]
7 6 5 4 3 2 1 0
Color Correction Matrix Coefficient 33 0 1 0 1 1 0 1 0
Gamma Segment Start Points This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 34 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma approximation. Current default gamma curve is very selected for optimum gray gradation.
Gamma Point 0 [GAMP0 : 40h : 00h]
7 6 5 4 3 2 1 0
Gamma Point 0 0 0 0 0 0 0 0 0
Gamma Point 1 [GMAP1 : 41h : 04h]
7 6 5 4 3 2 1 0
Gamma Point 1 0 0 0 0 0 1 0 0
Gamma Point 2 [GMAP2 : 42h : 1ch]
7 6 5 4 3 2 1 0
Gamma Point 2 0 0 0 1 1 1 0 0
Gamma Point 3 [GMAP3 : 43h : 34h]
7 6 5 4 3 2 1 0
Gamma Point 3 0 0 1 1 0 1 0 0
Gamma Point 4 [GMAP4 : 44h : 54h]
7 6 5 4 3 2 1 0
Gamma Point 4 0 1 0 1 0 1 0 0
Gamma Point 5 [GMAP5 : 45h : 78h] This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 35 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
7
6
5
4
3
2
1
0
Gamma Point 5 0 1 1 1 1 0 0 0
Gamma Point 6 [GMAP6 : 46h : 90h]
7 6 5 4 3 2 1 0
Gamma Point 6 1 0 0 1 0 0 0 0
Gamma Point 7 [GMAP7 : 47h : a4h]
7 6 5 4 3 2 1 0
Gamma Point 7 1 0 1 0 0 1 0 0
Gamma Point 8 [GMAP8 : 48h : e0h]
7 6 5 4 3 2 1 0
Gamma Point 8 1 1 1 0 0 0 0 0
Gamma Point 9 [GMAP9 : 49h : f4h]
7 6 5 4 3 2 1 0
Gamma Point 9 1 1 1 1 0 1 0 0
Gamma Slope 0 [GMAS0 : 50h : 40h]
7 6 5 4 3 2 1 0
Gamma Slope 0 0 1 0 0 0 0 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 36 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Gamma Slope 1 [GMAS1 : 51h : 80h]
7 6 5 4 3 2 1 0
Gamma Slope 1 1 0 0 0 0 0 0 0
Gamma Slope 2 [GMAS2 : 52h : 60h]
7 6 5 4 3 2 1 0
Gamma Slope 2 0 1 1 0 0 0 0 0
Gamma Slope 3 [GMAS3 : 53h : 40h]
7 6 5 4 3 2 1 0
Gamma Slope 3 0 1 0 0 0 0 0 0
Gamma Slope 4 [GMAS4 : 54h : 24h]
7 6 5 4 3 2 1 0
Gamma Slope 4 0 0 1 0 0 1 0 0
Gamma Slope 5 [GMAS5 : 55h : 18h]
7 6 5 4 3 2 1 0
Gamma Slope 5 0 0 0 1 1 0 0 0
Gamma Slope 6 [GMAS6 : 56h : 14h]
7 6 5 4 3 2 1 0
Gamma Slope 6 0 0 0 1 0 1 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 37 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Gamma Slope 7 [GMAS7 : 57h : 0fh]
7 6 5 4 3 2 1 0
Gamma Slope 7 0 0 0 0 1 1 1 1
Gamma Slope 8 [GMAS8 : 58h : 05h]
7 6 5 4 3 2 1 0
Gamma Slope 8 0 0 0 0 0 1 0 1
Gamma Slope 9 [GMAS9 : 59h : 02h]
7 6 5 4 3 2 1 0
Gamma Slope 9 0 0 0 0 0 0 1 0
Brightness Factor Y [BRIGHTY : 5ah : 00h]
7 6 5 4 3 2 1 0
Brightness Factor Y 0 0 0 0 0 0 0 0
Brightness Adjustment is performed for summing Y data and Brightness Factor Y. Brightness Factor Y is two' complement and its range is -128 ~ 127. s Bright Y = Y data + Brightness Factor Y. for positive values, B<7:0> = Integer; for negative values, B<7:0> = Two' Complement(Integer); s
Saturation Factor Cr [SATCR : 5bh : 80h]
7 6 5 4 3 2 1 0
Saturation Factor Cr 1 0 0 0 0 0 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 38 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Saturation Factor Cb [SATCB : 5ch : 80h]
7 6 5 4 3 2 1 0
Saturation Factor Cb 1 0 0 0 0 0 0 0
Saturation Adjustment is performed for multiplying Cr,Cb data by Saturation Factor Cr,Cb, respectively. Programmable range of Saturation Factor Cb,Cr is 0 ~ 2. For instant, Sat Cb = Cb data * B<7:0>/128.
Edge Enhancement Threshold Low [EDTHLO : 5dh : 05h]
7 6 5 4 3 2 1 0
Edge Enhancement Threshold Low 0 0 0 0 0 1 0 1
Edge Enhancement Threshold High [EDTHHI : 5eh : 80h]
7 6 5 4 3 2 1 0
Edge Enhancement Threshold High 1 0 0 0 0 0 0 0
Chroma Suppression Function [CHSUPFNC : 5fh : 64h]
7 6 5 4 3 2 1 0
Saturation Level 0 1 1 0
Suppression Gain Minimum 0 1 0 0
Saturation Level
11
0% of difference between Current Cb,Cr data and reference Cb,Cr level. So, Chroma Suppressed Cb,Cr data are equal to Current Cb,Cr data.
10 01 00 Suppression Gain Minimum
25% of difference between Current Cb,Cr data and reference Cb,Cr level. 50% of difference between Current Cb,Cr data and reference Cb,Cr level. 75% of difference between Current Cb,Cr data and reference Cb,Cr level.
When Amp Gain is greater than Suppression Gain Minimum, Chroma Suppression Function is started.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 39 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 40 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Auto Exposure
Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame Y mean value and target Y mean value.
FFh
AE Unlock Boundary [68h]
AE Lock Boundary [67h] 80h AE Target [66h] AE Lock Boundary [67h]
AE Unlock Boundary [68h]
0h Y Frame Mean
AE Mode Control 1 [AEMODE1 : 60h : bdh]
7 6 5 4 3 2 1 0
Anti - Banding Enable 1
Full Window
Window Mode
AE speed
AE Mode
0
1
1
1
1
0
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 41 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Anti-Banding Enable
When Anti-Banding is enabled, AE initializes Integration Time registers[63h65h] to 4 x Anti-Banding Step value[6ah-6ch], and integration
increment/decrement amount is set to Anti-Banding Step value in order to remove banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. In this mode, AE operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. Therefore, this mode is recommended for only indoor use. Full Window With this bit set to high, window mode is discarded and full image data is accounted for AE Y frame mean evaluation Window Mode 11 1/8 center weighted window mode. Weighting ratio is 8:1 for inside area vs. outside area 10 01 1/8 center only window mode. 1/4 center weighted window mode. Weighting ratio is 4:1 for inside area vs. outside area 00 AE Speed AE Mode 1/4 center only window mode.
(fast)11 - 10 - 01 - 00(slow) 11 Gain-Only control mode. Only preamp gain is controlled to get optimum exposure state. 10 Time-Only control mode. Only integration time is controlled to get optimum exposure state. 01 Time-Gain control mode. Integration time and preamp gain are controlled to get optimum exposure state. 00 AE function is disabled
AE Mode Control 2 [AEMODE2 : 61h : 5dh]
7 6 5 4 3 2 1 0
Reserved
Gain Speed
Integration Time Fine Tune
Amp Gain Fine Tune
AntiBanding Minimum Break
AE Subsampling mode
AE Analog Gain Control
0
1
0
1
1
1
0
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 42 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Gain Speed
Gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow)
Integration Time Fine Tune Amp Gain Fine Tune
Integration time fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Amp gain fine tuning is performed when AE a rrive around AE Fine Tune Boundary to settle into AE lock state smoothly.
Anti-Banding Minimum When AE is still of out lock state despite that AE preamp analog gain update Break value exceeds preamp minimum gain value(18h) and integration time(63h65h) is reached to AE Anti-Banding Step(6ah-6ch), integration time(63h-65h) is broken to less than AE Anti-Banding Step(6ah-6ch). AE Sub-sampling Mode AE Analog Gain Control AE statistics is executed on 1/4 of original image data to save power consumption AE updates Amp gain register(17h) in order to reach optimum exposure state
Color Space Conversion Mode [CSCMODE : 62h : 00h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 1 0
CSC Mode 0 0
Reserved 0
CSC Mode
0 : Mode 1 1 : Mode 2
Integration Time High [INTH: 63h : 13h]
7 6 5 4 3 2 1 0
Integration Time Higher 0 0 0 1 0 0 1 1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 43 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Integration Time Middle [INTM: 64h: 88h]
7 6 5 4 3 2 1 0
Integration Time Middle 1 0 0 0 1 0 0 0
Integration Time Low [INTL: 65h: 00h]
7 6 5 4 3 2 1 0
Integration Time Lower 0 0 0 0 0 0 0 0
Integration time value register defines the time which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera so that integration time needs to be increased in dark environment and decreased according to lighting condition. Maximum integration time is register maximum value(224-1) x sensor clock period (52ns, SCF 19.2Mhz) = 0.87sec. SCF = Sensor Clock Frequency
Luminance Target Value [AETRGT : 66h : 70h]
7 6 5 4 3 2 1 0
Luminance Target 0 1 1 1 0 0 0 0
This register defines the target luminance value for AE operation.
AE Lock & Fine Tune Boundary [AELFBND : 67h : a2h]
7 6 5 4 3 2 1 0
AE Fine Boundary 1 0 1 0 0
AE Lock Boundary 0 1 0
AE Lock Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded, and instead AE Speed Unlock Boundary is used as Lock boundary. AE Fine Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 44 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE start to tune fine integration time or amp gain in order to goes into lock state smoothly.
AE Unlock Boundary [AEULBND : 68h : 2ah]
7 6 5 4 3 2 1 0
AE Unlock Boundary 0 0 1 0 1 0 1 0
AE Speed Boundary 0 specifies Y Frame Mean displacement from AE Target where integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In anti-banding mode, this boundary is used as lock boundary for exposure control.
AE Speed and Frame Control [ASFCON : 69h : 00h]
7 6 5 AE Speed 2 4 3 2 1 0
Reserved
Y Frame Control
Cb,Cr Frame Control
0
0
0
0
0
0
0
0
AE Speed 2 Y Frame Control
(fast)11 - 10 - 01 - 00(slow) 11 10 01, 00 4 Frame mean Value. ( For AE ) 2 Frame mean Value. 1 Frame mean Value. 4 Frame mean Value. ( For AWB ) 2 Frame mean Value. 1 Frame mean Value.
Cb,Cr Frame Control
11 10 01, 00
AE Speed 2 is different in use to AE Speed 1. When Y Frame Mean is out of Unlock boundary, AE updates quickly Amp Gain register(17h) in order to reach Lock boundary state. Gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow) Frame Control register can be use 1, 2, 4 Frame mean Value. 4 Frame mean value has a history component of previous 3 Frame mean Value. To use 1 Frame mean Value is that AE changed every Frame instantly. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 45 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE Anti-Banding Step High [AESTEPH : 6ah : 02h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0 0
Integration Step Higher
1
0
AE Anti-Banding Step Middle [AESTEPM : 6bh : eeh]
7 6 5 4 3 2 1 0
Integration Step Middle 1 1 1 0 1 1 1 0
AE Anti-Banding Step Low [AESTEPL : 6ch : 00h]
7 6 5 4 3 2 1 0
Integration Step Lower 0 0 0 0 0 0 0 0
AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled. Anti-Banding Step value is resolved by the following equation. Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency) The default value is set with SCF 19.2Mhz, 50Hz power line, that is, Anti-Banding Step Value = 19.2Mhz / (2 x 50) = 192000d = 02ee00h
AE Integration Time Limit High [AEINTH : 6dh : 3ah]
7 6 5 4 3 2 1 0
AE Integration Time Limit Higher 0 0 1 1 1 0 1 0
AE Integration Time Limit Middle [AEINTM : 6eh : 98h]
7 6 5 4 3 2 1 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 46 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE Integration Time Limit Middle 1 0 0 1 1 0 0 0
AE Integration Time Limit Low [AEINTL : 6fh : 00h]
7 6 5 4 3 2 1 0
AE Integration Time Limit Lower 0 0 0 0 0 0 0 0
These three registers define the maximum integration time value that is allowed to sensor operation. It is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding mode enabled. The default value is set to 1/5sec with SCF set to 19.2Mhz 19.2Mhz / 5 = 3840500d = 3a9800h
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 47 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.
FFh AWVB White Pixel Boundary [77h]
AWB Unlock Boundary [76h]
AWB Lock Boundary [75h] 80h Cb/Cr Target [73h-74h] AWB Lock Boundary [75h]
AWB Unlock Boundary [76h]
AWB White Pixel Boundary [77h] 0h Cb/Cr Frame Mean
AWB Mode Control 1 [AWBMODE1 : 70h : 41h]
7 6 5 4 3 2 1 0
Reserved
Full Window
Reserved
Window Mode
AWB speed
Reserved
AWB On
0
1
0
0
0
0
0
1
Full Window
With this bit set to high, window mode is discarded and full image data is accounted for AE Y frame mean evaluation
Window Mode
1
1/4 center weighted window mode. Weighting ratio is 4:1 for inside area vs. outside area
0 AWB Speed AWB On
1/4 center only window mode.
(Fast)11 - 10 - 01 - 00(slow) Auto White Balance Control Enabled
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 48 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AWB Mode Control 2 [AEMODE2 : 71h : 02h]
7 6 5 4 3 2 1 0
Reserved
AWB Low Speed
AWB Subsampling mode
AWB Analog Gain Control
Reserved
0
0
0
0
0
0
1
0
AWB Low Speed
With this bit set to high, analog gain speed is decreased to 1/4 of the normal speed.
AWB Sub-sampling Mode AWB Analog Gain Control
AWB statistics is executed on 1/4 of original image data to save power consumption AWB updates R/B gain registers(14h,16h) in order to reach optimum white balance state
Cb Frame Mean Value [CBTRGT : 73h : 80h]
7 6 5 4 3 2 1 0
Cb Frame Mean 1 0 0 0 0 0 0 0
This register defines Cb target frame mean value for AWB operation.
Cr Frame Mean Value [CRTRGT : 74h : 80h]
7 6 5 4 3 2 1 0
Cr Frame Mean 1 0 0 0 0 0 0 0
This register defines Cr target frame mean value for AWB operation.
AWB Lock Boundary [AWBLBND : 75h : 02h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0
AWB Lock Boundary 0 1 0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) value where AWB This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 49 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
goes into LOCK state. AWB Unlock Boundary [AWBULBND : 76h : 06h]
7 6 5 4 3 2 1 0
AWB Unlock Boundary 0 0 0 0 0 1 1 0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) where AWB is released from LOCK state. AWB operation retains LOCK state unless C b/Cr frame mean values' displacement value exceeds this boundary. The value should be larger AWB Lock Boundary.
AWB White Pixel Boundary [AWBWBND : 77h : 30h]
7 6 5 4 3 2 1 0
AWB White Pixel Boundary 0 0 1 1 0 0 0 0
When Cb/Cr frame mean values' displacement from Cb/Cr Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation.
Current AE Operation Status [AESTAT : 7bh : RO]
7 6 5 4 3 2 1 0
AE Mode State
RO RO RO RO RO
AE Lock state
RO RO RO
AE Mode State
This nibble represents the mode where internal Y plane FSM is currently placed among time-gain control, time-only control, or gain-only control modes.
AE Lock State
Y channel FSM status, "0000" means that AE Y plane is in lock state
Current AWB Operation Status [AWBSTAT : 7ch : RO]
7 6 5 4 3 2 1 0
reserved
AE/AWB Lock
Cb Lock State
Cr Lock State
RO
RO
RO
RO
RO
RO
RO
RO
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 50 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE/AWB Lock
This single status bit indicates that AE and AWB are in lock state for optimum still image capture.
Cb Lock State Cr Lock State
Cb channel FSM status. "00" means that AWB Cb plane is in lock state Cr channel FSM status. "00" means that AWB Cr plane is in lock state
Active Y Frame Mean Value [LUMEAN : 7dh : RO]
7 6 5 4 3 2 1 0
Y Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Y plane frame mean value.
Active Cb Frame Mean Value [CBMEAN : 7eh : RO]
7 6 5 4 3 2 1 0
Cb Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cb plane frame mean value.
Active Cr Frame Mean Value [CRMEAN : 7fh : RO]
7 6 5 4 3 2 1 0
Cr Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cr plane frame mean value.
Minimum Anti-Banding Gain [BNDGMIN : 80h : 08h]
7 6 5 4 3 2 1 0
Minimum Anti-Banding Gain 0 0 0 0 1 0 0 0
The register specifies the minimum limit to which AE may decrease preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 51 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AE Lock Boundary < (Y Frame Mean - AE Target) < AE Unlock Boundary.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 52 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Maximum Anti-Banding Gain [BNDGMAX : 81h : 18h]
7 6 5 4 3 2 1 0
Maximum Anti-Banding Gain 0 0 0 1 1 0 0 0
The register specifies the maximum limit to which AE may increase preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (AE Target - Y Frame Mean) < AE Unlock Boundary.
AWB Luminance Higher Limit [AWBWHT : 8ah : c8h]
7 6 5 4 3 2 1 0
AWB Luminance Higher Limit 1 1 0 0 1 0 0 0
During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is larger than this register value.
AWB Luminance Lower Limit [AWBBLK : 8bh : 0ah]
7 6 5 4 3 2 1 0
AWB Luminance Lower Limit 0 0 0 0 1 0 1 0
During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is smaller than this register value.
AWB Valid Number of Pixel [AWBVALID : 8ch : 02h]
7 6 5 4 3 2 1 0
AWB Valid Number of Pixel 0 0 0 0 0 0 1 0
AWB update when the number of valid color pixel is larger than (this valid value x 64).
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 53 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Dark Bad Pixel Concealment Mode [DPCMODE : 90h : 01h]
7 6 5 4 3 2 1 0
Reserved
Dark Bad Pixel Concealment Mode
0
0
0
0
0
0
0
1
Dark Bad Pixel Concealment 10 Mode 01
Dark Bad Pixel Concealment is always performed. Dark Bad Pixel Concealment is performed when Integration Time (63h-65h) exceeds Dark Bad Integration Time(91h-93h)
11, 00
Dark Bad Pixel Concealment is turned off
Dark Bad Integration Time High [DPCINTH : 91h : 29h]
7 6 5 4 3 2 1 0
Dark Integration Time Higher 0 0 1 0 1 0 0 1
Dark Bad Integration Time Middle [DPCINTM : 92h : dah]
7 6 5 4 3 2 1 0
Dark Integration Time Middle 1 1 0 1 1 0 1 0
Dark Bad Integration Time Low [DPCINTL : 93h : 49h]
7 6 5 4 3 2 1 0
Dark Integration Time Lower 1 1 0 0 1 0 0 1
Dark Bad Integration Time registers(91h-93h) specify minimum integration time value(63h-65h) where dark bad concealment operation is performed when dark bad pixel concealment mode is "01 (binary)".
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 54 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Dark G Threshold [DPCGTH : 94h : 20h]
7 6 5 4 3 2 1 0
Dark G Threshold 0 0 1 0 0 0 0 0
The register value specify the current G pixel' differential value with neighboring G pixels, and is used s to check whether current G pixel is dark bad pixel or not.
Dark R/B Threshold [DPCGTH : 95h : 20h]
7 6 5 4 3 2 1 0
Dark R/B Threshold 0 0 1 0 0 0 0 0
The register value specify the current R or B pixel' differential value with neighboring G pixels, and is s used to check whether current R or B pixel is dark bad pixel or not.
Reference of Amp Gain for Dark Bad Pixel Concealment [DPCGAIN : 96h : 38h]
7 6 5 4 3 2 1 0
Reference of Amp Gain for Dark Bad Pixel Concealment 0 0 1 1 1 0 0 0
Amp Gain exceeds Reference of Amp Gain for Dark Bad Pixel Concealment, dark bad concealment operation is performed when dark bad pixel concealment mode is "01
Contrast factor Y [CONTY : 97h : 80h]
7 6 5 4 3 2 1 0
Contrast factor Y 1 0 0 0 0 0 0 0
Contrast Adjustment is performed for multiplying Y data by Contrast Factor Y, respectively. Programmable range of Contrast Factor Y is 0 ~ 2. Cont Y = Y data * B<7:0>/128.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 55 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
PLL Control Mode A [PCTRA : a0h : 01h]
7 6 5 4 3 2 1 0
Reserved
VCO Power Down
PLL Power Down 0
Bypass Mode
0
0
0
0
0
0
1
VCO Power Down (Active High) PLL Power Down (Active High)
When VCO Power Down is active, VCO does not oscillate. For getting out of VCO Power Down, VCO initialization is required. When PLL Power Down is active, digital circuits of PLL do not operate and the charge pump circuits is disabled. Also Bypass Mode or Sleep
Mode(SCTRB[4]) register is set to high, PLL goes into sleep. Bypass Mode 0 1 * VCO initialization To ensure the proper operation of the PLL, the activation of VCO initialization signal is required just after the deactivation of the VCO Power Down. During power-up sequence VCO initialization signal is recommended for more than 100ns. PLL output clock is 1/F(ck). PLL output clock is the same of PLL input clock.
PLL Control Mode B [PCTRB : a1h : 1dh]
7 6 5 4 3 2 1 0
Reserved 0 0 0
Post Divisor 1 1
Charge Pump Bias 1 0 1
The value of Post Divisor according to the output frequency Post Divisor Min 11 10 01 00 5MHz 10MHz 20MHz 40MHz F(ck) Max 12.5MHz 25MHz 50MHz 100MHz
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 56 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
PLL Feedback Divisor High [PFDDIVH : a4h : 00h]
7 6 5 4 3 2 1 0
PLL Feedback Divisor High 0 0 0 0 0 0 0 0
PLL Feedback Divisor Low [PFDDIVL : a5h : 02h]
7 6 5 4 3 2 1 0
PLL Feedback Divisor Low 0 0 0 0 0 0 1 0
The operation frequency of PLL is related to the proportion of Reference(PREFDIV) to Feedback(PFDDIV) Divisor. F(ck) is actually determined by the following equation.
F ( ck ) =
F ( ref ) ( Feedback Divisor ) ( R eference Divisor )
F(ck) : frequency of output F(ref) : frequency of PLL input Feedback Divisor : PFDDIV[13:0] + 2 Reference Divisor : 2
Pixel Number High [PXNUMH : b9h : 04h]
7 6 5 4 3 2 1 0
Pixel Number High 0 0 0 0 0 1 0 0
Pixel Number Low [PXNUML : bah : 00]
7 6 5 4 3 2 1 0
Pixel Number Low 0 0 0 0 0 0 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 57 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Stable Range variation [STTHVAL : bbh : 30h]
7 6 5 4 3 2 1 0
Stable Range variation 0 0 1 1 0 0 0 0
Frequency Change Variation [CHTHVAL : bch : 20h]
7 6 5 4 3 2 1 0
Frequency Change Variation 0 0 1 0 0 0 0 0
AFC Mode Control [AFCMODE : bdh : 00h]
7 6 5 4 3 2 1 0
Reserved
AFC Mode
Reserved
AFC Enable
0
0
0
0
0
0
0
0
AFC Mode
0 1
selected first AFC algorithm selected second AFC algorithm AFC off AFC on
AFC Enable
0 1
50Hz Integration Time High [INTEG50H : c0h : 02h]
7 6 5 4 3 2 1 0
50Hz Integration Time High 0 0 0 0 0 0 1 0
50Hz Integration Time Middle [INTEG50M : c1h : eeh]
7 6 5 4 3 2 1 0
50Hz Integration Time Middle This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 58 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
1
1
1
0
1
1
1
0
50Hz Integration Time Low [INTEG50L : c2h : 00h]
7 6 5 4 3 2 1 0
50Hz Integration Time Low 0 0 0 0 0 0 0 0
60Hz Integration Time High [INTEGT60H : c3h : 02h]
7 6 5 4 3 2 1 0
60Hz Integration Time High 0 0 0 0 0 0 1 0
60Hz Integration Time Middle [INTEGT60M : c4h : 71h]
7 6 5 4 3 2 1 0
60Hz Integration Time Middle 0 0 0 0 0 0 0 0
60Hz Integration Time Low [INTEGT60L :c5h : 00h]
7 6 5 4 3 2 1 0
60Hz Integration Time Low 0 0 0 0 0 0 0 0
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 59 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Anti-Banding Configuration
For Anti-Banding mode to work correctly, the following registers should be configured to the appropriate values.
AE Mode AE Anti-Banding Step AE Integration Time Limit
60h 6a-6ch 6d-6fh
Anti-Banding Enable[7] (Sensor Clock Frequency) / (2 x power line frequency) The value should be multiples of AE Anti-Banding Step
When Anti-Banding is enabled, AE initializes Integration Time registers[63-65h] to 4 x Anti-Banding Step value[6a-6ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition.
Frame Timing
For clear description of frame timing, clocks'acronyms are reminded in here again.
< Clock Acronym Definition > MCF : Master Clock Frequency DCF : Divided Clock Frequency ICF : Image Processing Clock Frequency VCF : Video Clock Frequency PCF : PLL Out Clock Frequency SCF : Sensor Clock Frequency LCF : Line Clock Frequency
< Frame Time Calculation > Core Frame Time is (IDLE SLOT + Video Height * LCP) and Real Frame Time is resolved as follows. When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP), otherwise is (Core Frame Time + VBLANK * LCP).
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 60 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
1. 5x5 Color Interpolation Timing (Full Size Mode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency 19.2Mhz PCF/1 = 38.4Mhz 1/19.2Mhz = 52ns 864 8 1366 SCPs SCF * 2 = 38.4Mhz PLL Out Clock Frequency(PCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size MCF*2 = 38.4Mhz DCF/2 = 19.2Mhz 1152 208 Line Mode 8bit 1152x864
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (1152 SCPs) Active Data: 1152 EA ISP Dummy LCP(1366 SCPs) (6 SCPs)
Video Lines is active every LCP, that is, 864 Video Lines for 864 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
If Integration Time < Core Frame Time, Real Frame Time is 4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 * (208+1024)= 1201544 SCPs = 0.062580sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. -> 15.979 frame per sec.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 61 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
2. 5x5 Color Interpolation Timing (1/4 Sub-Sampling Mode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency 19.2Mhz PCF/1 = 38.4Mhz 1/19.2Mhz = 52ns 432 8 1366 SCPs SCF = 19.2Mhz PLL Out Clock Frequency(PCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size MCF*2 = 38.4Mhz DCF/2 = 19.2Mhz 576 208 Line Mode 8bit 576x432
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (1152 SCPs) Active Data: 576 EA ISP Dummy LCP(1366 SCPs) (6 SCPs)
Video Lines is active every LCP, that is, 432 Video Lines for 432 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
If Integration Time < Core Frame Time, Real Frame Time is 4 * (208 + 1152+6) SCPs + 432 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 * (208+1024)= 611432 SCPs = 0.031845sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. -> 31.402 frame per sec.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 62 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
3. 5x5 Color Interpolation Timing (1/16 Mode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency 19.2Mhz PCF/1 = 38.4Mhz 1/19.2Mhz = 52ns 216 8 1366 SCPs SCF/2 = 9.6Mhz PLL Out Clock Frequency(PCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size MCF*2 = 38.4Mhz DCF/2 = 19.2Mhz 288 208 Line Mode 8bit 288x216
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (1152 SCPs) Active Data: 288 EA ISP Dummy LCP(1366 SCPs) (6 SCPs)
Video Lines is active every LCP, that is, 216 Video Lines for 216 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
If Integration Time < Core Frame Time, Real Frame Time is 4 * (208 + 1152+6) SCPs + 216 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 * (208+1024)= 316376 SCPs = 0.016478sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. -> 60.687frame per sec.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 63 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
4. 5x5 Color Interpolation Timing (VgaMode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency 19.2Mhz PCF/1 = 38.4Mhz 1/19.2Mhz = 52ns 480 8 1366 SCPs Irregular clock PLL Out Clock Frequency(PCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size MCF*2 = 38.4Mhz DCF/2 = 19.2Mhz 640 208 Line Mode 8bit 640x480
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (1152 SCPs) Active Data: 640 EA ISP Dummy LCP(1366 SCPs) (6 SCPs)
Video Lines is active every LCP, that is, 480 Video Lines for 864 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
If Integration Time < Core Frame Time, Real Frame Time is 4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 * (208+1024)= 1201544 SCPs = 0.062580sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. VgaMode Frame rate is same as Full Size Mode. And QVgaMode has same frame rate. -> 15.979 frame per sec.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 64 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
5. 5x5 Color Interpolation Timing (CifMode)
5x5 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency 19.2Mhz PCF/1 = 38.4Mhz 1/19.2Mhz = 52ns 288 8 1366 SCPs Irregular clock PLL Out Clock Frequency(PCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size MCF*2 = 38.4Mhz DCF/2 = 19.2Mhz 352 208 Line Mode 8bit 352x288
IDLE SLOT(4LCPs + (1024+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (1152 SCPs) Active Data: 352 EA ISP Dummy LCP(1366 SCPs) (6 SCPs)
Video Lines is active every LCP, that is, 288 Video Lines for 864 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
If Integration Time < Core Frame Time, Real Frame Time is 4 * (208 + 1152+6) SCPs + 864 * (208 + 1152+6) SCPs + 8 * (208 + 1152+6) SCPs + 4 * (208+1024)= 1201544 SCPs = 0.062580sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 1152 + 6) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. QCifMode Frame rate is same as CifMode Frame rate. -> 15.979 frame per sec.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 65 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Output Data according to Video Mode
Output Data according to Video Mode is controlled by configuring Sensor Control A[01h] and Output Format register[31h]. Configurable options are specified again for your reference.
Sensor Control A [SCTRA : 01h : 13h]
7 6 5 4 3 2 1 0
Reserved 0 0 0
X-Flip 1
Y-Flip 0 0
Video Mode 1 1
Output Format [OUTFMT : 31h : 31h]
7 6 5 4 3 2 1 0
GammaCorrected Bayer
Bayer 8bit Output
Cb/B First
Y First
YCbCr 4:4:4 / 4:2:2
RGB 4:4:4
RGB 565
8 bit Output
0
0
1
1
0
0
0
1
Output timings for general configurations are described below. Slot named as "X" means that it is has no meaningful value and should be discarded. 8bit Output is active, C[7:0] are always Hi-Z state. In Case of Cb or Cr data, the digit stands for its sequence, respectively. For example, Cb01 is equal to average of Cb0 and Cb1.
5X5 Mode or Sub-sampling(1/4, 1/16) Mode
1. YCbCr 4:2:2 with 8bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 8bit Output, Y First, Cb/B First
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 66 2003 Hynix Semiconductor Inc.
Confidential
MCLK
HV7151SP CMOS Image Sensor With Image Signal Processing
HSYNC
5X5 Mode Video Clock & Output Data CLK Y[7:0] X X Y0 Cb01 Y1 Cr01 Y2 Cb23 Y3 Cr23 Y4 Cb45 Y5 Cr45 Y6
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] X Y0 Cb02 Y2 Cr02 Y4 Cb46 Y6
1/16 Sub
- sampling Video Clock & Output Data CLK
Y[7:0]
X
Y0
Cb04
Y4
Cr04
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 67 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
2.
YCbCr 4:2:2 with 16bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 16bit Output, Cb/B First
MCLK
HSYNC
5X5 Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb01 Y1 Cr01 Y2 Cb23 Y3 Cr23 Y4 Cb45 Y5 Cr45 Y6 Cb67
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb02 Y2 Cr02 Y4 Cb46 Y6 Cr46
1/16 Sub
- sampling Video Clock & Output Data CLK
Y[7:0] C[7:0]
X X
Y0 Cb04
Y4 Cr04
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 68 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
3.
YCbCr 4:4:4 with 16bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 16bit Output, Y First, Cb/B First
MCLK
HSYNC
5X5 Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X X X Y0 X Y1 X Y2 X Y3 X Y4 X Y5 X Y6
Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb0 X Cr0 Y2 Cb2 X Cr2 Y4 Cb4 X Cr4 Y6 Cb6
1/16 Sub
- sampling Video Clock & Output Data CLK
Y[7:0] C[7:0]
X X
Y0 Cb0
X Cr0
Y4 Cb4
X Cr4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 69 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
4.
RGB 565 with 8bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 8bit Output, Cb/B First, RGB565
MCLK
HSYNC
5 X5 Mode Video Clock & Output Data CLK Y[7:0] X X RG0 GB0 RG1 BG1 RG2 GB2 RG3 GB3 RG4 GB4 RG5 GB5 RG6
{ R0[7:3]G0[7:5]} {G0[4:2]B0[7:3]}
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG2 GB2 RG4 GB4 RG6
1/16
Sub - sampling Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG4 GB4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 70 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
5.
RGB 565 with 16bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 16bit Output, Cb/B First, RGB565
MCLK
HSYNC
5 X5 Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 RG4 GB4 RG5 GB5 RG6 GB6
{R0[7:3]G0[7:5]} {G0[4:2]B0[7:3]}
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG2 GB2 RG4 GB4 RG6 GB6
1/16
Sub - sampling Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG4 GB4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 71 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
6.
RGB 4:4:4 with 16bit output
Register bit configurations Sensor Control A : 5x5 Mode or Sub-sampling Mode Output Format : 16bit Output, Cb/B First, RGB4:4:4
MCLK
HSYNC
5X5 Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X X X G0 B0 X R0 G1 B1 X R1 G2 B2 X R2 G3 B3 X R3 G4 B4 X R4 G5 B5 X R5 G6 B6
1/4 Sub - sampling Video Clock & Output Data CLK Y[7:0] C[7:0] X X G0 B0 X R0 G2 B2 X R2 G4 B4 X R4 G6 B6
1/16 Sub
- sampling Video Clock & Output Data CLK
Y[7:0] C[7:0]
X X
G0 B0
X R0
G4 B4
X R4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 72 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
VGA Mode or QVGA Mode
1. YCbCr 4:2:2 with 8bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 8bit Output, Y First, Cb/B First
MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] X Y0 Cb01Y1 Cr01Y2 Cb23Y3 Cr23 Cb Y5 Cr45 Y6 Cb67Y7 Cr67 Y8 Cb89 89 Y10 Y4 Y9Cr 45
QVGA Mode Video Clock & Output Data CLK Y[7:0] X Y0 Cb01Y1 Cr01 X X X Cb X Y4 Y5 Cr45 X 45 X X X Y8 Cb89 89 X Y9Cr
2.
YCbCr 4:2:2 with 16bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 16bit Output, Cb/B First MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 RG2 GB2 RG3 RG4 RG5 GB3 GB4 GB5 RG6 GB6 RG7 GB7 RG8 RG9 RG10 GB8 GB9GB10
QVGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb01 Y1 Cr01 X X X X Y4 Y5 X X X X Y8 Y9 Y10 Cb45 Cr45 Cb89 Cr89
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 73 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
3.
YCbCr 4:4:4 with 16bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 16bit Output, Y First, Cb/B First
MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X Y0 X Y1 X Y2 X Y3 X Y4X Y5 X Y6 X Y7 X Y8 X Y9 X Y10 X Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3C Cr4Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cr9 b4 Cb9 Cb10
QVGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X Y0 X X X Cb0 Cr0 X X Y2 X X X Cb2 Cr2 X X Y4X X X C Cr4 X b4 X Y6 X X X Cb6 Cr6 X X Y8 X X X Y10 X Cb8 Cr8 X X Cb10
4.
RGB 565 with 8bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 8bit Output, Cb/B First, RGB565
MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] X RG0GB0RG1GB1RG2GB2RG3 RG RG5GB5RG6GB6 RG7GB7RG8 RG RG10 GB34 GB GB89 GB 4 9
QVGA Mode Video Clock & Output Data CLK Y[7:0] X RG0GB0 X X RG2GB2 X GB X RG X 44 X RG6GB6 X X RG8 GB8X X RG10
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 74 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
5.
RGB 565 with 16bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 16bit Output, Cb/B First, RGB565
MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 RG2 GB2 RG3 RG4 RG5 GB3 GB4 GB5 RG6 GB6 RG7 GB7 RG8 RG9 RG10 GB8 GB9GB10
QVGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 X X X X RG4 RG5 GB4 GB5 X X X X RG8 RG9 X GB8 GB9 X
6.
RGB 4:4:4 with 16bit output
Register bit configurations Sensor Control A : VGA Mode or QVGA Mode Output Format : 16bit Output, Cb/B First, RGB4:4:4 MCLK HSYNC VGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X G0 X G1 X G2 X G3 X G4X G5 X G6 X G7 X G8 X G9X G10 B0 R0 B1 R1 B2 R2 B3 R3 B4 B5 R5 B6 R6 B7 R7 B8 R8 B9R9 B10 R4
QVGA Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X G0 X X B0 R0 X X X G2 X X B2 R2 X X G4X X X B4 X R4 X X G6 X X B6 R6 X X X G8 X X X G10 B8 R8 X X B10
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 75 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
CIF Mode or QCIF Mode
1. YCbCr 4:2:2 with 8bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 8bit Output, Y First, Cb/B First
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] X Y0 Cb01 Y1 Cr01 Y2 Cb23 Y3 Cr23 Y4 Cb45
QCIF Mode Video Clock & Output Data CLK Y[7:0] X Y0 Cb01 Y1 Cr01 X X X X Y4 Cb01
2.
YCbCr 4:2:2 with 16bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 16bit Output, Cb/B First
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb01 Y1 Cr01 Y2 Cb23 Y3 Cr23 Y4 Cb45
QCIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb01 Y1 Cr01 X X X X Y4 Cb45
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 76 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
3.
YCbCr 4:4:4 with 16bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 16bit Output, Y First, Cb/B First
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb0 X Cr0 Y1 Cb1 X Cr1 Y2 Cb2 X Cr2 Y3 Cb3 X Cr3 Y4 Cb4 X Cr4
QCIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X Y0 Cb0 X Cr0 Y1 Cb1 X Cb1 X X X X X X X X Y4 Cb4 X Cr4
4.
RGB 565 with 8bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 8bit Output, Cb/B First, RGB565
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 RG4 GB4
QCIF Mode Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG1 GB1 X X X X RG4 GB4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 77 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
5.
RGB 565 with 16bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 16bit Output, Cb/B First, RGB565
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 RG4 GB4
QCIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X RG0 GB0 RG1 GB1 X X X X RG4 GB4
6.
RGB 4:4:4 with 16bit output
Register bit configurations Sensor Control A : CIF Mode or QCIF Mode Output Format : 16bit Output, Cb/B First, RGB4:4:4
MCLK HSYNC CIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X G0 B0 X R0 G1 B1 X R1 G2 B2 X R2 G3 B3 X R3 G4 B4 X R4
QCIF Mode Video Clock & Output Data CLK Y[7:0] C[7:0] X X G0 B0 X R0 G1 B1 X R1 X X X X X X X X G4 B4 X R4
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 78 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Bayer Data Format
SCTRA[2:0] is set to Bayer mode - When Bayer output mode is selected, Window Width x Window Height raw image data are produced with the following sequence. After VSYNC goes low state, the first HSYNC line of a frame is activated with B pixel data appearing first when both of Column Start Address and Row Start Address are even.
VCLK
HSYNC Y[7:0] Even Line Y[7:0] Odd Line
X
B
G
B
G
B
G
X
G
R
G
R
G
R
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 79 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
I2C Chip Interface
The serial bus interface consists of the SDA(serial data) and SCK(serial clock) pins. HV7151SP sensor can operate only as a slave. The SCK only controls the serial interface. However, MCLK should be supplied and RESET should be high signal during controlling the serial interface. The Start condition is that logic transition (High to Low) on the SDA pin while the SCK pin is at high state. The Stop condition is that logic transition (Low to High) on the SDA pin while the SCK pin is at high state. To generate Acknowledge signal, the Sensor drives the SDA low when the SCK pin is at high state. Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an Acknowledge. The most significant bit of the byte should always be transmitted first.
SDA SCK START
MSB
LSB
1
2
8
9 ACK
1
2
8
9 ACK STOP
Register Write Sequences
One Byte Write
S *1
22H *2
A *3
01H *4
A *5
04H *6
A *7
P *8
Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 04H [Video Mode : VGA] *7. Read: acknowledge from sensor *8. Drive: I2C stop condition
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 80 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Multiple Byte Write using Auto Address Increment S *1
22H *2
A *3
0cH *4
A *5
03H *6
A *7
60H *8
A *9
P *10
Set "AE Integration Step High/Low" register as 5161H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 0cH [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Window Height Upper] *7. Read: acknowledge from sensor *8. Drive: 60H [Window Height Lower] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition
Register Read Sequence
S
*1
22H
*2
A
*3
1cH
*4
A
*5
S
*6
23H
*7
A
*8
Data of 07H
*9
A
P
*10 *11
Read "Reset Level Clamp" register from HV7151SP *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 1cH [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read " Reset Level Clamp" from sensor *10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 81 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AC/DC Characteristics
Absolute Maximum Ratings
Symbol Viopp Vdpp Vapp Vipp Top Tst Parameter I/O block supply voltage Internal digital supply voltage Analog supply voltage Input signal voltage Operating Temperature Storage Temperature Units Volts Volts Volts Volts C C Min. -0.3 -0.3 -0.3 -0.3 -10 -30 Max. 3.3 2.5 2.5 3.3 50 80
Caution: Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
Symbol Vio Vdd Vih Vil Voh Vol Ioh Iol Ta Parameter I/O block supply voltage Internal operation supply voltage Input voltage logic "1" Input voltage logic "0" Output voltage logic "1" Output voltage logic "0" Output High Current Output Low Current Ambient operating temperature Units Volt Volt Volt Volt Volt Volt mA mA Celsius -10 Min. 2.3 1.6 2.3 0 2.15 Max. 2.8 2.0 2.5 0.8 Vio 0.4 -4 4 50 6.5 6.5 60 60 60 60 Load[pF] Notes
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 82 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
AC Operating Conditions
Symbol Parameter Max Operation Frequency 1) PLL off : 38.4 2) PLL on : MCLK Main clock frequency Units Notes
38.4 (Re ference Divisor ) ( Feedback Divisor )
MHz
1,2,3
SCK 1.
I2C clock frequency
400
KHz
4
MCLK may be divided by internal clock division logic for easy integration with high speed video codec system.
2. 3. 4.
Reference Divider and Feedback Divider is registers a3h and a4h, a5h, respectively. Frame Rate : 15 frames/sec at 38.4Mhz and PLL off , HBLANK = 208, VBLANK = 8 SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section
Output AC Characteristics
All output timing delays are measured with output load 60[pF]. Output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, video output signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec.
VCLK
HSYNC
Y/C[7:0]
X
Data 0
Data 1
Data 2
Data 3
3ns
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 83 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
I2C Bus Timing
stop
start
start
stop
SDA
tr tbuf tf tlow thd;sta
SCK
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
Parameter SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of SCK/SDA
Symbol fsck tbuf thd;s ta tlow thigh tsu;s ta thd;dat tsu;dat tr tf tsu;s to Cb
Min. 0 1.2 1.0 1.2 1.0 1.2 0.1 250 1.2 -
Max. 400 250 300 -
Unit KHz us us us us us us ns ns ns us pf
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 84 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Electro-Optical Characteristics
Parameter Sensitivity Dark Signal Dark Shading Output Signal Shading Output Saturation Signal Power Consumption (Normal Mode) Units mV / luxsec mV/ sec mV/sec % mV mW Min. Typical 1175 TBD TBD TBD 610 60 600 Max. Target 2200 Under 1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 85 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Package information
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 86 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 87 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
Reference Circuit Information
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 88 2003 Hynix Semiconductor Inc.
Confidential
HV7151SP CMOS Image Sensor With Image Signal Processing
MEMO
Hynix Semiconductor Inc. System IC SBU
* Contact Point *
MT Marketing Team
15Floor, Hynix Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea Tel: 82-2-3459-5579 Fax: 82-2-3459-5580 E-mail : suyeon.moon@hynix.com
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 89 2003 Hynix Semiconductor Inc.

▲Up To Search▲

Price & Availability of HV7151SP

	To Download HV7151SP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .