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HM64YLB36514 Series
16M Synchronous Late Write Fast Static RAM (512-kword x 36-bit, Register-Latch Mode)
REJ03C0039-0001Z Preliminary Rev.0.10 May.15.2003
Description
The HM64YLB36514 is a synchronous fast static RAM organized as 512-kword x 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device.
Features
* 2.5 V 5% operation and 1.5 V (VDDQ) * 16M bit density * Internal self-timed late write * Byte write control (4 byte write selects, one for each 9-bit) * Optional x18 configuration * HSTL compatible I/O * Programmable impedance output drivers * Differential pseudo-HSTL clock inputs * Asynchronous G output control * Asynchronous sleep mode * FC-BGA 119pin package with SRAM JEDEC standard pinout * Limited set of boundary scan JTAG IEEE 1149.1 compatible * Protocol: Single differential clock register-latch mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications.
Rev.0.10, May.15.2003, page 1 of 22
HM64YLB36514 Series
Ordering Information
Type No. HM64YLB36514BP-6H Organization 512k x 36 Access time 5.5 ns Cycle time Package 6.5 ns 119-bump 1.27 mm 14 mm x 22 mm BGA (BP-119E)
Pin Arrangement
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc7 DQc5 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd5 DQd7 NC NC VDDQ 2 SA14 SA15 SA16 DQc8 DQc6 DQc4 DQc2 DQc0 VDD DQd0 DQd2 DQd4 DQd6 DQd8 SA10 NC TMS 3 SA13 SA12 SA11 VSS VSS VSS SWEc VSS VREF VSS SWEd VSS VSS VSS M1 SA18 TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SWE SA17 SA0 VDD SA3 TCK 5 SA6 SA5 SA4 VSS VSS VSS SWEb VSS VREF VSS SWEa VSS VSS VSS M2 SA2 TDO 6 SA7 SA9 SA8 DQb8 DQb6 DQb4 DQb2 DQb0 VDD DQa0 DQa2 DQa4 DQa6 DQa8 SA1 NC NC 7 VDDQ NC NC DQb7 DQb5 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa5 DQa7 NC ZZ VDDQ
(Top view)
Rev.0.10, May.15.2003, page 2 of 22
Block Diagram
HM64YLB36514 Series
SA0 to SA18
Write add. reg.
Read add. reg.
1 0 Memory array (way0) 512k x 36
SA0 to SA18 compare
Rev.0.10, May.15.2003, page 3 of 22
Match0
01
59-N
SWEx 1st reg. SWEx 2nd reg. Output latch Byte write control
(x: a to d)
Din reg.
55
SS reg. SWE reg.
59Impedance control
Output enable
K
/
ZQ
DQxn (x: a to d, n: 0 to 8)
HM64YLB36514 Series
Pin Descriptions
Name VDD VSS VDDQ VREF K K SS SWE SAn SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC I/O type Supply Supply Supply Supply Input Input Input Input Input Input Input Input Input I/O Input Input Input Input Output M2 VSS Descriptions Core power supply Ground Output power supply Input reference, provides input reference voltage Clock input, active high Clock input, active low Synchronous chip select Synchronous write enable Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection 1 x: a to d n: 0 to 8 n: 0 to 18 x: a to d Notes
M1 VDD
Protocol Synchronous register to latch operation
Notes 2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 RQ 300 . If ZQ = VDDQ or open, output buffer impedance will be maximum. 2. There is 1 protocol with mode control input pins (M1, M2). These mode pins are to be tied either VDD or VSS respectively. These mode pins are set at power-up and will not change the states during the SRAM operates. This SRAM is tested only in the synchronous register to latch operation.
Rev.0.10, May.15.2003, page 4 of 22
HM64YLB36514 Series
Truth Table
ZZ H L SS x H G x x SWE x x SWEa x x SWEb x x SWEc x x SWEd x x K x L-H K x H-L
Operation DQ (n) DQ (n+1)
Sleep mode Dead (not selected) Dead (dummy read) Read
High-Z High-Z
High-Z x
L
x
H
H
x
x
x
x
x
x
High-Z
High-Z
L
L
L
H
x
x
x
x
L-H
H-L
DOUT (a, b, c, d) 0 to 8 High-Z
x
L
L
x
L
L
L
L
L
L-H
H-L
Write a, b, c, d byte Write b, c, d byte Write a, c, d byte Write a, b, d byte Write a, b, c byte Write c, d byte Write a, d byte Write a, b byte Write b, c byte Write d byte Write c byte Write b byte Write a byte
DIN (a, b, c, d) 0 to 8 DIN (b, c, d) 0 to 8 DIN (a, c, d) 0 to 8 DIN (a, b, d) 0 to 8 DIN (a, b, c) 0 to 8 DIN (c, d) 0 to 8 DIN (a, d) 0 to 8 DIN (a, b) 0 to 8 DIN (b, c) 0 to 8 DIN (d) 0 to 8 DIN (c) 0 to 8 DIN (b) 0 to 8 DIN (a) 0 to 8
L
L
x
L
H
L
L
L
L-H
H-L
High-Z
L
L
x
L
L
H
L
L
L-H
H-L
High-Z
L
L
x
L
L
L
H
L
L-H
H-L
High-Z
L
L
x
L
L
L
L
H
L-H
H-L
High-Z
L L L L L L L L
L L L L L L L L
x x x x x x x x
L L L L L L L L
H L L H H H H L
H H L L H H L H
L H H L H L H H
L L H H L H H H
L-H L-H L-H L-H L-H L-H L-H L-H
H-L H-L H-L H-L H-L H-L H-L H-L
High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
Notes: 1. H: VIH, L: VIL, x: VIH or VIL 2. SWE, SS, SWEa to SWEd, and SA are sampled at the rising edge of K clock.
Rev.0.10, May.15.2003, page 5 of 22
HM64YLB36514 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable value of RQ to guarantee impedance matching with a tolerance of 15% is 250 . If the status of ZQ pin is open, output impedance is maximum value. Maximum impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock, to guarantee the proper update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance to be completely updated.
Rev.0.10, May.15.2003, page 6 of 22
HM64YLB36514 Series
Absolute Maximum Ratings
Parameter Input voltage on any pin Core supply voltage Output supply voltage Operating temperature Storage temperature Output short-circuit current Latch up current Package junction to top thermal resistance Package junction to board thermal resistance Symbol VIN VDD VDDQ TOPR TSTG IOUT ILI J-top J-board Rating -0.5 to VDDQ + 0.5 -0.5 to +3.13 -0.5 to +2.1 0 to +85 -55 to +125 25 200 6.5 12 Unit V V V C C mA mA C/W C/W 5 5 Notes 1, 4 1 1, 4
Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the instantaneous value of VDDQ. 5. See figure below.
J-top
J-board
Thermocouple Thermo grease
Teflon block
Thermocouple
Water
Cold plate SRAM
Water
SRAM
Water JEDEC/2S2P BGA Thermal board
Cold plate JEDEC/2S2P Thermal board
Water BGA
Teflon block
Thermo grease
Rev.0.10, May.15.2003, page 7 of 22
HM64YLB36514 Series Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions (Ta = 0 to +85C)
Parameter Power supply voltage: core Power supply voltage: I/O Input reference voltage: I/O Input high voltage Input low voltage Clock differential voltage Clock common mode voltage Notes: 1. 2. 3. 4. Symbol VDD VDDQ VREF VIH VIL VDIF VCM Min 2.38 1.40 0.70 VREF + 0.15 -0.50 0.10 0.90 Typ 2.50 1.50 0.75 Max 2.63 1.60 0.80 VDDQ + 0.50 VREF - 0.15 VDDQ + 0.30 1.30 Unit V V V V V V V 1 4 4 2, 3 3 Notes
Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. Minimum differential input voltage required for differential input clock operation. See figure below. VREF = 0.75 V (typ).
Differential Voltage / Common Mode Voltage
VDDQ
VDIF VCM
VSS
Rev.0.10, May.15.2003, page 8 of 22
HM64YLB36514 Series
DC Characteristics (Ta = 0 to +85C, VDD = 2.5 V 5%)
Parameter Input leakage current Output leakage current Standby current VDD operating current, excluding output drivers Quiescent active power supply current Maximum power dissipation, including output drivers Symbol ILI ILO ISBZZ IDD IDD2 P Min Max 2 5 150 350 200 2.3 Unit A A mA mA mA W Notes 1 2 3 4 5 6
Parameter Output low voltage Output high voltage ZQ pin connect resistance Output "Low" current Output "High" current
Symbol VOL VOH RQ IOL IOH
Min VSS VDDQ - 0.4 (VDDQ/2)/{(RQ/5) - 15%} (VDDQ/2)/{(RQ/5) + 15%}
Typ 250
Max VSS + 0.4 VDDQ
Unit Notes V V 7 8
(VDDQ/2)/{(RQ/5) + 15%} mA 9, 11 (VDDQ/2)/{(RQ/5) - 15%} mA 10, 11
Notes: 1. 0 VIN VDDQ for all input pins (except VREF, ZQ, M1, M2 pin) 2. 0 VOUT VDDQ, DQ in high-Z 3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is guaranteed at +75C junction temperature. 4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle 5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz 6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer to determine electrical and package requirements for the SRAM device. 7. RQ = 250 , IOL = 6.8 mA 8. RQ = 250 , IOH = -6.8 mA 9. Measured at VOL = 1/2 VDDQ 10. Measured at VOH = 1/2 VDDQ 11. The total external capacitance of ZQ pin must be less than 7.5 pF.
Rev.0.10, May.15.2003, page 9 of 22
HM64YLB36514 Series
AC Characteristics (Ta = 0 to +85C, VDD = 2.5 V 5%)
Single Differential Clock Register-Latch Mode
HM64YLB36514BP -6H Parameter CK clock cycle time CK clock high width CK clock low width Address setup time Data setup time Address hold time Data hold time Clock high to output valid Clock low to output valid Clock low to output hold Clock low to output low-Z (SS control) Clock high to output high-Z Output enable low to output low-Z Output enable low to output valid Output enable high to output high-Z Sleep mode recovery time Sleep mode enable time Notes: 1. 2. 3. 4. 5. 6. Symbol tKHKH tKHKL tKLKH tAVKH tDVKH tKHAX tKHDX tKHQV tKLQV tKLQX tKLQX2 tKHQZ tGLQX tGLQV tGHQZ tZZR tZZE Min 6.5 1.2 1.2 0.4 0.4 1.0 1.0 1.7 0.5 0.5 0.5 0.5 0.1 20.0 Max 5.5 2.3 2.3 2.3 2.3 15.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 4, 6 1, 3, 6 1, 4, 6 1, 4 1, 3 5 1, 3, 5 1 2 2 Notes
See figure in "AC Test Conditions". Parameters may be guaranteed by design, i.e., without tester guardband. Transitions are measured 50 mV of output high impedance from output low impedance. Transitions are measured 50 mV from steady state voltage. When ZZ is switching, clock input K must be at the same logic level for the reliable operation. Minimum value is verified by design and tested without guardband.
Rev.0.10, May.15.2003, page 10 of 22
HM64YLB36514 Series
Timing Waveforms
Read Cycle-1
tKHKH K, tKHKL tKLKH
K
tAVKH tKHAX A2 tAVKH tKHAX A3 A4 A1
SA
SS
tAVKH tKHAX
SWE SWEx
DQ Q0
tKHQV Q1 tKLQX tKLQV Q2 Q3
Note: ZZ = VIL
Read Cycle-2 (SS Controlled)
tKHKH K, K tAVKH SA A1 tKHAX A4 tKHKL tKLKH
A3 tAVKH tKHAX
SS SWE SWEx
tKHQV DQ Q0 tKHQZ Q1
tAVKH tKHAX
tKLQX2 Q3
Note: ZZ = VIL
Rev.0.10, May.15.2003, page 11 of 22
HM64YLB36514 Series Read Cycle-3 (G Controlled)
tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH
SS
tAVKH tKHAX
SWE SWEx G
tGHQZ DQ Q0 Q1 Q2 tGLQV tGLQX Q3
Note: ZZ = VIL
Write Cycle
tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH
SS
tAVKH tKHAX tKHAX
SWE
tAVKH
SWEx G
tDVKH DQ D0 D1 tKHDX D2 D3
Note: ZZ = VIL
Rev.0.10, May.15.2003, page 12 of 22
HM64YLB36514 Series Read-Write Cycle-1
READ tKHKH K, K tAVKH SA A1 A2 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A6 A7 READ tKHKL tKLKH WRITE READ DEAD WRITE (SS control)
SS
tAVKH
SWE
tAVKH
SWEx G
DQ tKHQV Q0 tKLQX tKLQV Q1 tGHQZ tDVKH tKHDX tGLQV Q2 D3 Q4 tGLQX tKHQZ D6
Note: ZZ = VIL
Read-Write Cycle-2
READ tKHKH K, K tAVKH SA A1 A2 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A5 A6 A7 READ tKHKL tKLKH WRITE READ DEAD WRITE (SS control)
SS
tAVKH
SWE
tAVKH
SWEx G
DQ
Low fixed
tKHQV Q0 tKLQX tKLQV Q1
tKHQZ tDVKH tKHDX Q2 D3 Q4 tKLQV tKHQZ D6
Note: G, ZZ = VIL During this period DQ pins are in the output state so that the input signal of opposite phase to the outputs must not be applied.
Rev.0.10, May.15.2003, page 13 of 22
HM64YLB36514 Series ZZ Control
tKHKH K, K tAVKH SA tAVKH A1 tKHAX tKHAX tKHAX tKHKL tKLKH
SS
tAVKH
SWE SWEx
ZZ Sleep active DQ tZZR Sleep off Q1 tZZE Sleep active
Rev.0.10, May.15.2003, page 14 of 22
HM64YLB36514 Series
Input Capacitance (VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25C, f = 1 MHz)
Parameter Input capacitance Clock input capacitance I/O capacitance Symbol CIN CCLK CIO Min Max Unit Pin name 4 5 5 pF pF pF SAn, SS, SWE, SWEx K, K DQxn Notes 1, 3 1, 2, 3 1, 3
Notes: 1. This parameter is sampled and not 100% tested. 2. Exclude G 3. Connect pins to GND, except VDD, VDDQ, and the measured pin.
AC Test Conditions
Parameter Input and output timing reference levels Input signal amplitude Input rise / fall time Clock input timing reference level VDIF to clock VCM to clock Output loading conditions Note: Parameters are tested with RQ = 250 and VDDQ = 1.5 V. Symbol VREF VIL, VIH tr, tf Conditions 0.75 0.25 to 1.25 0.5 (10% to 90%) Differential cross point 0.75 1.10 See figure below V V Unit V V ns Note
Output Loading Conditions
16.7 16.7 DQ 16.7 50 5 pF 50 5 pF 50 0.75 V 50 0.75 V
0.75 V
Rev.0.10, May.15.2003, page 15 of 22
HM64YLB36514 Series
Boundary Scan Test Access Port Operations
Overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 1990. But does not implement all of the functions required for 1149.1 compliance the HM64YLB series contains a TAP controller. Instruction register, boundary scans register, bypass register and ID register.
Test Access Port Pins
Symbol I/O TCK TMS TDI TDO Name Test clock Test mode select Test data in Test data out
Note: This device does not have a TRST (TAP reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected. To test boundary scan, the ZZ pin needs to be kept below VREF - 0.4 V.
TAP DC Operating Characteristics (Ta = 0 to +85C)
Parameter Boundary scan input high voltage Boundary scan input low voltage Boundary scan input leakage current Boundary scan output low voltage Boundary scan output high voltage Boundary scan output leakage current Notes: 1. 2. 3. 4. 0 VIN 3.6 V for all logic input pins IOL = 2 mA at VDD = 2.5 V. IOH = -2 mA at VDD = 2.5 V. 0 VOUT VDD, TDO in high-Z Symbol VIH VIL ILI VOL VOH ILO Min 1.4 V -0.3 V -10 A 2.1 V -5 A Max 3.6 V 0.8 V +10 A 0.2 V +5 A 1 2 3 4 Notes
Rev.0.10, May.15.2003, page 16 of 22
HM64YLB36514 Series
TAP AC Operating Characteristics (Ta = 0 to +85C)
Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high to TDI don't care TCK low to TDO unknown TCK low to TDO valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQX tTLQV Min 67 30 30 10 10 10 10 10 10 0 Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions (VDD = 2.5 V)
Temperature Input timing measurement reference level Input pulse levels Input rise/fall time Output timing measurement reference level Test load termination supply voltage (VT) Output load Boundary Scan AC Test Load
VT DUT 50 Z0 = 50 TDO
0C Ta +85C 1.1 V 0 to 2.5 V 1.5 ns typical (10% to 90%) 1.25 V 1.25 V See figure below
Rev.0.10, May.15.2003, page 17 of 22
HM64YLB36514 Series
TAP Controller Timing Diagram
tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV TDO tCS tCH RAM ADDRESS tTLQX tTHTL tTLTH
Test Access Port Registers
Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 70 bits Symbol IR [2:0] BP ID [31:0] BS [70:1] Note
TAP Controller Instruction Set
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction SAMPLE-Z IDCODE SAMPLE-Z BYPASS SAMPLE BYPASS PRIVATE BYPASS Do not use. They are reserved for vendor use only Tristate all data drivers and capture the pad value Operation Tristate all data drivers and capture the pad value
Note: This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1.
Rev.0.10, May.15.2003, page 18 of 22
HM64YLB36514 Series
Boundary Scan Order (HM64YLB36514)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Bump ID 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Signal name M2 SA0 SA3 SA1 SA2 ZZ DQa8 DQa7 DQa6 DQa5 DQa4 DQa2 DQa3 DQa0 DQa1 SWEa K K G SWEb DQb1 DQb0 DQb3 DQb2 DQb4 DQb5 DQb6 DQb7 DQb8 SA7 SA8 SA4 SA6 SA9 SA5 Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Bump ID 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R Signal name SA12 SA15 SA13 SA11 SA16 SA14 DQc8 DQc7 DQc6 DQc5 DQc4 DQc2 DQc3 DQc0 DQc1 SWEc ZQ SS NC NC SWE SWEd DQd1 DQd0 DQd3 DQd2 DQd4 DQd5 DQd6 DQd7 DQd8 SA18 SA10 SA17 M1
Rev.0.10, May.15.2003, page 19 of 22
HM64YLB36514 Series
Notes: 1. Bit#1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "Place Holder". Place holder registers are internally connected to VSS. 3. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite logic levels for the reliable operation. 4. ZZ must remain VIL during boundary scan. 5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results. 6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.
ID Register
Revision number (31:28) 0000 Device density and configuration (27:18) 0011100100 Vendor definition (17:12) 000000 Vendor JEDEC code (11:1) 00000000111 Start bit (0) 1
Part HM64YLB36514
TAP Controller State Diagram
1
Test-logicreset 0
0
Run-test/ idle
1
SelectDR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
SelectIR-scan 0 1 Capture-IR 0 0 Shift-IR 1
1
0 1
1
Exit1-IR 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0
0
Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high for at least five rising edges of TCK.
Rev.0.10, May.15.2003, page 20 of 22
HM64YLB36514 Series
Package Dimensions
HM64YLB36514BP Series (BP-119E)
Preliminary
Unit: mm
0.20
4x
C A
0.35 C
0.20 C 7654321
14.00
Y A B C D E F G H J K L M N P R T U
22.00
18.04
B
11.08
1.27
1.27
0.69 0.08
119 x 0.88 0.06 0.30 M C A B 0.15 M C
Details of the part Y
2.02 0.22
(0.15)
Package Code JEDEC JEITA Mass (reference value)
BP-119E -- -- 1.1 g
Rev.0.10, May.15.2003, page 21 of 22
HM64YLB36514 Series
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Rev.0.10, May.15.2003, page 22 of 22

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