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HD66503
(240-Channel Common Driver with Internal LCD Timing Circuit)
Description
The HD66503 is a common driver for liquid crystal dot-matrix graphic display systems. This device incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (alternating signals and frame synchronizing signals) required for the liquid crystal display. It also achieves low current consumption of 100 A through the CMOS process. Combined with the HD66520, a 160-channel column driver with an internal RAM, the HD66503 is optimal for use in displays for portable information tools.
Features
* * * * * * * * * * * * LCD timing generator: 1/120, 1/240 duty cycle internal generator Alternating signal waveform generator: Pin programmable 2 to 63 line inversion Recommended display duty cycle: 1/120, 1/240 (master mode): 1/120 to 1/240 (slave mode) Number of LCD driver: 240 Power supply voltage: 2.7 to 5.5V High voltage: 8 to 28-V LCD drive voltage Low power consumption: 100 A (during display) Internal display off function Oscillator circuit with standby function: 130 kHz (max) Display timing operation clock: 65 kHz (max) (operating at 1/2 system clock) Package: 272-pin TCP CMOS process
Ordering Information
Type No. HD66503TA0 HD66503TB0 TCP Straight TCP Folding TCP Outer Lead Pitch (m) 200 200
927
HD66503
Pin Arrangement
X240 X239 X238 X237 X236 X235 X234 X233 X232 X231
1 2 3 4 5 6 7 8 9 10
272 271 270 269 268 267 266 265 264 263 262 261 260 259 258
V2R V5R V6R V1R VEER VCC2 M/S DOC FLM CL1 M RESET DISPOFF DUTY MEOR
Top View
257 256 255 254 253 252 251 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 231 232 233 234 235 236 237 238 239 240 250 249 248 247 246 245 244 243 242 241
MWS0 MWS1 MWS2 MWS3 MWS4 MWS5 SHL GND C R CR VCC1 VEEL V1L V6L V5L V2L
Note : This figure does not specify the tape carrier package dimensions.
928
HD66503
Pin Description
Classification Power supply Symbol VCC1, VCC2 GND VEEL, VEER V1L, R V2L, R V5L, R V6L, R Control signals M/6 Pin No. 246 267 250 245 268 244 269 241 272 242 271 243 270 266 Pin Name VCC GND VEE V1 V2 V5 V6 I/O Power supply Power supply Power supply Input Input Input Input Number of Pins Functions 2 1 2 2 2 2 2 1 Controls the initiation and termination of the LCD timing generator. In addition, the input/output is determined of 4 signal pins: display data transfer clock (CL1); first line marker (FLM); alternating signal (M); and display off control ('2&). See Table 1 for details. Selects the display duty cycle. Low level: 1/120 display duty ratio High level: 1/240 display duty ratio The number of line in the line alternating waveform is set during master mode. The number of lines can be set between 10 and 63. When using the external alternating signal or during slave mode, set the number of lines to 0. See Table 2. During master mode, the signals alternating waveform output from pin M is selected. During low level, the line alternating waveform is output from pin M. During high level, pin M outputs an EOR (exclusive OR) waveform between a line alternating waveform and frame alternating waveform. Set the pin to low during slave mode. See Table 3. VCC-VEE: LCD drive circuits power supply LCD drive level power supply See Figure 1. VCC-GND: logic power supply
Master/slave Input
DUTY
259
Duty
Input
1
MWS0 to MWS5
257 256 255 254 253 252 258
MWS0 MWS1 MWS2 MWS3 MWS4 MWS5
Input
6
MEOR
M Exclusive- Input OR
1
929
HD66503
Classification Control signals Symbol CR, R, C Pin No. 247 248 249 261 Pin Name CR R C Reset Input I/O Number of Pins Functions 3 These pins are used as shown in Figure 4 in master mode, and as shown in Figure 5 in slave mode. The following initiation will be proceeded by setting to initiation. 1) Stops the internal oscillator or the external oscillator clock input. 2) Initializes the counters of the liquid crystal display timing generator and alternating signal (M) generator. 3) Set display off control output ('2&) to low and turns off display. After reset, display off control output ('2&) will stay low for four more frame cycles (four clocks of FLM signals) to prevent error display at initiation. The electrical characteristics are shown in Table 4. See Figure 2. However, when reset is performed during operation, RAM data in the HD66520 which is used together with the HD66503 may be destroyed. Therefore, write data to the RAM again. The bidirectional shift register shifts data at the falling edge of CL1. During master mode, this pin-outputs a data transfer clock with a two times larger cycle than the internal oscillator (or the cycle of the external clock) with a duty of 50%. During slave mode, this pin inputs the external data transfer clock. During master mode, pin FLM outputs the first line marker. During slave mode, this pin inputs the external data first line marker. The shift direction of the first line marker is determined by DUTY and SHL signal as follows. Set signal DUTY to high during slave mode. See Table 5. Pin M inputs and outputs the alternating signal of the LCD output.
5(6(7
1
LCD timing
CL1
263
Clock 1
I/O
1
FLM
264
First line marker
I/O
1
M
262
M
I/O
1
930
HD66503
Classification LCD timing Symbol SHL Pin No. 251 Pin Name Shift left I/O Input Number of Pins Functions 1 Pin SHL switches the shift direction of the shift register. Refer to FLM for details. Turns off the LCD. During master mode, liquid crystal drive output X1 to X240 can be set to level V1 by setting the pin to low. By setting the HD66520 to level V1 in the same way, the data on the display can be erased. During slave mode, set ',632)) high. Controls the display-off function. During master mode, pin '2& becomes an output pin and controls display off after reset and display off according to signal ',632)). In this case, connect this signal to the HD66520's pin ',632)). During slave mode, pin '2& becomes an input pin for display off control signal. In this case, connect this signal to the master HD66503's pin '2&. Selects one from among four levels (V1, V2, V5, and V6) depending on the combination of M signal and display data. See Figure 3.
',632))
260
Display off
Input
1
'2&
265
Display off control
I/O
1
LCD drive output
X1 to X240
240 to 1
X1 to X240
Output 240
Note: 30 input/outputs (excluding driver block)
931
HD66503
V1 V6 V5 V2
Figure 1 LCD Drive Levels
2.7V treset tr 0.8 VCC 0.2 VCC
VCC
RESET
Figure 2 Reset Pin Operation
M signal Display data Output level 1 V2 1 0 V6 1 V1 0 0 V5
Figure 3 LCD Drive Output
932
HD66503
Table 1
M/$ $ H L
M/$ Signal Status $
Mode Master Slave LCD Timing Generator 1/120 or 1/240 duty cycle control Stop CL1, FLM, M, Output Input
Input/Output State
Table 2
MSW0 to MSW5 Signals Status
MWS4 0 0 0 0 to 1 MWS3 0 0 0 0 to 1 MWS2 0 0 0 0 to 1 MWS1 0 0 1 1 to 1 MWS0 0 1 0 1 to 1 Line Alternating Waveform -- Disable 2-line alternation 3-line alternation to 63-line alternation Pin M State Input Output
Number of Lines MWS5 0 1 2 3 to 63 0 0 0 0 to 1
Table 3
Mode Master
MEOR Signal Status
MEOR H L Types of Alternating Waveforms Output by Pin M Line alternating waveform frame alternating waveform Line alternating waveform --
Slave
L
Table 4
Item Reset time Rise time
Power Supply Conditions
Symbol treset tr Min 1.0 -- Typ -- -- Max -- 200 Unit s ns
Table 5
Mode Master
FLM Status Control
DUTY H SHL H L L H L Shift Direction of First Line Marker X240 X1 X1 X240 X120 X1, X240 X121 X1 X120, X121 X240 X240 X1 X1 X240
Slave
H
H L
933
HD66503
Internal Block Diagram
X1 to X240
V1L V6L V5L V2L
LCD driver D1 to D240 Level shifter L1 to L240 Bidirectional shift register
DUTYS CL1P FLMP
V1R V6R V5R V2R
MLS
VEER
VEEL VCC1 VCC2 GND
Level shifter
MP DOCP
SHLS
RESET FLMM
LCD timing generator
CL1M FLMM
FLM1 CL1M
AC switching signal generator
MM MW0 DOCM
MWS5S to MWS0S
Display off controller
MEORS DISPS
CRP MSS
CR oscillator
M/S switcher
6
CR
R
C
CL1
FLM
M
DOC
M/S DUTY MEOR SHL MWS5 DISPOFF to MWS0
934
HD66503
1. CR Oscillator: The CR oscillator generates the HD66503 operation clock. During master mode, since the operation clock is needed, connect oscillation resistor Rf with oscillation capacitor Cf as follows. When the external clock is used, input external clock to pin CR and open pins C and R (Figure 4). When using the HD66503 during slave mode, the operation clock will not be needed; therefore, connect pin CR to VCC and open pins C and R (Figure 5). 2. Liquid Crystal Timing Generator: The liquid crystal timing generator creates various signals for the LCD. During master mode (M/6 = VCC), the generator operates the HD66503's internal circuitry as a common internal driver using the generated LCD signals. In addition, signals CL1, M, and '2& created by this generator can synchronously display data on a liquid crystal display by inputting them into the RAM-provided segment driver HD66520 used together with HD66503. During slave mode (M/6 = GND), this generator stops; the slave HD66503 operates based on signals CL1, M, '2&, and FLM generated by the master HD66503. 3. M/$ Switcher: Controls the input and output of LCD signals CL1, FLM, M, and '2&. $ This circuit outputs data when M/6 = VCC (master mode) and inputs data when M/6 = GND (slave mode). 4. Alternating Signal Generator: Generates the alternating signal for the liquid crystal display. Since the alternating signal decreases cross talk, it can alternate among 2 to 63 lines. The number of lines are specified with pins MWS0 to MWS5 is set to either VCC or GND. Moreover, the alternating signal can be externally input by grounding pins MWS0 to MWS5. In this case, the alternating signal is input from pin M.
C
R
CR External clock
C
R Rf
CR
OPEN OPEN
Cf
Figure 4 Oscillator Connection in Master Mode
C
R
CR
OPEN OPEN
VCC
Figure 5 Oscillator Connection in Slave Mode
935
HD66503
5. Display Off Control Circuit: Controls display-off function by using external display off signal ',636 and automatic display off signal FLMM generated by the liquid crystal timing generator. Automatic display off signal FLMM is an internal signal that is used to turn off the display in four frames after signal reset is released. As a result, it is possible to turn off display using the display off signal that is sent randomly from an external LSI and automatically prevent incorrect display after reset release. 6. Bidirectional Shift Register: This is a 240-bit bidirectional shift register. This register can change the shift direction using signal SHL. During master mode, the scan signal of the common driver can be generated by sequentially shifting first line marker signal FLM generated internally. During slave mode, a scan signal is generated by sequentially shifting first line marker signal FLM input from pin FLM. 7. Level Shifter: Boosts the logic signal to a high voltage signal for the LCD. 8. LCD Drive Circuit: One of the LCD levels V1, V2, V5, and V6 are selected and output via pin X according to the combination of the data in the bidirectional shift register and signal M. Table 6 Output Level of LCD Circuit
M 1 1 0 0 Output Level V2 V6 V1 V5
Data in the Shift Register 1 0 1 0
936
HD66503
Internal Function Description 1. Generation of Signals CL1 and FLM: Signal CL1 shifts the scanning signal of the common driver. It is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock CR. FLM is a clock signal that is output once every 240 CL1 clock cycles for a duty of 1/240 (DUTY = VCC), and every 120 CL1 clock cycles for a duty of 1/120 (DUTY = GND). 2. Generation of Signal M: Signal M alternates current in the LCD. It alternates the current to decrease cross talk after a certain number of lines ranging from 2 to 63 lines. The number of lines can be specified with pins MWS0 to MWS5 by setting each pin to either VCC or GND (H or L). In addition, when pin MEOR is connected to GND, signal M is a simple line alternating waveform, and when pin MEOR is connected to VCC, signal M is an EOR (exclusive OR) of line alternating waveform and frame alternating waveform.
CR CL1 FLM 240 (120) 1 2
Figure 6 Generation of Signals CL1 and FLM
(When MWS0 to MWS5 = 6)
CL1
1 M (MEOR = GND) M (MEOR = VCC) FLM
2
3
4
5
6
1
2
Figure 7 Generation of Signal M
937
HD66503
3. Auto Display-Off Control: This functions prevents incorrect display after reset release. The display is turned off four frames following after reset release. In addition, the display off control signal shown in Figure 8 is output by pin '2&. This pin is connected to pin ',632)) of the HD66520.
RESET FLM DOC 1 2 3 4 5 6
Figure 8 Automatic Display-Off Control Function
938
HD66503
Application Example
Outline of HD66503 System Configuration The HD66503 system configuration is outlined in Figures 9 and 10. Refer to the connection list (Table 7) for connection details. * When a single HD66503 is used to configure a small display (Figure 9) * When two HD66503s are used to configure a large display (Figure 10)
HD66520 No. 1 LCD No. 1 COM1 to COM240 Note: One HD66503 drives common signals and supplies timing signal to the HD66520. When using an external clock When using the internal oscillator Refer to connection list A Refer to connection list D
Figure 9 When Using a Single HD66503
HD66520 LCD COM1 No. 1 to COM240 COM241 to No. 2 COM480 HD66520 Note: Upper and lower displays are driven by separate HD66503s to ensure display quality. No. 1 operates in master mode, and No. 2 operates in slave mode. Lower display Upper display No. 1 When using the internal oscillator When using an external clock Refer to connection list B Refer to connection list E No. 2 Refer to connection list C Refer to connection list C
Figure 10 When Using Two HD66503s
939
940
Connection Example M/S DUTY H Rf Cf Rf Cf -- -- From CL1 From FLM From M of of HD66503 of HD66503 HD66503 To CL1 of HD66520 HD66503 To FLM of HD66520 HD66503 To M of HD66520 HD66503 To DOC of HD66503 T0 DISPOFF of HD66520 From DOC of HD66503 H L To CL1 of HD66520 To FLM of HD66520 To M of HD66520 To DISPOFF of HD66520 L H From controller Cf From controller Cf H H Rf Rf MEOR RESET DISPOFF CR R C CL1 FLM M DOC A H MWS0, MWS1, MWS2, MWS3, MWS4, MWS5 SHL X1 to X240 COM1 to COM240 Sets the number of lines for alternating the current H From CPU or external reset circuit COM240 to COM1 COM1 to COM240
Table 7
HD66503
HD66503 Connection List
HD66503 Connection List
B
H
H
Sets the number of lines for alternating the current L
From CPU or external reset circuit
H L
COM240 to COM1 COM241 to COM480
C
L
H
Sets the number of lines for alternating the current H From controller From -- external oscillator -- To CL1 of HD66520 To FLM of HD66520
From CPU or external reset circuit
H To M of HD66520 To DISPOFF of HD66520 L
COM480 to COM241 COM1 to COM240
D
H
H
Sets the number of lines for alternating the current H From controller From -- external oscillator -- To CL1 of HD66520 HD66503
From CPU or external reset circuit
H To FLM of HD66520 HD66503 To M of HD66520 HD66503 To DOC of HD66503 To DISPOFF of HD66520 L
COM240 to COM1 COM1 to COM240
E
H
H
Sets the number of lines for alternating the current
From CPU or external reset circuit
H
COM240 to COM1
Notes: H = VCC (Fixed) L = GND (Fixed) "--" means "open" Rf: Oscillation resistor Cf: Oscillation capacitor
HD66503
Example of System Configuration (1)
Figure 11 shows a system configuration for a 240 x 160-dot LCD panel using segment driver HD66520 with internal bit-map RAM. All required functions can be prepared for liquid crystal display with just two chips except for liquid crystal display power supply circuit functions. Refer to Timing Chart (1) for details.
240 SHL LS0 LS1
seg1 seg2
LCD HD66520 (ID No. 0) 160
seg159 seg160 com1 com2
Line scan direction
com239 com240
X1 , X2, X3,......... X240
3 FLM, CL1, M / 1 / DOC DOC
LCD driver HD66503 / MWS0 to 5 6 / MEOR 1 / RESET 1 VCC
LCD display timing control circuit DISPOFF CR R C DUTY SHL M/S
V1, V2, V5, V6 V1, V2, V3, V4 1 16 / / A0 to A15 DB0 to DB7 CS, WE, OE DISPOFF
3 /
8 /
Power supply circuit
Figure 11 System Configuration (1)
941
HD66503
Example of System Configuration (2)
Figure 12 shows a system configuration for a 240 x 320-dot LCD panel using segment driver HD66520 with internal bit-map RAM. Refer to Timing Chart (1) for details.
240 SHL LS0 LS1
seg1 seg2
LCD HD66520 (ID No. 0)
seg159 seg160 seg161 seg162
HD66520 (ID No. 2)
seg319 seg320
VCC
X1, X2, X3, ......... X240
3 FLM, CL1, M / 1 DOC /
LCD driver HD66503 DOC LCD display timing control circuit DISPOFF CR R C DUTY SHL M/S / MWS0 to 5 6 / MEOR 1 / RESET 1 VCC
V1, V2, V5, V6 V1, V2, V3, V4 1 16 / / A0 to A15 DB0 to DB7 CS, WE, OE DISPOFF
3 /
8 /
Power supply circuit
Figure 12 System Configuration (2)
942
com239 com240
Line scan direction
SHL
LS0
LS1
com1 com2
320
Timing Chart (1)
10 lines M 10 lines 10 lines
10 lines
CR 240 1 2 10 11 12 20 21 22 120 121 122 130 131 132 CL1 FLM 140 141 142 240 1 2
X1 (COM1) V6 V1 V5 V6 V5
V6
V1 V5
X2 (COM2) V6 V5 V1 V6 V5
V6
V5 V1
Figure 13 Timing Chart (1)
X120 (COM120) V6 V5 V6 V2 V5 X121 (COM121) V6 V5 V6 V1 V5 X122 (COM122) V6 V5 V6 V5 V1 X240 V5 V6 V2 (COM240) V6 V5
V6
V5
V6
V5
V6
V5
V6
V2
V5
HD66503
943
HD66503
Example of System Configuration (3)
Figure 14 shows a system configuration for a 320 x 480-dot LCD panel using segment driver HD66520 with internal bit-map RAM. Refer to Timing Chart (2) for details.
A0 to A15 DB0 to DB7 CS, WE, OE
16/ 8/ 3/
VCC
FLM, CL1, M 3 / MWS0 to 5 / 6 MEOR /1 DISPOFF / 1 RESET / 1 LS0 LS1 SHL
HD66520 (ID No.0) 320
HD66520 (ID No.2)
LS1 LS0 SHL
1 / DOC CR R C DUTY SHL M/S DOC CR
seg2 seg1 com1 com2
seg160 seg159
seg162 seg161
seg320 seg319
X1, X2, X3, ......... X240
com239 com240 com241 com242 RESET DISPOFF
Line scan cirection
seg161 seg162
seg159 seg160
seg1 seg2
320 VCC
LS1 LS0 SHL
seg319 seg320
com479 com480
VCC
HD66520 (ID No.1)
HD66520 (ID No.3)
LS0 LS1 SHL
Power supply circuit
V1, V2, V5, V6
V1, V2, V3, V4
Figure 14 System Configuration (3)
944
480 VCC
HD66503 Master mode
LCD driver
LCD
X1, X2, X3, ......... X240
OPEN OPEN
R
HD66503 Slave mode
FLM, CL1, M MWS0 to 5 MEOR
LCD driver
C DUTY SHL M/S
Timing Chart (2)
10 lines M 10 lines 10 lines
10 lines
CR 480 1 2 10 11 12 20 21 22 240 241 242 250 251 252 CL1 FLM 260 261 262 480 1 2
X1 (COM1) V6 V1 V5 V6 V1 V5 V6 V5 V1 V6 V5 V1
V6
V1 V5
HD66503 No. 1 X2 (COM2) X240 V6 V2 V5 (COM240) V6 V2 V5
V6
V5 V1
Figure 15 Timing Chart (2)
X241 (COM241) V6 V1 V5 V6 V5 V1 V6 V1 V5 HD66503 No. 2 X242 (COM242) X480 V6 V2 V5 (COM480) V6 V5 V1 V6 V2 V5
V6 V2 V5
V6
V1 V5
V6
V5 V1
V6 V2 V5
HD66503
945
HD66503
Power Supply Circuit
+3V VCC1, VCC2
V1L, V1R R1 V6L, V6R
R1 V3L, V3R
R2 V4L, V4R
R1 V5L, V5R
R1
V2L, V2R
VEEL, VEER
Contrast -25V 0V GND
Note: The values of R1 and R2 vary with the LCD panel used. When the bias factor is 1/15, for example, the values of R1 and R2 can be determined as follows: R1 4R1 + R2 = 1 15
If R1 = 3 k, then R2 = 33 k
Figure 16 Power Supply Circuit
946
HD66503
Absolute Maximum Ratings
Item Power voltage Logic circuit LCD drive circuit Input voltage (1) Input voltage (2) Operating temperature Storage temperature Symbol VCC VEE VT1 VT2 Topr Tstg Ratings -0.3 to +7.0 VCC - 30.0 to VCC + 0.3 -0.3 to VCC + 0.3 VEE - 0.3 to VCC + 0.3 -20 to +75 -40 to +125 Unit V V V V C C Notes 2 5 2, 3 4, 5
Notes: 1. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability. 2. Measured relative to GND (0V). 3. Applies to all input pins except for V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R, and to input/output pins in high-impedance state. 4. Applies to pins V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. 5. Apply the same voltage to pairs V1L and V1R, V2L and V2R, V5L and V5R, V6L and V6R, and VEEL and VEER. It is important to preserve the relationships VCC1 = VCC2 V1L = V1R V6L = V6R V5L = V5R V2L = V2R VEEL = VEER
947
HD66503
Electrical Characteristics
DC Characteristics (VCC = 2.7 to 5.5V, VCC-VEE = 8 to 28V, GND = 0V, Ta = -20 to +75C)
Item Input high level voltage Input low level voltage Output high level voltage Output low level voltage Driver "on" resistance Input leakage current (1) Input leakage current (2) Operating frequency (1) Operating frequency (2) Oscillation frequency (1) Oscillation frequency (2) Symbol VIH VIL VOH VOL RON IIL1 IIL2 fopr1 fopr2 fOSC1 fOSC2 Min 0.8 VCC 0 VCC-0.4 -- -- -1.0 -25 10 5 70 21 -- Typ -- -- -- -- -- -- -- -- -- 100 30 -- Max VCC 0.2 VCC -- 0.4 2.0 1.0 25 200 500 130 39 80 Unit V V V V k A A kHz kHz kHz kHz A IOH = -0.4 mA IOL = +0.4 mA VCC-VEE = 28V, load current: 150 A VIN = 0 to VCC VIN = VEE to VCC Measurement Condition Notes 1 1 2 2 13, 14 1 3
Master mode 4 (external clock operation) Slave mode Cf = 100 pF 5%, Rf = 51 k 2% Cf = 100 pF 5%, Rf = 180 k 2% Master mode 1/240 duty cycle, Cf = 100 pF, Rf = 180 k VCC-GND = 3V, VCC-VEE = 28V 5 6, 12 6, 12 7, 8
Power IGND1 consumption (1)
Power IGND2 consumption (2)
--
--
20
A
Master mode 7, 9 1/240 duty cycle external clock fopr1 = 30 kHz VCC-GND = 3V, VCC-VEE = 28V Slave mode 1/240 duty cycle during operation fCL = 15 kHz VCC-GND = 3V, VCC-VEE = 28V 7, 10
Power IGND3 consumption (3)
--
--
10
A
948
HD66503
Item Power consumption Symbol IEE Min -- Typ -- Max 20 Unit A Measurement Condition Master mode 1/240 duty cycle, Cf = 100 pF, Rf = 180 k VCC-GND = 3V VCC-VEE = 28V, Notes 7, 11
Notes: 1. Applies to input pins MEOR, MWS0 to MWS5, DUTY, SHL, ',632)), M/6, and when inputting to input/output pins CL1, FLM, '2&, and M. 2. Applies when outputting from input/output pins CL1, FLM, '2&, and M. 3. Applies to V1L/R, V2L/R, V5L/R, and V6L/R. X1 to X240 are open. 4. Figure 17 shows the external clock specifications:
Duty = TH 0.8VCC 0.5VCC 0.2VCC trcp tfcp TL External clock OPEN OPEN CR R C Duty trcp tfcp Min 45 -- -- TH x 100% TH + TL Typ 50 -- -- Max 55 50 50
5(6(7, and CR,
Unit % ns ns
Figure 17 External Clock
5. Regulates to operation frequency limits of the bidirectional shift register in the slavemode. 6. Connect resistance Rf and capacitance Cf as follows:
Cf Rf CR R C
Figure 18 Timing Components
7. Input and output currents are excluded. When a CMOS input is floating, excess current flows from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to VCC and GND levels, respectively. 8. This value is specified for the current flowing through GND under the following conditions: Internal oscillation circuit is used. Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL, ',632)), M/6, and 5(6(7 is connected to VCC. Oscillator is set as described in note 6. 9. This value is specified for the current flowing through GND under the following conditions: Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL, ',632)), M/6, and 5(6(7 is connected to VCC. Oscillator is set as described in note 4.
949
HD66503
10. This value is specified for the current flowing through GND under the following conditions: Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL, '2&, ',632)), 5(6(7, and CR is connected to VCC, M/6 to GND, and frequency of CL1, FLM, M is respectively established as follows. fCL1 = 15 kHz, fFLM = 62.5 Hz, fM = 120 Hz 11. This value is specified for the current flowing through V EE under the following condition described in note 8. Do not connect any lines to pin X. 12. Figure 19 shows a typical relation among ocsillation frequency R f and Cf. Oscillation frequency may vary with mounting conditions.
300
fOSC = (kHz)
200 Cf = 100 (pF) 100
0
0
100 Rf (k)
200
Figure 19 Ocsillation Frequency Characteristics
13. Indicates the resistance between one pin from X1 to X240 and another pin from the V pins V1L/R, V2L/R, V5L/R, and V6L/R, when a load current is applied to the X pin; defined under the following conditions: VCC-VEE = 28 (V) V1L/R, V6L/R = VCC-1/10 (VCC-VEE) V5L/R, V2L/R = VEE + 1/10 (VCC-VEE)
RON V1L, V1R
V6L, V6R Pin X (X1 to X240) V5L, V5R
V2L, V2R Connect any of these MOS switch
Figure 20 On Resistance Conditions
950
HD66503
14. V1L/R and V6L/R should be near the VCC level, and V5L/R and V2L/R should be near the VEE level. All these voltage pairs should be separated by less than V, which is the range within which RON, the LCD drive circuits' output impedance is stable. Note that V depend on power supply voltages VCC-VEE. See Figure 21.
VCC V1L/R V V6L/R V (V) 2.5 V5L/R V V2L/R VEE 8 28 VCC-VEE (V) 6.4
Figure 21 Relationship between Driver Output Waveform
951
HD66503
AC Characteristics (VCC = 2.7 to 5.5V, VCC-VEE = 8 to 28V, GND = 0V, Ta = -20 to +75C) Slave Mode (M/$ = GND) $
Item CL1 high-level width CL1 low-level width FLM setup time FLM hold time CL1 rise time CL1 fall time Note: Symbol tCWH tCWL tFS tFH tr tf Min 500 500 100 100 -- -- Typ -- -- -- -- -- -- Max -- -- -- -- 50 50 Unit ns ns ns ns ns ns Notes 1 1 1 1 1 1
1. Based on the load circuit shown in Figure 22.
Test point
30 pF (including jig capacitance)
Figure 22 Load Circuit
tr 0.8 VCC 0.2 VCC tf tCWH tCWL
CL1
tFS FLM 0.8 VCC 0.2 VCC
tFH
Figure 23 Slave Mode Timing
952
HD66503
Master Mode (M/$ = VCC) $
Item CL1 delay time FLM delay time M delay time FLM setup time Symbol tDCL1 tDFLM tDM tFS Min -- -- -- tosc/2 - 500 Typ -- -- -- -- Max 1 1 500 -- Unit s s ns ns Notes
tOSC CR 0.8 VCC 0.2 VCC tDCL1 CL1 0.8 VCC 0.2 VCC tFS tDFLM FLM 0.8 VCC 0.2 VCC tDM M 0.8 VCC 0.2 VCC tDFLM tDCL1
Figure 24 Master Mode Timing
953

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