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STV7697B
Scan Driver for Plasma Display Panels
Main Features
s 64-output PDP Scan Driver s 170V Absolute Maximum Rating s 5V Supply for Logic s -200/750 mA Peak Output Current s 1 A Source / Sink Output Diode s 64-bit Shift Register (8 MHz) s Blank Control s Complementary Output Control s BCD Technology s 100 Pin-TQFP Package
TQFP100 (14 x 14 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7697B
Description
The STV7697B is a scan driver for plasma display panels (PDP) implemented in ST's proprietary BCD (Bi-polar CMOS DMOS) technology. Using a 64-bit cascadable 8-MHz shift register, it drives 64 highcurrent and high-voltage outputs. By connecting several STV7697B devices in series, any vertical pixel definition can be performed. The STV7697B is supplied with separate 160V power output and 5 V logic supplies. All command inputs are CMOS compatible. The STV7697B package is a 100-pin TQFP.
October 2003
1/18
STV7697B
Table of Contents
Chapter 1
1.1
Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pinout Diagrams ............................................................................................................... 3
Chapter 2 Chapter 3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Absolute Maximum Ratings ................................................................................................ 9 Thermal Data ...................................................................................................................... 9 Supply Characteristics ....................................................................................................... 10 Power Output Characteristics ........................................................................................... 10 SIN and SOUT Characteristics ......................................................................................... 11 Input (CLR, CLK, STB, BLK, POL, SIN/SOUT, and F/R) Characteristics ......................... 11 AC Timing Requirements ................................................................................................... 11 AC Timing Characteristics .................................................................................................. 12
Chapter 4 Chapter 5 Chapter 6
Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
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STV7697B
Pin Allocation and Descriptions
1
1.1
Pin Allocation and Descriptions
Pinout Diagram
Figure 1: STV7697B (TQFP100)
VSSLOG
VSSLOG
NC* VSSP1
VSSP1
VPP1
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VPP2
VCC
SIN
F/R
78
77
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
76 75 74 73 72 71 70 69 68 67 66 65 64
OUT64
VSSP2
VSSP2 NC*
OUT1
VPP1
SOUT
OUT2
VPP2 NC*
POL
CLR
STB
CLK
BLK
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
TQFP100 (Top View)
63 62 61 60 59 58 57 56 55 54 53 52 51
VSSSUB
VSSP2
NC
NC*
OUT28
OUT29
OUT30
NC*
OUT31
OUT32 OUT33
OUT34
OUT35
NC*
OUT36
OUT37
VSSP1
VSSP1
*NC: Not Connected
VSSP1
OUT38
VPP2
VSSP2
VPP1
VPP1
VPP2
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Pin Allocation and Descriptions
Table 1: Supply Pins Pin No.
88 34 35 41 42 78 79 97 98 83 93 30 31 32 45 46 81 82 94 95 44
STV7697B
Pin Name
VCC VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP1 VPP1 VSSLOG VSSLOG VSSP1 VSSP1 VSSP1 VSSP2 VSSP2 VSSP2 VSSP2 VSSP1 VSSP1 VSSSUB 5V Logic Supply
Pin Description
High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs High Voltage Supply for Power Outputs Logic Ground Logic Ground Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Ground for Power Outputs Substrate Ground
Table 2: Shift Register and Input Pins Pin No.
85 86 87 89 90 91 92 84
Pin Name
SOUT CLK STB BLK POL SIN CLR F/R Shift Register Data Output Clock for Shift Register Data
Pin Description
Latch for Shift Register Data (Strobe Input) Blanking Control for Power Outputs Polarity Selection Shift Register Data Input Clear for Shift Register Data Forward/Reserve modes for selecting Shift Register
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STV7697B
Table 3: Power Output Pins Pin No.
99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 36 37
Pin Allocation and Descriptions
Pin Name
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 OUT32
Pin Description
Power Output 1 Power Output 2 Power Output 3 Power Output 4 Power Output 5 Power Output 6 Power Output 7 Power Output 8 Power Output 9 Power Output 10 Power Output 11 Power Output 12 Power Output 13 Power Output 14 Power Output 15 Power Output 16 Power Output 17 Power Output 18 Power Output 19 Power Output 20 Power Output 21 Power Output 22 Power Output 23 Power Output 24 Power Output 25 Power Output 26 Power Output 27 Power Output 28 Power Output 29 Power Output 30 Power Output 31 Power Output 32
Pin No.
38 39 40 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
Pin Name
OUT33 OUT34 OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64
Pin Description
Power Output 33 Power Output 34 Power Output 35 Power Output 36 Power Output 37 Power Output 38 Power Output 39 Power Output 40 Power Output 41 Power Output 42 Power Output 43 Power Output 44 Power Output 45 Power Output 46 Power Output 47 Power Output 48 Power Output 49 Power Output 50 Power Output 51 Power Output 52 Power Output 53 Power Output 54 Power Output 55 Power Output 56 Power Output 57 Power Output 58 Power Output 59 Power Output 60 Power Output 61 Power Output 62 Power Output 63 Power Output 64
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Pin Allocation and Descriptions
Table 4: Miscellaneous Pins Pin No.
29 33 43 47 77 80 96
STV7697B
Pin Name
NC NC NC NC NC NC NC Not connected Not connected Not connected Not connected Not connected Not connected Not connected
Pin Description
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STV7697B
Circuit Description
2
Circuit Description
Figure 2: STV7697B Block Diagram
CLR CLK SIN (SOUT) STB
Q1 Q2 P1
64-bit Shift Register
P64
F/R SOUT VSSSUB VSSLOG
S1
S64
Latch
Q63 Q64
BLK VCC POL VSSP1 VSSP2
---
---
VPP1 VPP2 VPP2
STV7697B
VSSP1 OUT1
VPP1
VSSP2 OUT64
The STV7697B includes all the necessary logic and power circuits to drive the rows of electrodes of a plasma display panel (PDP). The state of the displayed line is loaded into the shift register. Data is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade several drivers to perform any vertical resolution (Table 5). Inputs CLK, STB, SIN and SOUT are Schmitt trigger inputs.
Table 5: Shift Register Truth Table F/R
H H L L
CLK
Rise L or H Rise L or H
SIN
In In Out Out
SOUT
Out Out In In Forward Shift Steady Reverse Shift Steady
Comments
The forward / reverse (F/R) input is used to select the direction of the shift register where data input/ output status is set according to the selected direction. In Reverse mode (F/R = low), data is input on the SOUT pin and output on the SIN pin. The maximum frequency of the shift clock is 8 MHz. The clear signal (CLR) resets the shift register data to 0 when it is pulled to a high level. Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the latch input (STB) is at low level.
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Circuit Description
STV7697B
All the data are kept memorized in the latch stage when the strobe input (STB) is pulled high. The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the POL input signal (Table 6). Sustain current must not be sunk in the power output to VPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application.
Table 6: Power Output Truth Table Pn*
X X H L H L X X X X
CLR
X X L L L L X X H H
STB
X X L L L L H H L L
BLK
H H L L L L L L L L
POL
H L L L H H L H L H
Driver Output
All H All L H L L H Qn Qn L H
Comments
Forced to High Forced to Low Copy Data Copy Data Copy Inverted Data Copy Inverted Data Data Latched Inverted Data Latched All Low All High
*Pn is the parallel output of the shift register (n = 1 to 64). Pn takes the value of serial input (SIN) after "n" shift clock periods.
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STV7697B
Electrical Characteristics
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Logic Supply Driver Supply Logic Input Voltage Logic Output Voltage Driver Output Voltage (Scanning mode) Driver Output Current (See Note 1 and Note 3) Diode Output Current (See Note 2 and Note 3) Latch-up Susceptibility Junction Temperature Operating Temperature Storage Temperature
Symbol
VCC VPP VIN VOUT VPOUT IPOUT IDOUT IL TJMAX TOPER TSTG
Value
-0.3, +7 -0.3, +170 -0.3, VCC +0.3 -0.3, VCC + 0.3 -0.3, VPP -250, +800 1.2 200 +125 -20, +85 -50, +150
Units
V V V V V mA A mA C C C
Note:1. Through one power output. 2. Through one power output with VPP = VSSP (See Figure 4.) 3. These parameters are measured during ST's internal qualification which includes temperature characterization on standard batches and on corners batches of the process. These parameters are not tested on the parts.
3.2
Thermal Data
Parameter
Maximum Operating Junction Junction-ambient Thermal Resistance (See Note 1) Operating Power Dissipation (TOPER = 25 C)
Symbol
TJOPER RthJA POPER
Value
125 40 2
Units
C C/W W
Note:1. TQFP soldered on 4-layer printed circuit board.
9/18
Electrical Characteristics
STV7697B
3.3
Supply Characteristics
(VCC = 5 V, VPP = 160 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, TAMB = 25C and fCLK = 8 MHz, unless otherwise specified)
Symbol
VCC ICCH ICCL VPP IPPH
Parameter
Logic Supply Voltage Logic Supply Current (all inputs high) Logic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs)
Test Conditions
Min.
4.5
Typ.
5
Max.
5.5 100
Units
V A mA
fCLK = 8 MHz, SIN =1010 15
5.8 160 100
V A
3.4
Power Output Characteristics
Parameter
Power Output High Level (voltage drop versus VPP, VPP=90V) Power Output Peak Current (See Note 1) Power Output Low Level Power Output Peak Current (See Note 2)
Symbol
VPOUTH IPOUTH-peak VPOUTL IPOUTL-peak VDOUTH1 VDOUTL1 VDOUTH2 VDOUTL2
Test Conditions
IPOUTH = - 10 mA IPOUTH = - 40 mA VPP =130V IPOUTL = 200 mA VPOUTL = 30V VCC = 5V
Min.
5 10
Typ.
3 5 -200 2.6 650 2
Max.
Units
V mA
5
V mA
Output Diode High Level (See Note 3 and Note 4) IDOUTH = +400 mA Output Diode Low Level (See Note 3 and Note 4) Output Diode High Level (See Note 3) Output Diode Low Level (See Note 3) IDOUTL = - 400 mA IDOUTH = +1000 mA IDOUTL = - 1000 mA -3.5 -2.5
3
V V
-1.3 3.5 -2 5
V V
Note:1. These parameters are measured during ST's internal qualification which includes temperature characterization on standard batches and on corners batches of the process. These parameters are not tested on the parts. 2. Peak current: pulse mode 720 Hz, 200ns pulse width, VCC=5 V. 3. Compatible with power dissipation (see Figure 4: Test Configuration). 4. The typical value increases when more than one output is activated.
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STV7697B
Electrical Characteristics
3.5
SIN and SOUT Characteristics
Parameter
Logic Output High Level Logic Output Low Level
Symbol
VOH VOL
Test Conditions
IOH = -1 mA IOL = 1 mA
Min.
4.4 0.05
Typ.
4.7 0.1
Max.
4.8 0.25
Units
V V
3.6
Input (CLR, CLK, STB, BLK, POL, SIN/SOUT, and F/R) Characteristics
Parameter
Input High Level Input Low Level High Level Input Current Low Level Input Current Pins CLR, CLK, SIN/SOUT, STB, F/R, BLK and POL VIH = VCC VIL = 0 V -10
Symbol
VIH VIL IIH IIL
Test Conditions
Min.
0.8 VCC
Typ.
Max.
Units
V
0.2VCC 10
V A
-10
10
A
3.7
AC Timing Requirements
VCC = 4.5 V to 5.5 V, TAMB = -20 to +85C, max. leading/trailing edge for input signals (tr, tf) = 10 ns
Symbol
tCLK tWHCLK tWLCLK tSDAT tHDAT tSFR tDSTB tSSTB tSTB tBLK tPOL Data Clock Period
Parameter
Min.
125 30 30 10 10 100 10 10 30 100 100
Typ.
Max.
Units
ns ns ns ns ns ns ns ns ns ns ns
Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock (low to high) transition Hold Time of data input after clock (low to high) transition F/R Set-up time before low to high transition Minimum Delay to latch STB after clock (low to high) transition Set-up Time STB before clock (low to high) transition Strobe STB Pulse Duration Blanking (BLK) Pulse Duration Polarity (POL) Pulse Duration
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Electrical Characteristics
STV7697B
3.8
AC Timing Characteristics
(VCC = 5V, VPP = 90V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25oC, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V and CL = 10pF, unless otherwise specified)
Symbol
tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time
Parameter
Min.
125
Typ.
Max.
Units
ns
20 15 45 50 135 100 120 90 110 80 40 130
40 30 70 75 200 170 190 160 180 150 80 200
ns ns ns ns ns ns ns ns ns ns ns ns
Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition Delay of power output change (high to low transition) to Blank (BLK) or Polarity (POL) transition Delay of power output change (low to high transition) to Blank (BLK) or Polarity (POL) transition Power Output Rise Time (See Note 2) Power Output Fall Time (See Note 2)
Note:1. See Figure 4: Test Configuration. 2. One output among 64, loading capacitor COUT = 200 pF, other outputs at low level.
12/18
STV7697B
Electrical Characteristics
Figure 3: AC Characteristics Waveform
13/18
Electrical Characteristics
Figure 4: Test Configuration
STV7697B
VPP=VSSP
VPP=VSSP
VDOUTH
IDOUTH
VDOUTL VSSP
IDOUTL
VSSP
Output sinking current as positive value, sourcing current as negative value.
14/18
STV7697B
Input/Output Schematic Diagrams
4
Input/Output Schematic Diagrams
Figure 5: F/R, BLK, CLR and POL Inputs
Figure 7: SIN and SOUT Inputs
VCC SIN, SOUT
VCC
F/R, BLK, CLR, POL
VSSLOG VSSLOG VSSLOG VSSLOG
VSSLOG
Figure 6: CLK and STB Inputs Figure 8: Power Outputs
VCC
VPP
CLK, STB
OUTi
VV SSLOG
SSSUB
VV SSLOG
SSLOG
VSSP
15/18
Package Mechanical Data
STV7697B
5
Package Mechanical Data
Dimensions
A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Millimeters Min.
0.05 1.35 0.17 0.09
Inches Max.
1.60 0.15 1.45 0.27 0.20
Typ.
Min.
0.002 0.053 0.007 0.004
Typ.
Max.
0.063 0.006 0.057 0.011 0.008
1.40 0.22 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00
0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039
0.45
0.75
0.018
0.030
0 (Min.), 7 (Max.)
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STV7697B
Revision History
6
Revision History
Table 7: Summary of Modifications
Version
0.1 0.2 0.3
Date
2 August 2002 23 Sept. 2002 20 March 2003 First issue. Modification of Pinout description.
Description
Modification of Pinouts. Update of Figure 2: STV7697B Block Diagram, Figure 3: AC Characteristics Waveform, Figure 5: F/R, BLK, CLR and POL Inputs, Figure 7: SIN and SOUT Inputs and Figure 8: Power Outputs. Update of Electrical Characteristic values. Datasheet status changed to "Preliminary Data". Removed all references to STV7697BD package. Changed value of IDOUT to 1.2 A. Included values for tPHL3, tPLH3, tPHL4 and tPLH4. Updated Figure 7 and Figure 8. Updated parameter values in Power Output Characteristics on page 10 and AC Timing Characteristics on page 12. Updated and corrected data in Section 3.5, Section 3.6, Section 3.7 and Section 3.8.
0.4
18 June 2003
0.5
05 August 2003
0.6 0.7
10 September 2003 23 September 2003
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Revision History
Notes:
STV7697B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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