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IS62WV5128CLL
512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
* High-speed access time: 55ns, 70ns * CMOS low power operation - 1.5 W (typical) CMOS standby * TTL compatible interface levels * Single power supply - 2.5V--3.6V VDD (62WV5128CLL) * Fully static operation: no clock or refresh required * Three state outputs * Industrial temperature available * 2 CS Options Available
ISSI
MARCH 2003
(R)
DESCRIPTION
The ISSI IS62WV5128CLL are high-speed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV5128CLL is packaged in the JEDEC standard 36-pin mini BGA (6mm x 8mm). 36-pin mini BGA is available in both 1CS and 2CS options.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 8 MEMORY ARRAY
VDD GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CS2 CS1 OE WE CONTROL CIRCUIT
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Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
1
www..com
Rev. 00B 03/13/03
IS62WV5128CLL
PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 2 CS Option (Package Code B2)
ISSI
36-pin mini BGA (B) (6mm x 8mm) (Package Code B)
(R)
1
2
3
4
5
6
1
2
3
4
5
6
A B C D E F G H
A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9
A1 A2
CS2 WE NC
A3 A4 A5
A6 A7
A8 I/O0 I/O1 VDD GND
A B C D E F G H
A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9
A1 A2
NC WE NC
A3 A4 A5
A6 A7
A8 I/O0 I/O1 VDD GND
A18 OE A10 CS1 A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
A18 OE A10 CS1 A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
PIN DESCRIPTIONS
A0-A18 CS1 CS2 OE WE I/O0-I/O7 NC VDD GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
IS62WV5128CLL
OPERATING RANGE (VDD)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V - 3.6V 2.5V - 3.6V
ISSI
(R)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value -0.3 to VDD+0.5 -0.2 to +4.2 -55 to +125 0.6 Unit V V C W
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions IOH = -1 mA IOL = 2.1 mA VDD 2.5-3.6V 2.5-3.6V 2.5-3.6V 2.5-3.6V Min. 2.2 -- 2.2 -0.2 -1 -1 Max. -- 0.4 VDD + 0.3 0.6 1 1 Unit V V V V A A
Notes: 1. VIL (min.) = -1.0V for pulse width less than 10 ns.
TRUTH TABLE
Mode Not Selected (Power-down) Output Disable Read Write WE X X H H L CS1 H X L L L CS2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ISB1, ISB2 Icc Icc Icc
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
3
IS62WV5128CLL
ISSI
Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF
(R)
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 62WV5128CLL (Unit) 0.4 to VDD-0.3V 5ns VREF See Figures 1 and 2
2.5V - 3.6V R1() R2() VREF VTM 3070 3150 1.5V 2.8V
AC TEST LOADS
R1 VTM
R1 VTM
OUTPUT 30 pF Including jig and scope R2
OUTPUT 5 pF Including jig and scope R2
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
IS62WV5128CLL
ISSI
Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. VDD = Max., Com. IOUT = 0 mA, f = 0 Ind. VDD = Max., Com. VIN = VIH or VIL Ind. CS1 = VIH , CS2 = VIL, f = 1 MHZ VDD = Max., CS1 VDD - 0.2V, CS2 0.2V, VIN VDD - 0.2V, or Vin 0.2V, f = 0 Com. Ind. typ(2) Max. 55 ns 50 55 2 3 0.6 0.8 Max. 70 ns 45 50 2 3 0.6 0.8 Unit mA mA mA
(R)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV5128CLL (2.5V - 3.6V)
Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs)
ISB2
CMOS Standby Current (CMOS Inputs)
10 10 0.5
10 10 0.5
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time
(2)
55 ns Min. Max. 55 -- 10 -- -- -- 5 0 10 -- 55 -- 55 35 20 -- 20 --
70 ns Min. Max. 70 -- 10 -- -- -- 5 0 10 -- 70 -- 70 40 25 -- 25 --
Unit ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACS1/tACS2 tDOE tHZOE tLZOE(2) tHZCS1/tHZCS2(2) tLZCS1/tLZCS2
(2)
OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to VDD0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
5
IS62WV5128CLL
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
tRC
ISSI
(R)
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CS1
tACS1/tACS2
tLZOE
CS2
tLZCS1/ tLZCS2
HIGH-Z
tHZCS
DATA VALID
DOUT
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
IS62WV5128CLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time 55 ns Min. Max. 55 45 45 0 0 40 25 0 -- 5 -- -- -- -- -- -- -- -- 20 --
ISSI
70 ns Min. Max. 70 60 60 0 0 50 30 0 -- 5 -- -- -- -- -- -- -- -- 20 -- Unit ns ns ns ns ns ns ns ns ns ns
(R)
tWC
tSCS1/tSCS2 CS1/CS2 to Write End tAW Address Setup Time to Write End tHA tSA tPWE tSD tHD tHZWE(3) tLZWE(3)
Notes:
Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to VDD0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tSCS1 tHA
CS1
tSCS2
CS2
tAW tPWE tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
7
IS62WV5128CLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
ISSI
tWC
(R)
ADDRESS
OE
tSCS1 tHA
CS1
tSCS2
CS2
tAW tPWE tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tSCS1 tHA
CS1
tSCS2
CS2
tAW tPWE tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
IS62WV5128CLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol VDR IDR tSDR tRDR Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.5V, CS1/CS2 VDD - 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.5 -- 0 tRC
ISSI
Max. 3.6 10 -- -- Unit V A ns ns
(R)
DATA RETENTION WAVEFORM (CS1 Controlled) CS1
tSDR VDD 3.0V Data Retention Mode tRDR
2.2V
VDR CS1 VDD- 0.2V
CS1 GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode VDD tSDR tRDR
3.0
CS2 2.2V VDR 0.4V GND
CS2 0.2V
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
9
IS62WV5128CLL
ORDERING INFORMATION IS62WV5128CLL (2.5V - 3.6V) Commercial Range: 0C to +70C
Speed (ns) 55 55 Order Part No. IS62WV5128CLL-55B IS62WV5128CLL-55B2 Package mini BGA (6mm x 8mm) mini BGA (6mm x 8mm) 2CS
ISSI
(R)
Industrial Range: -40C to +85C
Speed (ns) 55 55 70 70 Order Part No. IS62WV5128CLL-55BI IS62WV5128CLL-55B2I IS62WV5128CLL-70BI IS62WV5128CLL-70B2I Package mini BGA (6mm x 8mm) mini BGA (6mm x 8mm) 2CS mini BGA (6mm x 8mm) mini BGA (6mm x 8mm) 2CS
10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 03/13/03
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (36-pin)
Top View 1 2 3 4 56 6
ISSI
Bottom View
b (36x)
(R)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
Notes: 1. Controlling dimensions are in millimeters.
A2 SEATING PLANE A1 A
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.24 0.60
mBGA - 8mm x 10mm
INCHES Min. Typ. Max.
36
MILLIMETER Sym.
N0. Leads
INCHES Min. Typ. Max.
36
Min. Typ. Max.
36 -- -- -- 5.25BSC 5.90 6.00 3.75BSC 0.75BSC 0.30 0.35 0.40 6.10 1.20 0.30 -- 8.10
Min. Typ. Max.
36 -- 0.24 0.60 -- -- -- 5.25BSC 7.90 8.00 8.10 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 --
-- 0.009 0.024
-- -- --
0.047 0.012 --
A A1 A2 D D1 E E1 e b
-- 0.009 0.024
-- -- --
0.047 0.012 --
7.90 8.00
0.311 0.315 0.319 0.207BSC 0.232 0.236 0.240 0.148BSC 0.030BSC 0.012 0.014 0.016
9.90 10.00 10.10
0.390 0.394 0.398 .207BSC 0.311 0.315 0.319 0.148BSC 0.030BSC 0.012 0.014 0.016
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 01/15/03

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