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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949-01 is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87949-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
FEATURES
* 15 single ended LVCMOS outputs, 7 typical output impedance * Selectable LVCMOS or LVPECL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum input frequency: 250MHz * Output skew: 200ps (maximum) * Part-to-part skew: 500ps (typical) * Multiple frequency skew: 350ps (maximum) * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Functionally compatible to the MPC949 in a smaller footprint requiring less board space
,&6
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/ nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949-01 is characterized at 3.3V core/3.3V output and 3.3V core/ 2.5V output. Guaranteed bank, output and part-topart skew characteristics make the ICS87949-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 QB0 - QB2 1 DIV_SELB 0 QC0 - QC3 1 DIV_SELC 0 QD0 - QD5 1 DIV_SELD MR/nOE 0 0 1 1 /1 /2 R 0 QA0 - QA1
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2
48 47 46 45 44 43 42 41 40 39 38 37 MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GND GND QD0 VDDD QD1 GND QD2 VDDD QD3 GND QD4 VDDD
36 35 34 33 32 31 30 29 28 27 26 25
nc GND QC0 VDDC QC1 GND QC2 VDDC QC3 GND GND QD5
ICS87949-01
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87949AY-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 2, 2002
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 5 6 7 8 9 10 11 12 13, 14, 18, 22, 26, 27, 31, 35, 39, 43, 44, 48 15, 17, 19, 21, 23, 25 16, 20, 24, 28, 30, 32, 34 29, 33 36 37, 41 38, 40, 42 45, 47 46 Name MR/nOE CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD Input Input Power Input Input Input Input Input Input Input Input Type Description Master reset and output enable. Resets outputs to tristate. Pulldown Enables and disables all outputs. LVCMOS interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. Connect to 3.3V. Pullup Pullup LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input. for Bank A outputs. for Bank B outputs. for Bank C outputs. for Bank D outputs. Pulldown Non-inver ting differential LVPECL clock input. Pulldown PCLK select input. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels.
GND QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC nc VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Power
Power supply ground. Connect to ground.
Output Power Output Power Unused Power Output Output Power
Bank D outputs. LVCMOS interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Connect to 3.3V or 2.5V. Bank C outputs. LVCMOS interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V. No connect. Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V. Bank B outputs. LVCMOS interface levels. 7 typical output impedance. Bank A outputs. LVCMOS interface levels. 7 typical output impedance. Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AY-01
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2
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
Maximum 4 Units pF K K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, *VDDx = 3.465V 51 51 TBD 7 Test Conditions Minimum Typical
*NOTE: VDDx denotes VDDA, VDDB, VDDC, VDDD.
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0 - QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0 - QB2 QC0 - QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0 - QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AY-01
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3
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 47.9C/W (0 lfpm) -65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC, VDDD. **IDDx denotes IDDA, IDDB, IDDC, IDDD. Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 50 14 Maximum 3.465 3.465 Units V V mA mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol Parameter DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 *VDDx = VIN = 3.465V *VDDx = VIN = 3.465V *VDDx = 3.465V, VIN = 0V *VDDx = 3.465V, VIN = 0V -5 -150 2.6 0.5 TBD TBD Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V V V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL IOZL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low
Output Tristate Current High IOZH NOTE 1: Outputs terminated with 50 to VDDx/2. See page 8, Figure 1A, 3.3V Output Load Test Circuit. *NOTE: VDDx denotes VDD, VDDA, VDDB, VDDC, VDDD.
87949AY-01
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4
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
Maximum 150 5 Units A A A A 1 VDD V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions *VDDx = VIN = 3.465V *VDDx = VIN = 3.465V *VDDx = 3.465V, VIN = 0V *VDDx = 3.465V, VIN = 0V -5 -150 0.3 Minimum Typical
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. NOTE: *VDDx denotes VDD, VDDA, VDDB, VDDC, VDDD.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle Output Enable Time;NOTE 6 f = 10MHz Test Conditions f 250MHz f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% 20% to 80% 500 700 700 50 Minimum Typical Maximum 250 3.5 3.5 100 200 350 Units MHz ns ns ps ps ps ps ps ps % ns ns
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc tEN
Output Disable Time;NOTE 6 f = 10MHz tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87949AY-01
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5
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
Maximum 3.465 2.625 Units V V mA mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C
Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC, VDDD. **IDDx denotes IDDA, IDDB, IDDC, IDDD. Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 50 13
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C
Symbol Parameter DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.8 0.5 TBD TBD Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V V V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL IOZL IOZH
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High
NOTE 1: Outputs terminated with 50 to VDDx/2. See page 8, Figure 1B, 3.3V/2.5V Output Load Test Circuit.
87949AY-01
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6
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
Maximum 150 5 Units A A A A 1 VDD V V
TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 Minimum Typical
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle Output Enable Time;NOTE 6 f = 10MHz Test Conditions f 250MHz f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% 20% to 80% 500 700 700 50 Minimum Typical Maximum 250 3.5 3.5 100 200 350 Units MHz ns ns ps ps ps ps ps ps % ns ns
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc tEN
Output Disable Time;NOTE 6 f = 10MHz tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87949AY-01
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7
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V5%
VDD VDDx
SCOPE
LVCMOS
GND
Qx
-1.65V5%
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
2.05V5%
1.25V5%
V DD VDDx
SCOPE
LVCMOS
GND
Qx
-1.25V5%
FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
87949AY-01
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8
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
VDD
nPCLK V PCLK
PP
Cross Points
V
CMR
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
Vx DD 2
V
Qy
DD x
2 tsk(o)
FIGURE 3 - OUTPUT SKEW
PART 1 Qx
V
DD x
2
PART 2 Qy
V
DD x
2 tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
87949AY-01
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9
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
80%
80% V
SWING
20% Clock Inputs and Outputs t t
20%
R
F
FIGURE 5 - INPUT
AND
OUTPUT RISE
AND
FALL TIME
V
DD
CLK0, CLK1
2
nPCLK PCLK
V
DD x
QAx, QBx, QCx, QDx
2
QAx, QBx, QCx, QDx
87949AY-01
t
PD
FIGURE 6 - PROPAGATION DELAY
V
DD x
2 Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 7 - odc & tPERIOD
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10
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949-01 is: 1545
87949AY-01
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11
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87949AY-01
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12
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949-01
LOW SKEW /1, /2 CLOCK GENERATOR
Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87949AY-01 ICS87949AY-01T Marking ICS87949AY-01 ICS87949AY-01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87949AY-01
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REV. A JANUARY 2, 2002

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