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| Low Capacitance, 4-/8-Channel 15 V/+12 V iCMOSTM Multiplexers ADG1208/ADG1209 FEATURES <1 pC charge injection over full signal range 1 pF off capacitance 33 V supply range 120 on resistance Fully specified at 15 V/+12 V 3 V logic compatible inputs Rail-to-rail operation Break-before-make switching action Available in 16-lead TSSOP and 4 mm x 4 mm LFCSP_VQ Typical power consumption < 0.03 W FUNCTIONAL BLOCK DIAGRAMS ADG1208 S1 S1A DA S4A D S1B DB S8 1-OF-8 DECODER S4B 1-OF-4 DECODER 05713-001 ADG1209 APPLICATIONS Audio and video routing Automatic test equipment Data-acquisition systems Battery-powered systems Sample-and-hold systems Communication systems A0 A1 A2 EN A0 A1 EN Figure 1. GENERAL DESCRIPTION The ADG1208 and ADG1209 are monolithic, iCMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1208 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG1209 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery powered instruments. 1.0 MUX (SOURCE TO DRAIN) 0.9 TA = 25C 0.8 CHARGE INJECTION (pC) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -15 -10 VDD = +5V VSS = -5V -5 0 VS (V) 5 10 15 05713-051 VDD = +15V VSS = -15V VDD = +12V VSS = 0V Figure 2. Source to Drain Charge Injection vs. Source Voltage Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved. ADG1208/ADG1209 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings ............................................................7 ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 14 Test Circuits..................................................................................... 15 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 4/06--Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG1208/ADG1209 SPECIFICATIONS DUAL SUPPLY VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. 1 Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG1208 ADG1209 Channel On Leakage, ID, IS (On) ADG1208 ADG1209 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off ) CD (Off ) ADG1208 CD (Off ) ADG1209 +25C -40C to +85C -40C to +125C VSS to VDD 120 200 3.5 6 20 64 0.02 0.1 0.02 0.1 0.1 0.02 0.2 0.2 240 270 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA max nA typ nA max nA max V min V max A max A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF max pF typ pF max pF typ pF max Test Conditions/Comments VS = 10 V, IS = -1 mA, see Figure 29 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA 10 76 12 83 VS = -5 V, 0 V, +5 V, IS = -1 mA VD = 10 V, VS = -10 V, see Figure 30 VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 30 0.6 0.6 0.6 0.6 0.6 1 1 1 1 1 2.0 0.8 VS = VD = 10 V, see Figure 31 0.005 0.1 2 80 130 75 95 83 100 25 0.4 -85 -85 0.15 550 1 1.5 6 7 3.5 4.5 VIN = VINL or VINH 165 105 125 185 115 140 10 RL = 300 , CL = 35 pF VS = 10 V, see Figure 32 RL = 300 , CL = 35 pF VS = 10 V, see Figure 34 RL = 300 , CL = 35 pF VS = 10 V, see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V, see Figure 33 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 36 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 38 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz, see Figure 39 RL = 50 , CL = 5 pF, see Figure 37 f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V Rev. 0 | Page 3 of 20 ADG1208/ADG1209 Parameter CD, CS (On) ADG1208 CD, CS (On) ADG1209 POWER REQUIREMENTS IDD IDD ISS ISS VDD/VSS 1 2 +25C 7 8 5 6 0.002 -40C to +85C -40C to +125C Unit pF typ pF max pF typ pF max A typ A max A typ A max A typ A max A typ A max V min/max Test Conditions/Comments f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V or VDD Digital inputs = 5 V |VDD | = |VSS| 1.0 220 320 0.002 1.0 0.002 1.0 5/16.5 Temperature range is as follows: Y version: -40C to +125C. Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 20 ADG1208/ADG1209 SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. 1 Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG1208 ADG1209 Channel On Leakage ID, IS (On) ADG1208 ADG1209 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off ) CD (Off ) ADG1208 CD (Off ) ADG1209 CD, CS (On) ADG1208 CD, CS (On) ADG1209 +25C -40C to +85C -40C to +125C 0 to VDD 300 475 5 16 60 0.02 0.1 0.02 0.1 0.1 0.02 0.2 0.2 567 625 Unit V typ max typ max typ nA typ nA max nA typ nA max nA max nA typ nA max nA max V min V max A max pF typ ns typ 210 140 155 235 ns typ 160 ns typ 175 20 -0.2 -85 -85 450 1.2 1.8 7.5 9 4.5 5.5 9 10.5 6 7.5 ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max pF typ pF max pF typ pF max VIN = VINL or VINH Test Conditions/Comments VS = 0 V to10 V, IS = -1 mA, see Figure 29 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA 26 27 VS = 3 V, 6 V, 9 V; IS = -1 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 0.6 0.6 0.6 0.6 0.6 1 1 1 1 1 2.0 0.8 VS = VD = 1 V or 10 V; see Figure 31 0.001 0.1 3 100 170 90 110 105 130 45 RL = 300 , CL = 35 pF VS = 8 V, see Figure 32 RL = 300 , CL = 35 pF VS = 8 V, see Figure 34 RL = 300 , CL = 35 pF VS = 8 V, see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V, see Figure 33 VS = 6 V, RS = 0 , CL = 1 nF, see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 36 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 38 RL = 50 , CL = 5 pF, see Figure 37 f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V Rev. 0 | Page 5 of 20 ADG1208/ADG1209 Parameter POWER REQUIREMENTS IDD IDD VDD 1 2 +25C 0.002 -40C to +85C -40C to +125C Unit A typ A max A typ A max V min/max Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V 1.0 220 330 5/16.5 Temperature range is as follows: Y version: -40C to +125C. Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 20 ADG1208/ADG1209 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs 1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (Y Version) Storage Temperature Junction Temperature TSSOP, JA, Thermal Impedance LFCSP_VQ, JA, Thermal Impedance Reflow Soldering Peak Temperature (Pb-Free) 1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) 30 mA 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -40C to +125C -65C to +150C 150C 112C/W 30.4C/W 260(+0/-5)C Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 20 ADG1208/ADG1209 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 EN 15 A0 A0 1 EN 2 VSS 3 16 15 A1 A2 GND VDD S5 S6 S7 05713-002 ADG1208 TOP VIEW (Not to Scale) 14 13 12 11 10 9 S1 4 S2 5 S3 6 S4 7 D8 VSS 1 S1 2 S2 3 S3 4 PIN 1 INDICATOR 13 A2 14 A1 12 GND 11 VDD 10 S5 9 S6 05713-004 ADG1208 TOP VIEW (Not to Scale) S8 Figure 3. ADG1208 Pin Configuration (TSSOP) Figure 4. ADG1208 Pin Configuration (LFCSP_VQ), Exposed Pad Tied to Substrate, VSS Table 4. ADG1208 Pin Function Descriptions TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Number LFCSP_VQ 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic A0 EN VSS S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal 8. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 5. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Table 5. ADG1208 Truth Table A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH NONE 1 2 3 4 5 6 7 8 Rev. 0 | Page 8 of 20 S7 8 S8 7 S4 5 D6 ADG1208/ADG1209 16 EN A0 1 EN 2 VSS 3 16 15 A1 GND VDD S1B S2B S3B S4B 05713-003 ADG1209 TOP VIEW (Not to Scale) 14 13 12 11 10 9 S1A 4 S2A 5 S3A 6 S4A 7 DA 8 VSS 1 S1A 2 S2A 3 S3A 4 PIN 1 INDICATOR 15 A0 13 GND 14 A1 12 VDD 11 S1B 10 S2B 9 S3B ADG1209 TOP VIEW (Not to Scale) S4B 8 S4A 5 DB 7 DA 6 DB Figure 5. ADG1209 Pin Configuration (TSSOP) Figure 6. ADG1209 Pin Configurations (LFCSP_VQ), Exposed Pad Tied to Substrate, VSS Table 6. ADG1209 Pin Function Descriptions Pin Number TSSOP LFCSP_VQ 1 15 2 16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic A0 EN VSS S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Drain Terminal A. Can be an input or an output. Drain Terminal B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Table 7. ADG1209 Truth Table A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 ON SWITCH PAIR NONE 1 2 3 4 Rev. 0 | Page 9 of 20 05713-005 ADG1208/ADG1209 TYPICAL PERFORMANCE CHARACTERISTICS 200 180 160 ON RESISTANCE () 250 TA = 25C VDD = +13.5V VSS = -13.5V ON RESISTANCE () VDD = +15V VSS = -15V 200 TA = +125C 150 TA = +85C TA = +25C 100 TA = -40C 50 VDD = +15V VSS = -15V 140 120 100 80 60 40 20 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18 05713-030 VDD = +16.5V VSS = -16.5V -10 -5 0 5 TEMPERATURE (C) 10 15 Figure 7. On Resistance as a Function of VD (VS) for Dual Supply Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply 600 VDD = 12V VSS = 0V 600 TA = 25C 500 VDD = +4.5V VSS = -4.5V VDD = +5V VSS = -5V 400 TA = +125C 500 ON RESISTANCE () ON RESISTANCE () TA = +85C 400 TA = +25C 300 TA = -40C 300 VDD = +5.5V VSS = -5.5V 200 200 100 100 05713-031 -6 -4 -2 0 2 SOURCE OR DRAIN VOLTAGE (V) 4 6 0 2 4 6 8 TEMPERATURE (C) 10 12 Figure 8. On Resistance as a Function of VD (VS) for Dual Supply 450 TA = 25C 400 350 ON RESISTANCE () Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply 400 VDD = +15V VSS = -15V VBIAS = +10V/-10V ID, S (ON) + + ID (OFF) + - IS (OFF) + - 0 -100 -200 -300 05713-057 VDD = 10.8V VSS = 0V 300 300 250 200 150 100 50 05713-032 LEAKAGE CURRENT (pA) VDD = 12V VSS = 0V 200 100 VDD = 13.2V VSS = 0V ID, S (ON) - - ID (OFF) - + IS (OFF) - + 0 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 14 -400 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) 90 100 110 120 Figure 9. On Resistance as a Function of VD (VS) for Single Supply Figure 12. ADG1208 Leakage Currents as a Function of Temperature, Dual Supply Rev. 0 | Page 10 of 20 05713-034 0 0 05713-033 0 -18 -15 -12 0 -15 ADG1208/ADG1209 150 VDD = 12V VSS = 0V VBIAS = 1V/10V IS (OFF) + - 50 ID, S (ON) + + ID (OFF) + - 0 ID, S (ON) - - -50 ID (OFF) - + IS (OFF) - + CHARGE INJECTION (pC) 6 DEMUX (DRAIN TO SOURCE) TA = 25C VDD = +5V VSS = -5V 100 LEAKAGE CURRENT (pA) 4 2 0 VDD = +15V VSS = -15V VDD = +12V VSS = 0V -2 -100 -4 05713-058 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) 90 100 110 120 -10 -5 0 VS (V) 5 10 15 Figure 13. ADG1208 Leakage Currents as a Function of Temperature, Single Supply 200 180 160 140 VDD = +15V VSS = -15V IDD PER CHANNEL TA = 25C Figure 16. Drain-to-Source Charge Injection vs. Source Voltage 350 300 250 TIME (ns) VDD = +5V VSS = -5V VDD = +12V VSS = 0V IDD (A) 120 100 80 60 40 20 0 0 2 4 6 8 10 LOGIC, INX (V) 12 14 16 VDD = +12V VSS = 0V 05713-035 200 150 100 50 0 -40 VDD = +15V VSS = -15V -20 0 20 40 60 TEMPERATURE (C) 80 100 120 Figure 14. IDD vs. Logic Level 1.0 Figure 17. tON/tOFF Times vs. Temperature 0 -10 -20 OFF ISOLATION (dB) MUX (SOURCE TO DRAIN) 0.9 TA = 25C 0.8 VDD = +15V VSS = -15V TA = 25C CHARGE INJECTION (pC) -30 -40 -50 -60 -70 -80 -90 -100 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -15 -10 VDD = +5V VSS = -5V -5 0 VS (V) 5 10 15 05713-040 VDD = +15V VSS = -15V VDD = +12V VSS = 0V 100k 1M 10M FREQUENCY (Hz) 100M 1G Figure 15. Source-to-Drain Charge Injection vs. Source Voltage Figure 18. Off Isolation vs. Frequency Rev. 0 | Page 11 of 20 05713-049 -110 10k 05713-052 05713-041 -150 -6 -15 ADG1208/ADG1209 20 VDD = +15V VSS = -15V TA = 25C 0 10 LOAD = 10k TA = 25C -20 CROSSTALK (dB) 1 THD + N (%) -40 ADJACENT CHANNELS -60 -80 -100 -120 10k NONADJACENT CHANNELS VDD = +5V, VSS = -5V, VS = +3.5Vrms VDD = +15V, VSS = -15V, VS = +5Vrms 0.1 05713-042 100k 1M 10M FREQUENCY (Hz) 100M 1G 100 1k FREQUENCY (Hz) 10k 100k Figure 19. ADG1208 Crosstalk vs. Frequency 0 12 Figure 22. THD + N vs. Frequency -20 10 VDD = +15V VSS = -15V TA = 25C CROSSTALK (dB) -40 CAPACITANCE (pF) 8 SOURCE/DRAIN ON -60 ADJACENT CHANNELS 6 DRAIN OFF -80 4 -100 NONADJACENT CHANNELS 05713-053 2 SOURCE OFF 100k 1M 10M FREQUENCY (Hz) 100M 1G -10 -5 0 VBIAS (V) 5 10 15 Figure 20. ADG1209 Crosstalk vs. Frequency 12 Figure 23. ADG1208 Capacitance vs. Source Voltage, 15 V Dual Supply VDD = 12V VSS = 0V TA = 25C SOURCE/DRAIN ON -6.0 -6.5 -7.0 10 ON RESPONSE (dB) CAPACITANCE (pF) -7.5 -8.0 -8.5 -9.0 -9.5 05713-054 8 DRAIN OFF 6 4 2 SOURCE OFF 100k 1M 10M FREQUENCY (Hz) 100M 1G 0 2 4 6 VBIAS (V) 8 10 12 Figure 21. On Response vs. Frequency Figure 24. ADG1208 Capacitance vs. Source Voltage, 12 V Single Supply Rev. 0 | Page 12 of 20 05713-045 -10.0 10k 0 05713-043 -120 10k 0 -15 05713-036 0.01 10 ADG1208/ADG1209 12 8 7 SOURCE/DRAIN ON 6 VDD = 12V VSS = 0V TA = 25C SOURCE/DRAIN ON 10 CAPACITANCE (pF) 8 VDD = +5V VSS = -5V TA = 25C DRAIN OFF CAPACITANCE (pF) 5 DRAIN OFF 4 3 2 SOURCE OFF 6 4 2 SOURCE OFF -4 -3 -2 -1 0 VBIAS (V) 1 2 3 4 5 05713-055 1 05713-047 05713-056 0 -5 0 0 2 4 6 VBIAS (V) 8 10 12 Figure 25. ADG1208 Capacitance vs. Source Voltage, 5 V Dual Supply 8 7 6 Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply 8 VDD = +15V VSS = -15V TA = 25C SOURCE/DRAIN ON 7 6 SOURCE/DRAIN ON CAPACITANCE (pF) CAPACITANCE (pF) 5 4 DRAIN OFF 3 2 SOURCE OFF 1 05713-046 5 4 3 2 1 0 -5 VDD = +5V VSS = -5V TA = 25C DRAIN OFF SOURCE OFF 0 -15 -10 -5 0 VBIAS (V) 5 10 15 -4 -3 -2 -1 0 1 VBIAS (V) 2 3 4 5 Figure 26. ADG1209 Capacitance vs. Source Voltage, 15 V Dual Supply Figure 28. ADG1209 Capacitance vs. Source Voltage, 5 V Dual Supply Rev. 0 | Page 13 of 20 ADG1208/ADG1209 TERMINOLOGY RON Ohmic resistance between D and S. RON Difference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on terminals D, S. CS (Off) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. 0 | Page 14 of 20 ADG1208/ADG1209 TEST CIRCUITS V IS (OFF) A S D ID (OFF) A 05713-038 ID (ON) NC S D A 05713-039 S D IDS 05713-037 VS VD NC = NO CONNECT VD VS Figure 30. Off Leakage Figure 31. On Leakage Figure 29. On Resistance VDD 3V ADDRESS DRIVE (VIN) 0V 50% 50% VSS VSS S1 S2-S7 S8 VS8 OUTPUT D GND 300 35pF 05713-022 tr < 20ns tf < 20ns A0 VIN 50 A1 A2 VDD VS1 tTRANSITION tTRANSITION 90% ADG12081 2.4V EN OUTPUT 90% 1SIMILAR CONNECTION FOR ADG1209. Figure 32. Address to Output Switching Times, tTRANSITION VDD 3V ADDRESS DRIVE (VIN) 0V VIN 50 A0 A1 A2 S1 S2-S7 S8 80% OUTPUT 80% 2.4V EN GND VS VSS VDD VSS ADG12081 D OUTPUT 300 35pF 05713-023 tBBM 1SIMILAR CONNECTION FOR ADG1209. Figure 33. Break-Before-Make Delay, tBBM VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% A0 A1 A2 VDD VSS VSS S1 S2-S8 VS tON (EN) 0.9VO OUTPUT tOFF (EN) 0.9VO VIN 50 EN ADG12081 D GND OUTPUT 300 35pF 1SIMILAR CONNECTION FOR ADG1209. Figure 34. Enable Delay, tON (EN), tOFF (EN) Rev. 0 | Page 15 of 20 05713-024 ADG1208/ADG1209 VDD VSS VDD 3V A0 A1 VIN A2 VSS ADG12081 VOUT QINJ = CL x VOUT VOUT VS VIN 05713-025 RS S EN GND D CL 1nF VOUT 1SIMILAR CONNECTION FOR ADG1209. Figure 35. Charge Injection VDD 0.1F VSS 0.1F NETWORK ANALYZER NETWORK ANALYZER VOUT RL 50 VDD 0.1F VSS 0.1F VDD S VSS VDD S1 VSS 50 D 50 VS VOUT D S2 VS GND R 50 GND RL 50 05713-026 OFF ISOLATION = 20 log VS CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 36. Off Isolation Figure 38. Channel-to-Channel Crosstalk VDD 0.1F VSS 0.1F VDD VDD S VSS NETWORK ANALYZER VSS 0.1F AUDIO PRECISION RS S 0.1F 50 VS D RL 50 VOUT VDD VSS IN D VIN 05713-027 VS V p-p RL 10k VOUT 05713-029 GND INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH GND Figure 37. Bandwidth Figure 39. THD + Noise Rev. 0 | Page 16 of 20 05713-028 VOUT VOUT VS ADG1208/ADG1209 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 1 8 6.40 BSC PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 0.60 MAX 0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50 13 12 16 1 PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC PIN 1 INDICATOR TOP VIEW (BOTTOM VIEW) EXPOSED PAD 4 5 9 8 12 MAX 1.00 0.85 0.80 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model ADG1208YRUZ 1 ADG1208YRUZ-REEL71 ADG1208YCPZ-REEL1 ADG1208YCPZ-REEL71 ADG1209YRUZ1 ADG1209YRUZ-REEL71 ADG1209YCPZ-REEL1 ADG1209YCPZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option RU-16 RU-16 CP-16-4 CP-16-4 RU-16 RU-16 CP-16-4 CP-16-4 Z = Pb-free part. Rev. 0 | Page 17 of 20 ADG1208/ADG1209 NOTES Rev. 0 | Page 18 of 20 ADG1208/ADG1209 NOTES Rev. 0 | Page 19 of 20 ADG1208/ADG1209 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05713-0-4/06(0) Rev. 0 | Page 20 of 20 |
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