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16-Bit, 250 kSPS PulSAR ADC in MSOP AD7694
FEATURES
16-bit resolution with no missing codes Throughput: 250 kSPS @ 5 V INL: 4 LSB max S/(N + D): 92 dB @ 20 kHz THD: -106 dB @ 20 kHz Pseudo-differential analog input range: 0 V to VREF with VREF up to VDD No pipeline delay Single-supply operation: 2.7 V or 5 V Serial interface SPI(R)/QSPITM/MICROWIRETM/DSP-compatible Supply Current: 540 A @ 2.7 V/100 kSPS, 800 A @ 5 V/100 kSPS Standby current: 1 nA 8-lead MSOP package Improved 2nd Source to LTC1864 and LTC1864L
APPLICATION DIAGRAM
1V TO VDD 2.5V TO 5V
0 TO VREF IN+ IN-
REF
VDD SCK SDO CNV 3-WIRE SPI INTERFACE
05003-001
AD7694
GND
Figure 1.
Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADC
Type True Differential Pseudo Differential/Unipolar Unipolar 100 kSPS AD7684 AD7683 AD7680 250 kSPS AD7687 AD7685 AD7694 500 kSPS AD7688 AD7686
APPLICATIONS
Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control
GENERAL DESCRIPTION
The AD7694 is a 16-bit, charge redistribution, successive approximation, PulSARTM analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V to 5.25 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input, IN+, between 0 V to REF with respect to a ground sense, IN-. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7694 is housed in an 8-lead MSOP package with an operating temperature specified from -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7694 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 Application Information................................................................ 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Transfer Functions...................................................................... 12 Typical Connection Diagram ................................................... 13 Analog Input ............................................................................... 13 Driver Amplifier Choice............................................................ 13 Voltage Reference Input ............................................................ 14 Power Supply............................................................................... 14 Supplying the ADC from the Reference.................................. 14 Digital Interface.......................................................................... 14 Layout .......................................................................................... 15 Evaluating the AD7694's Performance .................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD7694 SPECIFICATIONS
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error1, TMIN to TMAX Gain Error Temperature Drift Offset Error1, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 16 0 -0.1 -0.1 1 A Grade Typ Max Min 16 0 -0.1 -0.1 B Grade Typ Max Unit Bits V V V nA
IN+ - IN- IN+ IN- Acquisition phase
VREF VDD + 0.1 0.1
VREF VDD + 0.1 0.1
1 See the Analog Input section. 16 -4 0.5 2 0.3 0.7 0.3 0.05 0 0 88 92 87 -106 -106 92 87
15 -6 REF = VDD = 5 V 0.5 2 0.3 0.7 0.3 0.05 0 0 90 86 -100 -100 89 86
+6 30 3.5
+4 15 3.5
VDD = 5 V 5% VDD = 4.75 V to 5.25 V VDD = 2.7 V to 4.75 V fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V
Bits LSB LSB LSB ppm/C mV ppm/C LSB kSPS kSPS dB2 dB dB dB dB dB
250 150
250 150
88
1 2
See Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 3 of 16
AD7694
VDD = 2.7 V to 5.25 V; VREF = VDD; TA = -40C to +85C, unless otherwise noted. Table 3.
Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS -3 dB Input Bandwidth DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD Operating Current VDD Standby Current1, 2 TEMPERATURE RANGE Specified Performance ISINK = +500 A ISOURCE = -500 A Specified performance VDD = 5 V, 100 kSPS throughput VDD = 2.7 V, 100 kSPS throughput VDD = 5 V, 25C TMIN to TMAX -40 Conditions Min 1 250 kSPS, VIN+ - VIN- = VREF/2 = 2.5 V 50 9 Typ Max VDD Unit V A MHz
VDD = 4.75 V VDD = 2.7 V VDD = 5.25 V VDD = 3.3 V
0.8 0.45 3.15 1.9 -1 -1
+1 +1
V V V V A A
Serial, 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VDD - 0.3 2.7 0.8 540 1 5.25 1.2 960 50 +85
V V V mA A nA C
1 2
With all digital inputs forced to VDD or GND, as required. During acquisition phase.
Rev. 0 | Page 4 of 16
AD7694 TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V; TA = -40C to +85C, unless otherwise stated. Table 4.
Parameter Conversion Time: CNV Rising Edge to Data Available Time between Conversions SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay CNV Low to SDO, D15 MSB Valid CNV High to SDO High Impedance Symbol tCONV tCYC tSCK tSCKL tSCKH tHSDO tDSDO tEN tDIS Min 4 50 20 20 5 20 60 60 Typ Max 3.2 Unit s s ns ns ns ns ns ns ns
VDD = 2.7 V to 4.75 V; TA = -40C to +85C, unless otherwise stated. Table 5.
Parameter Conversion Time: CNV Rising Edge to Data Available Time between Conversions SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay CNV Low to SDO, D15 MSB Valid CNV High to SDO High Impedance Symbol tCONV tCYC tSCK tSCKL tSCKH tHSDO tDSDO tEN tDIS Min 6.66 125 50 50 5 50 120 120 Typ Max 4.66 Unit s s ns ns ns ns ns ns ns
Rev. 0 | Page 5 of 16
AD7694 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Analog Inputs IN+1, IN-1 REF Supply Voltages VDD to GND Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) Rating GND - 0.3 V to VDD + 0.3 V or 130 mA GND - 0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -65C to +150C 150C 200C/W (MSOP-8) 44C/W (MSOP-8) 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
500A
IOL
TO SDO CL 50pF 500A IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
VIH VIL
tDELAY
VOH VOL
tDELAY
VOH VOL
05003-003
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 16
05003-002
AD7694 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF 1 IN+ 2 IN- 3
8
VDD SCK
05003-004
AD7694
7
TOP VIEW 6 SDO (Not to Scale) 5 CNV GND 4
Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic REF IN+ IN- GND CNV SDO SCK VDD Type1 AI AI AI P DI DO DI P Function Reference Input Voltage. The REF range is from 1 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a ceramic capacitor of a few F. Analog Input. It is referred to in IN-. The voltage range, i.e., the difference between IN+ and IN-, is 0 V to VREF. Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. On its leading edge, it initiates the conversions. It enables the SDO pin when low. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When CNV is low, the conversion result is shifted out by this clock. Power Supply.
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
Rev. 0 | Page 7 of 16
AD7694 TERMINOLOGY
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 19). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level 1/2 LSB above analog ground (38.1 V for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111...10 to 111...11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N + D) by the following formula ENOB = (S/[N + D]dB - 1.76)/6.02 and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N + D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and the time the input signal is held for conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function is applied.
Rev. 0 | Page 8 of 16
AD7694 TYPICAL PERFORMANCE CHARACTERISTICS
4 3 2 1 0 -1 -2
05003-005
POSITIVE INL = +0.68 LSB NEGATIVE INL = -1.14 LSB
2.0 1.5 1.0 0.5
POSITIVE DNL = +0.59 LSB NEGATIVE DNL = -0.56 LSB
DNL (LSB)
INL (LSB)
0 -0.5 -1.0
05003-008
-3 -4 0 16384 32768 CODE 49152
-1.5 -2.0 0 16384 32768 CODE 49152
65536
65536
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
12000 108568 10000 VDD = REF = 5V
8000 VDD = REF = 2.5V 7000 6000 65487
8000 5000
COUNTS
COUNTS
6000
4000 32418 3000 28148
4000 2000 2000 10003 0 0 24E0 24E1 24E2 24E3 24E4 24E5 CODE IN HEX 24E6 24E7 24E8 0 1
05003-006 05003-009 05003-010
12500 0 0 0
1000 0 0
251B 251C 251D 251E 251F 2520 2521 2522 2523 2524 2525 2526
0
27
2133
2808
50
1
0
0
CODE IN HEX
Figure 6. Histogram of a DC Input at the Code Center
Figure 9. Histogram of a DC Input at the Code Center
0 -20 16384 POINT FFT VDD = REF = 5V fS = 250kSPS fIN = 20.43kHz SNR = 92.5dB THD = -109.9dB SFDR = -111.0dB
0 -20 16384 POINT FFT VDD = REF = 2.5V fS = 150kSPS fIN = 20.43kHz SNR = 88.5dB THD = -102.7dB SFDR = -105.1dB
AMPLITUDE (dB OF FULL SCALE)
-40 -60 -80 -100 -120 -140 -160 -180 0 20 40
AMPLITUDE (dB OF FULL SCALE)
05003-007
-40 -60 -80 -100 -120 -140 -160 -180 0 10 20
60 80 FREQUENCY (kHz)
100
120
30 40 50 FREQUENCY (kHz)
60
70
Figure 7. FFT Plot
Figure 10. FFT Plot
Rev. 0 | Page 9 of 16
AD7694
100 17 1200
1000 95
SNR, S/[N+D] (dB)
16
OPERATING CURRENT (A)
fS = 100kSPS
800
90
15
ENOB (Bits)
SNR
600
S/[N+D] 85
ENOB 14
05003-011
400
200
05003-014
80 2.5
13 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0
0 2.5
3.0
3.5
4.0 SUPPLY (V)
4.5
5.0
5.5
Figure 11. SNR, S/(N + D), and ENOB vs. Reference Voltage
Figure 14. Operating Current vs. Supply
100
900 VDD = 5V, fS = 100kSPS 800
95
OPERATING CURRENT (A)
VREF = 5V, -10dB 90
S/[N+D] (dB)
700 600 500 400 300 200 100 0 -55
05003-015
VDD = 2.7V, fS = 100kSPS
VREF = 5V, -1dB 85 VREF = 2.5V, -1dB 80
75
05003-012
70 0 50 100 FREQUENCY (kHz) 150
200
-35
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 12. S/[N + D] vs. Frequency
Figure 15. Operating Current vs. Temperature
-80 VREF = 2.5V, -1dB -85
POWER-DOWN CURRENT (nA)
1000
750
-90
THD (dB)
-95 VREF = 5V, -1dB -100
500
-105 -110
250
05003-016
05003-013
-115 0 40 80 120 FREQUENCY (kHz) 160
200
0 -55
-35
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 13. THD vs. Frequency
Figure 16. Power-Down Current vs. Temperature
Rev. 0 | Page 10 of 16
AD7694
6
OFFSET ERROR, GAIN ERROR (LSB)
4
2 OFFSET ERROR 0
-2 GAIN ERROR -4
05003-017
-6 -55
-35
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 17. Offset and Gain Error vs. Temperature
Rev. 0 | Page 11 of 16
AD7694 APPLICATION INFORMATION
IN+ SWITCHES CONTROL MSB 32,768C 16,384C REF COMP GND 32,768C 16,384C MSB 4C 2C C C LSB SW- CNV
05003-018
LSB 4C 2C C C
SW+ BUSY CONTROL LOGIC OUTPUT CODE
IN-
Figure 18. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7694 is a low power, single-supply, 16-bit ADC using a successive approximation architecture. It is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes typically 4 W, ideal for battery-powered applications. The AD7694 provides the user with on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. The AD7694 is specified from 2.7 V to 5.25 V. It is housed in a 8-lead MSOP. The AD7694 is an improved second source to LTC1864 and LTC1864L. For even better performance, the AD7685 should be considered.
toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code. Because the AD7694 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7694 is shown in Figure 19 and Table 8.
ADC CODE (STRAIGHT BINARY)
111...111 111...110 111...101
CONVERTER OPERATION
The AD7694 is a successive approximation ADC based on a charge redistribution DAC. Figure 18 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase begins. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Thus, the differential voltage between the inputs, IN+ and IN-, captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4...VREF/65536). The control logic
000...010 000...001 000...000 -FS
-FS + 1 LSB
-FS + 0.5 LSB
ANALOG INPUT
Figure 19. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 V 0V Digital Output Code Hexadecimal FFFF2 8001 8000 7FFF 0001 00003
2
3
This is also the code for an overranged analog input (VIN+ - VIN- above VREF - VGND). This is also the code for an underranged analog input (VIN+ - VIN- below VGND).
Rev. 0 | Page 12 of 16
05003-019
+FS - 1 LSB +FS - 1.5 LSB
AD7694
(NOTE 1) REF 2.2 TO 10F (NOTE 2) 100nF 2.7V TO 5.25V
33 0 TO VREF (NOTE 3) 2.7nF (NOTE 4)
REF IN+
VDD SCK
AD7694
IN- GND
SDO CNV
3-WIRE INTERFACE
Figure 20. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 20 shows an example of the recommended application diagram for the AD7694.
the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7694 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7694 input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN-. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this will cause these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA, maximum. For instance, these conditions could eventually occur when the input buffer's (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part.
VDD D1 CPIN GND CIN
DRIVER AMPLIFIER CHOICE
Although the AD7694 is easy to drive, the driver amplifier needs to meet the following requirements: * The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7694. Note that the AD7694 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7694 analog input circuit 1-pole, low-pass filter made by R1 and C2 or by the external filter, if one is used. For ac applications, the driver needs to have a THD performance suitable to that of the AD7694. Figure 13 gives the THD versus frequency that the driver should exceed. For multichannel multiplexed applications, the driver amplifier and the AD7694 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier's data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
IN+ OR IN-
RIN
D2
05003-021
Figure 21. Equivalent Analog Input Circuit
*
This analog input structure allows the sampling of the differential signal between IN+ and IN-. By using this differential input, small signals common to both inputs are rejected. For instance, by using IN- to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input IN+ can be modeled as a parallel combination of the capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 and is a lumped component made up of some serial resistors and the onresistance of the switches. CIN is typically 30 pF and is mainly
*
Rev. 0 | Page 13 of 16
05003-020
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION. NOTE 2: CREF IS USUALLY A 10F CERAMIC CAPACITOR (X5R). NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
AD7694
Table 9. Recommended Driver Amplifiers
Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031 Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply and low power Small, low power, and low frequency High frequency and low power
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7694, with its low operating current, can be supplied directly using the reference circuit, as shown in Figure 23. The reference line can be driven by either * * * The system power supply directly A reference voltage with enough current output capability, such as the ADR43x A reference buffer, such as the AD8031, that can also filter the system power supply, as shown in Figure 23
5V OR 3V 5V OR 3V 10 5V OR 3V 10k 1F
VOLTAGE REFERENCE INPUT
The AD7694 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (e.g., an unbuffered reference voltage like the low temperature drift ADR43x reference or a reference buffer using the AD8031 or the AD8605), a 10 F (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If desired, smaller reference decoupling capacitor values down to 2.2 F can be used with a minimal impact on performance, especially DNL.
AD8031
(NOTE 1)
2.2 TO 10F
1F
REF
VDD
AD7694
05003-023
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER
Figure 23. Example of an Application Circuit
POWER SUPPLY
The AD7694 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 22. This makes the part ideal for a low sampling rate (even a few Hz) and low batterypowered applications.
10,000
DIGITAL INTERFACE
The AD7694 is compatible with SPI, QSPI, digital hosts, and DSPs, e.g., Blackfin(R) ADSP-BF53x or ADSP-219x. The connection diagram is shown in Figure 24 and the corresponding timing diagram is shown in Figure 25. A rising edge on CNV initiates a conversion and forces SDO to high impedance. When the conversion is complete, the AD7694 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
CONVERT CNV
1,000
OPERATING CURRENT (A)
VDD = 5V 100 VDD = 2.7V
10
DIGITAL HOST
SDO DATA IN
05003-024
1
AD7694
SCK
0.1
05003-022
CLK
0.01 10
Figure 24. Connection Diagram
100
1k 10k SAMPLING RATE (SPS)
100k
1M
Figure 22. Operating Current vs. Sampling Rate
Rev. 0 | Page 14 of 16
AD7694
tCYC
CNV
tCONV
ACQUISITION CONVERSION
tACQ
ACQUISITION
tSCK tSCKL
SCK 1 2 3 14 15 16*
tHSDO tEN
SDO D15 D14
tSCKH tDSDO
D13 D1 D0
05003-025
tDIS
*SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW
Figure 25. Serial Interface Timing
LAYOUT
The printed circuit board that houses the AD7694 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7694 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7694 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog section. In such a case, it should be joined underneath the AD7694s.
The AD7694 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. That is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low impedance traces. Finally, the power supply, VDD, of the AD7694 should be decoupled with a ceramic capacitor, typically 100 nF. This capacitor should be placed close to the AD7694 and connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7694'S PERFORMANCE
Other recommended layouts for the AD7694 are outlined in the evaluation board for the AD7694 (EVAL-AD7694). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2.
Rev. 0 | Page 15 of 16
AD7694 OUTLINE DIMENSIONS
3.00 BSC
8
5
3.00 BSC
4
4.90 BSC
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.15 0.00 0.38 0.22 COPLANARITY 0.10
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 26. 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions Shown in Millimeters
ORDERING GUIDE
Models AD7694ARM AD7694ARMRL7 AD7694BRM AD7694BRMRL7 EVAL-AD7694CB1 EVAL-CONTROL BRD22 EVAL-CONTROL BRD32 Integral Nonlinearity 6 LSB max 6 LSB max 4 LSB max 4 LSB max Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package (Option) MSOP (RM-8) MSOP (RM-8) MSOP (RM-8) MSOP (RM-8) Evaluation Board Controller Board Controller Board Transport Media, Quantity Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Branding C2H C2H C2J C2J
1 2
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05003-0-7/04(0)
Rev. 0 | Page 16 of 16
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