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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Features
* High Performance:
-7K 3 CL=2 fCK tCK tAC tAC Clock Frequency Clock Cycle Clock Access Time 1 133 7.5 -- 5.4 -75B, CL=3 133 7.5 -- 5.4 -8B, CL=2 100 10 -- 6 Units MHz ns ns ns
Clock Access Time 2
1. Terminated load. See AC Characteristics on page 37. 2. Unterminated load. See AC Characteristics on page 37. 3. tRP = tRCD = 2 CKs
* * * * * * * * * * * *
Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 8192 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II
* * * * * *
Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BA0/BA1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave
* -7K parts for PC133 2-2-2 operation -75B parts for PC133 3-3-3 operation -8B parts for PC100 2-2-2 operation
Description
The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC's advanced 256Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A12, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported.
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM
Pin Assignments for Planar Components (Top View)
VD D DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 VD D LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD V DD DQ0 V DDQ NC DQ1 V SSQ NC DQ2 V DDQ NC DQ3 V SSQ NC V DD NC WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD V DD NC V DDQ NC DQ0 V SSQ NC NC V DDQ NC DQ1 V SSQ NC V DD NC WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS NC V SSQ NC DQ3 V DDQ NC NC V SSQ NC DQ2 V DDQ NC V SS NC DQM CK CKE A12 A11 A9 A8 A7 A6 A5 A4 V SS V SS DQ7 V SSQ NC DQ6 V DDQ NC DQ5 V SSQ NC DQ4 V DDQ NC V SS NC DQM CK CKE A12 A11 A9 A8 A7 A6 A5 A4 V SS V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS NC UDQM CK CKE A12 A11 A9 A8 A7 A6 A5 A4 V SS
54-pin Plastic TSOP(II) 400 mil 16Mbit x 4 I/O x 4 Bank NT5SV64M4AT 8Mbit x 8 I/O x 4 Bank NT5SV32M8AT 4Mbit x 16 I/O x 4 Bank NT5SV16M16AT
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Pin Description
CK CKE (CKE0, CKE1) CS RAS CAS WE BA1, BA0 A0 - A12 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Bank Select Address Inputs DQ0-DQ15 DQM, LDQM, UDQM V DD V SS V DDQ V SSQ NC -- Data Input/Output Data Mask Power (+3.3V) Ground Power for DQs (+3.3V) Ground for DQs No Connection --
Input/Output Functional Description
Symbol CK CKE, CKE0, CKE1 CS RAS, CAS, WE BA1, BA0 Type Input Input Input Input Input Polarity Positive Edge Active High Active Low Active Low -- Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11), when sampled at the rising clock edge. Assume the x4 organization. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. Data Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A12
Input
--
DQ0 - DQ15
InputOutput
--
DQM LDQM UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output Active High enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. -- -- Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity.
V DD , VSS V DDQ V SSQ
Supply Supply
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Ordering Information
Speed Grade Organization Part Number Clock Frequency@CAS Latency NT5SV64M4AT-7K 64M x 4 NT5SV64M4AT-75B NT5SV64M4AT-8B NT5SV32M8AT-7K 32M x 8 NT5SV32M8AT-75B NT5SV32M8AT-8B NT5SV16M16AT-7K 16M x 16 NT5SV16M16AT-75B NT5SV16M16AT-8B NT5SV16M16AT-7KL 16M x 16 NT5SV16M16AT-75BL NT5SV16M16AT-8BL SP : Standard Power ; LP : Low power 143MHz@CL3 133MHz@CL3 125MHz@CL3 143MHz@CL3 133MHz@CL3 125MHz@CL3 143MHz@CL3 133MHz@CL3 125MHz@CL3 143MHz@CL3 133MHz@CL3 125MHz@CL3 133MHz@CL2 100MHz@CL2 100MHz@CL2 133MHz@CL2 100MHz@CL2 100MHz@CL2 133MHz@CL2 100MHz@CL2 100MHz@CL2 133MHz@CL2 100MHz@CL2 100MHz@CL2 Note PC133 , PC100 PC133 , PC100 PC100 PC133 , PC100 PC133 , PC100 PC100 PC133 , PC100 PC133 , PC100 PC100 PC133 , PC100 PC133 , PC100 PC100 LP 400mil 54PIN TSOP II Package Self Refresh
SP
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Block Diagram
CKE
CKE Buffer Row Decoder
Column Decoder
Column Decoder
Cell Array Memory Bank 0
Ro w Decoder
Cell Array Memory Bank 1
CK
CK Buffer
Sense Amplifiers
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 BA1 BA0 A10
Sense Amplifiers
Da ta Input/O utpu t Buffe rs DQM Column Decoder Cell Array Memory Bank 3 Sense Amplifiers
A ddress Buffers (15 )
Control Signa l G enerator
DQ0
Data Control Circu itry
DQ X
Column Address Counter
Refresh Counter
Mode Re gister
Column Decoder
Ro w Decoder
CS RAS CAS WE
Command Decoder
Cell Array Memory Bank 2
Sense Amplifiers
Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15).
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Row Decode r
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD +0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section.
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Mode Register Operation (Address Input For Mode Set)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register(Mx)
Burst Type
M3 0 1 Type Sequential Interleave
Operation Mode
M1 4 M13 M12 M11 M10 M9 0 0 0 0 0 0 0 0 0 0 0 1 M8 0 0 M7 0 0 Mode Normal Multiple Burst with Single Write
Burst Length
Length M2 0 0 0 M1 0 0 1 1 0 0 1 1 M0 Sequential Interleave 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Reserved 1 2 4 8 Reserved Reserved Reserved Reserved
CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
0 1 1 1 1
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A12, BA0, and BA1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organization: x4, x8, or x16). Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length 2 Starting Address (A2 A1 A0) xx0 xx1 x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Sequential Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Note: Page length is a function of I/O organization and column addressing. x4 organization (CA0-CA9, CA11); Page Length = 2048 bits x8 organization (CA0-CA9); Page Length = 1024 bits x16 organization (CA0-CA8); Page Length = 512 bits
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (t RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC ). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD). The maximum time that each bank can be held active is specified as tRAS(max).
Bank Activate Command Cycle
(CAS Latency = 3, t RCD = 3)
T0 CK
..........
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
ADDRESS
Bank A Row Addr. R A S-CAS delay (tRCD) Bank A Activate
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
R A S - R A S delay time (tRRD) Write A with Auto Precharge Bank B Activate Bank A Activate
COMMAND
: "H" or "L"
NOP
NOP
..........
NOP
NOP
RAS Cycle time ( tRC )
Bank Select
The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation.
Bank Selection Bits
BA0 0 1 0 1 BA1 0 0 1 1 Bank Bank 0 Bank 1 Bank 2 Bank 3
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock's rising edge after the necessary RAS to CAS delay (t RCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF ) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle.
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
C A S latency = 2
t CK2, DQs
C A S latency = 3
DOUT A 0
DOUT A 1
DOUT A2
DOUT A 3
t CK3, DQs
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears.
Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
C A S latency = 2
t CK2, DQs
C A S latency = 3
DOUT A 0
DOUT B 0
DOUT B1
DOUT B 2
DOUT B3
t CK3, DQs
DOUT A 0
DOUT B 0
DOUT B1
DOUT B 2
DOUT B 3
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CK
DQM high for CAS latency = 2 only. Required to mask first bit of READ data.
T1
T2
T3
T4
T5
T6
T7
T8
DQM
COMMAND
NOP
READ A
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
C A S latency = 2
t CK2, DQs
C A S latency = 3
DIN A 0
DIN A 1
DIN A 2
DIN A 3
t CK3, DQs
DIN A 0
DIN A 1
DIN A 2
DIN A 3
: "H" or "L"
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
DQM
COMMAND
READ A
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CL = 2: DQM needed to mask first, second bit of READ data.
C A S latency = 2 DIN A 0 DIN A 1 DIN A 2 DIN A 3
t CK2, DQs
CL = 3: DQM needed to mask first bit of READ data.
C A S latency = 3 DIN A 0 DIN A 1 DIN A 2 DIN A 3
t CK3, DQs
: DQM high for CAS latency = 2 : DQM high for CAS latency = 3
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DIN A 0
DIN A 1
DIN A 2
DIN A 3
The first data element and the Write are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 CK Interval
DQs
DIN A 0
DIN B 0
DIN B 1
DIN B 2
DIN B 3
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
t CK2, DQs
CAS latency = 3
DIN A 0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
tCK3 , DQs
DIN A 0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
: "H" or "L"
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention.
REV 1.0
May, 2001
15
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Non-Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
WRITE A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
C A S latency = 2
tCK2, DQs
CAS latency = 3
DIN A 0
DIN A 1
DOUT B0
DOUT B 1
DOUT B2
DOUT B 3
tCK3, DQs
DIN A 0
DIN A 1
DOUT B 0
DOUT B 1
DOUT B2
DOUT B 3
: "H" or "L"
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention.
REV 1.0
May, 2001
16
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP ) has been satisfied. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS(min). If this interval does not satisfy t RAS(min) then t RCD must be extended.
Burst Read with Auto-Precharge
(Burst Length = 1, CAS Latency = 2, 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tRP
DOUT A 0
*
tRP
DOUT A 0
t CK2, DQs
CAS latency = 3
*
at completion t. *Bank can be reactivated cycle time andofspeed sort. t is a function of clock
RP
t CK3, DQs
Begin Auto-precharge
See the Clock Frequency and Latency table.
RP
REV 1.0
May, 2001
17
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Read with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK
COMMAND
READ A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tRP
DOUT A 0 DOUT A 1
*
tRP
tCK2, DQs
CAS latency = 3
*
DOUT A 1
tCK3, DQs
Begin Auto-precharge
DOUT A0
*
Bank can be reactivated at completion of t R P. tR P is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Burst Read with Auto-Precharge
*
(Burst Length = 4, CAS Latency = 2, 3)
T0 CK
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
READ A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tRP
DOUT A 0 DOUT A1 DOUT A 2 DOUT A 3
*
tRP
t CK2, DQs
CAS latency = 3
*
DOUT A3 RP
t CK3, DQs
DOUT A0
DOUT A 1
DOUT A 2
Begin Auto-precharge
t. *Bankiscan be reactivated at completion ofspeed sort. t a function of clock cycle time and
RP
See the Clock Frequency and Latency table.
*
REV 1.0
May, 2001
18
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay t RP .
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
Auto-Precharge
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tRP
DOUT A 0 DOUT A1
*
DOUT B 0 DOUT B 1 DOUT B2 DOUT B 3
t CK2, DQs
CAS latency = 3
tRP
DOUT A0 DOUT A 1
*
DOUT B 0 DOUT B 1 DOUT B2 DOUT B 3 RP RP
t CK3, DQs
be reactivated completion of t . *Bankiscanfunction of clockatcycle time and speed sort. t a See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
Auto-Precharge
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
NOP
CAS latency = 2
tRP
DOUT A 0 D IN B0 DIN B 1
*
D IN B2 D IN B 3 D IN B4
t CK2, DQs
DQM
be reactivated t. *Bankiscanfunction of clock at completion ofspeed sort. t a cycle time and
RP RP
.
See the Clock Frequency and Latency table .
REV 1.0
May, 2001
19
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing autoprecharge cannot be reactivated until tDAL , Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
T0 CK
T1
T2
T3
T4
T5
(Burst Length = 2, CAS Latency = 2, 3) T6 T7 T8
COMMAND
WRITE A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tDAL
DIN A 0 DIN A 1
*
tDAL
t CK2, DQs
CAS latency = 3
*
can be reactivated completion of t . *Bank is a function of clockatcycle time and speed sort. t
DAL DAL
t CK3, DQs
DIN A 0
DIN A 1
See the Clock Frequency and Latency table.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until t DAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3) T6 T7 T8
T0 CK
T1
T2
T3
T4
T5
COMMAND
WRITE A
Auto-Precharge
NOP
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 3
tDAL
DIN A 0 DIN A 1 DIN B 0 DIN B 1 DIN B2
*
DIN B3
t CK3, DQs
be reactivated completion of t . *Bankiscanfunction of clockatcycle time and speed sort. t a
DAL DAL
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
20
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
WRITE A
Auto-Precharge
NOP
NOP
READ B
NOP
NOP
NOP
NOP
NOP
CAS latency = 3
tDAL
DIN A 0 DIN A1 DIN A 2 DOUT B 0
*
DOUT B 1 DOUT B 2
tCK3, DQs
* Bank A can be reactivated at completion of tDAL .
See the Clock Frequency and Latency table.
tDAL is a function of clock cycle time and speed sort.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10 LOW HIGH Bank Select BA0, BA1 DON'T CARE Precharged Bank(s) Single bank defined by BA0, BA1 All Banks
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL , Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP ).
REV 1.0
May, 2001
21
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Burst Read Followed by the Precharge Command
(Burst Length = 4, CAS Latency = 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ Ax 0
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
tRP
C A S latency = 3 DOUT Ax 0 DOUT Ax1 DOUT Ax 2 D O U T A x3
*
tCK2, DQs
*
Burst Write Followed by the Precharge Command
Bank A can be reactivated at completion of t RP .
tR P is a function of clock cycle and speed sort.
(Burst Length = 2, CAS Latency = 2) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
Activate Bank Ax
NOP
WRITE Ax 0
NOP
NOP
Precharge A
NOP
NOP
tDPL
tRP
*
CAS latency = 2
t CK2, DQs
DIN Ax 0
DIN Ax 1
can reactivated at completion of t *tBankand t be are functions of clock cycle and .speed sort.
RP DPL RP
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
22
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
(Burst Length = 8, CAS Latency = 2, 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
tRP
C A S latency = 2
*
tRP
t CK2, DQs
DOUT Ax 0
DOUT Ax1
DOUT Ax 2
DOUT Ax 3
*
D O U T A x3
C A S latency = 3
t CK3, DQs
DOUT Ax 0
DOUT Ax1
DOUT Ax 2
*
Bank A can be reactivated at completion of tRP . tR P is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table.
REV 1.0
May, 2001
23
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, t DPL.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3) T0 CK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
NOP
WRITE Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
DQM
tDPL
CAS latency = 2
tCK2, DQs
DIN Ax 0
DIN Ax 1
DIN Ax 2
tDPL
CAS latency = 3
tCK3, DQs
DIN Ax 0
DIN Ax 1
DIN Ax 2
tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time.
REV 1.0
May, 2001
24
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP ) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC ).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the devic e exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC ) plus the Self Refresh exit time (t SREX ).
REV 1.0
May, 2001
25
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (t RP ) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (t REF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
Tm CK
tCK
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+ 8
CKE
tCES(min)
COMMAND
NOP
COMMAND
NOP
NOP
NOP
NOP
NOP
: "H" or "L"
REV 1.0
May, 2001
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency.
Data Mask Activated during a Read Cycle
(Burst Length = 4, CAS Latency = 2)
T0 CK T1 T2 T3 T4 T5 T6 T7 T8
DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DOUT A0
DOUT A 1
A two-clock delay before the DQs become Hi-Z
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.
REV 1.0
May, 2001
27
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
(Burst Length = 4, CAS Latency = 2) T6 T7 T8
T0 CK
T1
T2
T3
T4
T5
CKE
A one clock delay before suspend operation starts
A one clock delay to exit the Suspend command
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DOUT A 0
DOUT A 1
DOUT A2
DOUT element at the DQs when the suspend operation starts is held valid
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited.
Clock Suspend during a Write Cycle
(Burst Length = 4, CAS Latency = 2)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
CKE
A one clock delay before suspend operation starts
A one clock delay to exit the Suspend command
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DIN A 0
DIN A 1
DIN A 2
DIN A 3
DIN is masked during the Clock Suspend Period
REV 1.0
May, 2001
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Command Truth Table (See note 1)
CKE Function Mode Register Set Auto (CBR) Refresh Entry Self Refresh Exit Self Refresh Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto-Precharge Read Read with Auto-Precharge Reserved No Operation Device Deselect Clock Suspend Mode Entry Clock Suspend Mode Exit Data Write/Output Enable Data Mask/Output Disable Power Down Mode Entry Any Any Active Active Active Active Idle/Active Any (Power Down) Device State Idle Idle Idle Idle (SelfRefresh) See Current State Table See Current State Table Idle Active Active Active Active Previous Cycle H H H L H H H H H H H H H H H L H H H Current Cycle X H L H X X X X X X X X X X L H X X L CS L L L H L L L L L L L L L L H X X X X H L H L H L Power Down Mode Exit RAS L L L X H L L L H H H H H H X X X X X X H X H CAS L L L X H H H H L L L L H H X X X X X X H X H WE L H H X H L L H L L H H L H X X X X X X H X H X X X X 6, 7 X X X X X X X X X X X X X L H X X BS X BS BS BS BS BS X X X X X X X X X L H X X X 2 2 2 2 2 2 DQM X X X X X BA0, BA1 A10 OP Code X X X X A12, A11, A9-A0 Notes
Row Address L H L H X X X X X X X X Column Column Column Column X X X X X X X X
4
5
6, 7
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3. 3. Not applicable. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cy cles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the devic e state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can't remai n in this mode longer than the Refresh period (t REF ) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
REV 1.0
May, 2001
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Clock Enable (CKE) Truth Table
CKE Current State Previous Cycle H L L Self Refresh L L L L H L Power Down L L H H H H H All Banks Idle H H H H H L H Any State other than listed above H L L H L H H H H H L L L L L X H L H L L X H L L L L H L L L L X X X X X X X X H L L L X H L L L X X X X X X X X X H L L X X H L L X X X X X X X X X X H L X X X H L X X X X X X X X X X X X OP Code X X X X X Entry Self Refresh Mode Register Set Power Down Refer to operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 5 4 Refer to the Idle State section of the Current State Truth Table X X OP Code CBR Refresh Mode Register Set 4 3 3 3 4 Refer to the Idle State section of the Current State Truth Table X X X X ILLEGAL Maintain Power Down Mode 3 3 3 2 Current Cycle X H H H H H L X H CS X H L L L L X X H RAS X X H H H L X X X Command CAS X X H H L X X X X WE X X H L X X X X X BA0, BA1 X X X X X X X X X Action A 12 - A0 X X X X X X X X X INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 1 2 2 2 2 2 Notes
1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t CES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 26). 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle stat e. 5. Must be a legal command as defined in the Current State Truth Table.
REV 1.0
May, 2001
30
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Current State Truth Table
Current State CS L L L Idle L L L L H L L L Row Active L L L L H L L L Read L L L L H L L L Write L L L L H RAS CAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X
(Part 1 of 3)(See note 1)
Command BA0,BA1 A12 - A0 X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write w/o Precharge Read w/o Precharge No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect OP Code Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Continue the Burst Continue the Burst 4 8, 9 8, 9 4 8, 9 8, 9 6 4 7, 8 7, 8 5 4 4 Notes 2 2, 3
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied.
REV 1.0
May, 2001
31
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Current State Truth Table
Current State CS L L L Read with Auto Precharge L L L L H L L L Write with Auto Precharge L L L L H L L L Precharging L L L L H L L L Row Activating L L L L H RAS CAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X
(Part 2 of 3)(See note 1)
Command BA0,BA1 A12 - A0 X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 4, 10 4 4 4 4 4 4 4 4 4 4 4 4 4 OP Code Action Notes
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied.
REV 1.0
May, 2001
32
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Current State Truth Table
Current State CS L L L Write Recovering L L L L H L L Write Recovering with Auto Precharge L L L L L H L L L Refreshing L L L L H L L L Mode Register Accessing L L L L H RAS CAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X
(Part 3 of 3)(See note 1)
Command BA0,BA1 A12 - A0 X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row Active after tDPL No Operation; Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles 4 4 4, 9 4, 9 4 4 9 9 OP Code Action Notes
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied.
REV 1.0
May, 2001
33
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Absolute Maximum Ratings
Symbol VD D V DDQ V IN V OUT TA TSTG PD IOUT Parameter Power Supply Voltage Power Supply Voltage for Output Input Voltage Output Voltage Operating Temperature (ambient) Storage Temperature Power Dissipation Short Circuit Output Current Rating -0.3 to +4.6 -0.3 to +4.6 -0.3 to V DD+0.3 -0.3 to V DD+0.3 0 to +70 -55 to +125 1.0 50 Units V V V V C C W mA Notes 1 1 1 1 1 1 1 1
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA
Symbol V DD V DDQ VI H V IL Parameter Min. Supply Voltage Supply Voltage for Output Input High Voltage Input Low Voltage 3.0 3.0 2.0 -0.3
= 0C to 70C)
Rating Units Typ. 3.3 3.3 -- -- Max. 3.6 3.6 V DD + 0.3 0.8 V V V V 1 1 1, 2 1, 3 Notes
1. All voltages referenced to VSS and V SSQ. 2. V IH (max) = V DD + 1.2V for pulse width 5ns. 3. V IL (min) = V SS - 1.2V for pulse width 5ns.
Capacitance
Symbol CI CO
(TA = 25C, f = 1MHz, V DD = 3.3V 0.3V)
Parameter Min. 2.5 2.5 4.0 Typ 3.0 2.8 4.5 Max. 3.8 3.5 6.5 Units pF pF pF Notes
Input Capacitance (A0-A12, BA0, BA1, CS, RAS, CAS , WE, CKE, DQM) Input Capacitance (CK) Output Capacitance (DQ0 - DQ15)
REV 1.0
May, 2001
34
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM DC Electrical Characteristics (T A = 0 to +70C, VDD
Symbol II(L) IO(L) V OH V OL Parameter Input Leakage Current, any input (0.0V V I N V DD), All Other Pins Not Under Test = 0V Output Leakage Current (D OUT is disabled, 0.0V V OUT V DDQ ) Output Level (LVTTL) Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL) Output "L" Level Voltage (IOUT = +2.0mA)
= 3.3V 0.3V)
Min. -1 -1 2.4 -- Max. +1 +1 -- 0.4 Units A A V V Notes 1
DC Output Load Circuit
3.3 V 1200 Output 50pF 870 V O H (DC) = 2.4V, I O H = -2mA V OL (DC) = 0.4V, I OL = 2mA
REV 1.0
May, 2001
35
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Operating, Standby, and Refresh Currents (TA = 0 to +70C, VDD
Parameter Symbol Test Condition -7K 1 bank operation tR C = tRC(min), t CK = min Active-Precharge command cycling without burst operation CKE V IL (max), tC K = min, CS = V I H(min) CKE V IL (max), tC K = Infinity, CS = V I H(min) CKE V I H(min), tCK = min, CS = V IH (min) CKE V I H(min), tCK = Infinity, CKE V I H(min), tCK = min, CS = V IH (min) CKE V IL (max), tC K = min, tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 tCK = min, t R C = tRC(min) CBR command cycling CKE 0.2V SP LP -75 B -8B
= 3.3V 0.3V)
Speed Units Notes
Operating Current
IC C 1
130
120
115
mA
1, 2, 3
Precharge Standby Current in Power Down Mode
ICC2P ICC2PS ICC2N ICC2NS
2 2 30 8 60 6
2 2 30 8 60 6
2 2 20 8 45 6
mA mA mA mA mA mA
1 1 1, 5 1, 7 1, 5 1, 6
Precharge Standby Current in Non-Power Down Mode
No Operating Current (Active state: 4 bank)
ICC3N ICC3P
Operating Current (Burst Mode)
IC C 4
120
120
90
mA
1, 3, 4
Auto (CBR) Refresh Current
IC C 5
175 3 1.2
175 3 1.2
155 3 1.2
mA mA mA
1 1,8 8
Self Refresh Current
IC C 6
1. Currents given are valid for a single device. . 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tC K and t R C . Input signals are changed up to three times during tR C (min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tC K (min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. 8. SP : Standard power ; LP : Lower power
REV 1.0
May, 2001
36
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM AC Characteristics
(TA = 0 to +70C, VDD = 3.3V 0.3V)
1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and V IL (or between VIL and VIH ) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and V IH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and V IH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and V IH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
tT Clock tCKL tCKH V IH 1.4V V IL Output Zo = 50 50pF AC Output Load Circuit (A) Vtt = 1.4V 50
tSETUP
tHOLD 1.4V
Input
Output tAC tLZ Output 1.4V tO H Zo = 50 50pF AC Output Load Circuit (B)
REV 1.0
May, 2001
37
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Clock and Clock Enable Parameters
Symbol tCK3 tCK2 tAC3 (A) tAC2 (A) tAC3 (B) tAC2 (B) tCKH tCKL tCES tCEH tSB tT Parameter Clock Cycle Time, CAS Latency = 3 Clock Cycle Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Clock Enable Set-up Time Clock Enable Hold Time Power down mode Entry Time Transition Time (Rise and Fall) -7 K Min. 7 7.5 -- -- -- -- 2.5 2.5 1.5 0.8 0 0.5 Max. 1000 1000 -- -- 5.4 5.4 -- -- -- -- 7.5 10 Min. 7.5 10 -- -- -- -- 2.5 2.5 1.5 0.8 0 0.5 -75B Max. 1000 -- -- -- 5.4 6 -- -- -- -- 7.5 10 Min. 8 10 -- -- -- -- 3 3 2 1 0 0.5 -8B Max. 1000 1000 -- -- 6 6 -- -- -- -- 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 2 Notes
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
-7K Symbol tCS tC H tAS tAH tR C D tR C tRAS tRP tR R D tC C D Parameter Min. Command Setup Time Command Hold Time Address and Bank Select Set-up Time Address and Bank Select Hold Time RAS to CAS Delay Bank Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS Delay Time 1.5 0.8 1.5 0.8 15 60 45 15 15 1 Max. -- -- -- -- -- -- 100K -- -- -- Min. 1.5 0.8 1.5 0.8 20 67.5 45 20 15 1 Max. -- -- -- -- -- -- 100K -- -- -- Min. 2 1 2 1 20 70 50 20 20 1 Max. -- -- -- -- -- -- 100K -- -- -- ns ns ns ns ns ns ns ns ns CK 1 1 1 1 1 -75B -8B Units Notes
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-7K Symbol tRSC Parameter Min. Mode Register Set Cycle Time 15 Max. -- Min. 15 Max. -- Min. 20 Max. -- ns -75B -8B Units
REV 1.0
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(c) NANYA TECHNOLOGY CORP. All rights reserved.
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Read Cycle
-7K Symbol Parameter Min. -- tOH tLZ tHZ3 tHZ2 tDQZ 1. 2. 3. 4. Data Out Hold Time 2.7 Data Out to Low Impedance Time Data Out to High Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 0 3 3 2 -- -- 5.4 5.4 -- 2.7 0 3 3 2 -- -- 5.4 6 -- 3 0 3 3 2 -- -- 6 6 -- ns ns ns ns CK 3 3 2, 4 Max. -- Min. -- Max. -- Min. 2.5 Max. -- ns 1 -75B -8B Units Notes
AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
-7K Symbol tREF tSREX Refresh Period Self Refresh Exit Time Parameter Min. -- 10 Max. 64 -- Min. -- 10 Max. 64 -- Min. -- 10 Max. 64 -- ms ns 1 -75B -8B Units Notes
1. 8192 a uto refresh cycles.
Write Cycle
-7K Symbol tDS tD H tDPL tDAL3 tDAL2 tDQW Parameter Min. Data In Set-up Time Data In Hold Time Data input to Precharge Data In to Active Delay CAS Latency = 3 Data In to Active Delay CAS Latency = 2 DQM Write Mask Latency 1.5 0.8 15 5 5 0 Max. -- -- -- -- -- -- Min. 1.5 0.8 15 5 5 0 Max. -- -- -- -- -- -- Min. 2 1 20 5 5 0 Max. -- -- -- -- -- -- ns ns ns CK CK CK -75B -8B Units
REV 1.0
May, 2001
39
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Clock Frequency and Latency
Symbol fCK tCK tAA tRP tRCD tRC tRAS tDPL tDAL tRRD tCCD tWL tDQW tDQZ tCSL Clock Frequency Clock Cycle Time CAS Latency Precharge Time RAS to CAS Delay Bank Cycle Time Minimum Bank Active Time Data In to Precharge Data In to Active/Refresh Bank to Bank Delay Time CAS to CAS Delay Time Write Latency DQM Write Mask Latency DQM Data Disable Latency Clock Suspend Latency Parameter 143 7 3 3 3 9 6 2 5 2 1 0 0 2 1 -7K 133 7.5 2 2 2 8 6 2 5 2 1 0 0 2 1 133 7.5 3 3 3 9 6 2 5 2 1 0 0 2 1 -75B 100 10 2 2 2 7 5 2 5 2 1 0 0 2 1 125 8 3 3 3 9 6 2 5 2 1 0 0 2 1 -8B 100 10 2 2 2 7 5 2 5 2 1 0 0 2 1 Units MHz ns CK CK CK CK CK CK CK CK CK CK CK CK CK
REV 1.0
May, 2001
40
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NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM
Timing Diagrams
Page
AC Parameters for Write Timing..................................................................................................................................42 AC Parameters for Read Timing (3/3/3), BL=4 ...........................................................................................................43 AC Parameters for Read Timing (2/2/2), BL=2 ...........................................................................................................44 AC Parameters for Read Timing (3/2/2), BL=2 ...........................................................................................................45 AC Parameters for Read Timing (3/3/3), BL=2 ...........................................................................................................46 Mode Register Set.......................................................................................................................................................47 Power on Sequence and Auto Refresh (CBR) ............................................................................................................48 Clock Suspension / DQM During Burst Read .............................................................................................................49 Clock Suspension / DQM During Burst Write ............................................................................................................50 Power Down Mode and Clock Suspend......................................................................................................................51 Auto Refresh (CBR).....................................................................................................................................................52 Self Refresh (Entry and Exit) .......................................................................................................................................53 Random Row Read (Interleaving Banks) with Precharge, BL=8.................................................................................54 Random Row Read (Interleaving Banks) with Auto-precharge, BL=8 ........................................................................55 Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8 ........................................................................56 Random Row Write (Interleaving Banks) with Precharge, BL=8.................................................................................57 Read/Write Cycle ...............................................................................................................................................58 Interleaved Column Read Cycle..................................................................................................................................59 Auto Precharge after a Read Burst, BL=4...................................................................................................................60 Auto Precharge after a Write Burst, BL=4...................................................................................................................61 Burst Read and Single Write Operation ......................................................................................................................62 CS Function (Only CS signal needs to be asserted at minimum rate) ........................................................................63
REV 1.0
May, 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 2)
T3 T11 T13 T14 T15 T16 T17 T18 T 19 T20 T21 T22 T4 T5 T6 T7 T8 T9 T10 T 12
T0
T1
T2
CK tCK2 tCS tC H tC EH
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
t CKH
tC KL
CKE
tCES
256Mb Synchronous DRAM
CS
AC Parameters for Write Timing
RAS
CAS
WE
42
tAH
RBx RAy CAx RBx CBx R Ay CAy
* BA1
A10
RAx
RAz
RBy
tAS
RAz R By
A0-A9, A11,A12
RAx
DQM tR CD tDAL tR C
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3
tDS tDH
Ay0 Ay1 Ay2 Ay3
tD PL tRP tRR D
DQ
Hi-Z
*BA0 = "L"
Bank2,3 = Idle
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Ac tivate Command Bank 0
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 1 Command Bank 0 Bank 1
Write Command Bank 0
Prec harge Command Bank 0
Ac tivate Command Bank 0
Ac tivate Command Bank 1
tDPL and tDAL depend on clock cycle time and speed sort. S ee the Clock Frequency and Latency Table.
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 3; tRCD , tRP = 3)
T1 T 10 T 11 T12 T13 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK tCK 3
Begin Auto Prec harge Bank 0 Begin Auto Precharge Bank 1
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CKE
256Mb Synchronous DRAM
CS
RAS
AC Parameters for Read Timing (3/3/3)
CAS
WE
43
RBx C Ax RBx CBx
* BA1
A10
R Ax
R Ay
A0-A9, A11, A12 tRRD tRAS tRC tAC3 t RCD
A x0
R Ax
R Ay
DQM
tRP t OH
Hi-Z
Ax1 Ax2 Ax3 Bx0 Bx1 Bx2
DQ
* BA0 = "L"
R ead w ith Auto Precharge Com mand Bank 0
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Ac tiv ate Comm and Bank 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3 = Idle
Ac tivate C omm and Bank 0
R ead with Auto Precharge C omm and Bank 1
Ac tiv ate Com mand Bank 0
\
May, 2001
REV 1.0
(Burst length = 2, CAS latency = 2; tRCD , tRP = 2)
T1 T 11 T12 T 13 T2 T3 T4 T5 T6 T7 T8 T9 T10
T0
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK tCK2 tCS tCH
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
tCKH tCKL tCEH
CKE
tCES
256Mb Synchronous DRAM
CS
RAS
AC Parameters for Read Timing (2/2/2)
CAS
WE
44
tAH
R Ax RBx R Ay R Ax CAx RBx CB x R Ay
* BA1
A10
tAS
A0-A9, A11, A12 tRRD t RAS(mi n) tRC t OH tHZ
Ax0 Ax1
DQM tA C2 tRCD tLZ
tRP tRP tHZ
Bx0 Bx1
Note: Must satisfy t RAS(min) For -260 : extend t RC D1 clo ck
DQ
Hi-Z
* BA0 = "L"
Ac tivate C omm and Bank 0
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Read w ith Auto Prec harge Com mand Bank 0 Ac tiv ate C omm and Bank 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3 = Idle
R ead with Auto Precharge C omm and Bank 1
Ac tivate C omm and Bank 0
\
May, 2001
REV 1.0
(Burst length = 2, CAS latency = 3; tRCD , tRP = 2)
T1 T 10 T11 T 12 T13 T2 T3 T4 T5 T6 T7 T8 T9
T0
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK t CK3 tCS t CH
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
tCKH tCKL t CEH
CKE
tCES
256Mb Synchronous DRAM
CS
RAS
AC Parameters for Read Timing (3/2/2)
CAS
WE
45
tA H
RBx RAy CAx RBx C Bx RAy
* BA1
A10
R Ax
tAS
A0-A9, A11, A12 tRRD tRAS tRC tAC3 tRCD tL Z
Ax0
R Ax
DQM
t RP tO H tHZ
Ax 1
No te: Must satisfy t RAS(min). Exten ded tR CD 1 clo ck. No t requir ed for BL 4.
tRP tHZ
Bx0 Bx 1
DQ
Hi-Z
* BA0=" L"
(c) NANYA TECHNOLOGY CORP. All rights reserved.
R ead w ith Auto Precharge Com mand Bank 0 Ac tiv ate Com mand Bank 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3=Idle
Activate C ommand Bank 0
R ead with Auto Precharge C omm and Bank 1
Ac tiv ate Comm and Bank 0
\
May, 2001
REV 1.0
(Burst length = 2, CAS latency = 3; tRCD , tRP = 3)
T2 T 10 T 11 T12 T13 T14 T3 T4 T5 T6 T7 T8 T9
T0
T1
CK tCK3
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CKE tCEH
256Mb Synchronous DRAM
CS
RAS
AC Parameters for Read Timing (3/3/3)
CAS
WE
46
RB x RAy CAx RB x CB x RAy
* BA1
A10
R Ax
A0-A9, A11, A12 t RRD tRA S (mIn ) tRP tRC tAC3 tOH
R Ax
DQM
tRP
tRCD
Ax0 Ax1 Bx0 Bx1
DQ
H i-Z
Bank 2,3= Idle
*BA0=" L" Bank 0
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Ac tiv ate Com mand Bank 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Ac tiv ate Com mand Bank 0
Note: Must satisfy tRAS(min). R ead w ith E xtende d tRC D not r equired Auto Precharge for BL4. C omm and
Read w ith Auto Prec harge Com mand Bank 1
Activate Com mand Bank 0
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Mode Register Set
\
(CAS latency = 2)
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T 17
T18
T19
T20
T 21
T22
tRSC
T2
tRP
T0
tCK2
BA0,BA1
CS
RAS
CAS
WE
CKE
A10,A11, A12
REV 1.0
May, 2001
47
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
A0-A9
DQM
CK
DQ
H i-Z
Precharge C omm and All Banks
T1
M ode Regis ter Set Com mand
A ddress Ke y
T3
T4
Any C omm and
T5
T6
\
May, 2001
T3 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T4 T5 T6 T7 T8 T9 T10
REV 1.0
Minimum of 8 Refresh Cycles are required 2 Clock min.
T0
T1
T2
CK
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
tCK
CKE
High level is required
256Mb Synchronous DRAM
CS
RAS
CAS
WE
Power-On Sequence and Auto Refresh (CBR)
48
Address Key
BS
A10
A0-A9, A11,A12
DQM tRC
DQ
Hi-Z
tRP
Precharge 1st Auto Refresh Command Command All Banks
8th Auto Refresh Command
Mode Register Set Command
Any Command
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Inputs must be stable for 200s
\
May, 2001
REV 1.0
(Burst length = 8, CAS latency = 3; tRCD = 3)
T3 T13 T14 T15 T16 T18 T19 T20 T22 T4 T5 T6 T7 T8 T9 T10 T11 T12 T17 T21
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK tCES tCEH
t CK 3
CKE
256Mb Synchronous DRAM
CS
RAS
CAS
Clock Suspension / DQM During Burst Read
WE
49
CA x Ax0 Ax1 Ax2 Ax3
* BA1
A10
R Ax
A0-A9, A11,A12
R Ax
DQM tHZ
Ax4 Ax6 Ax7
DQ
Hi-Z
* BA0=" L"
(c) NANYA TECHNOLOGY CORP. All rights reserved. Clock Suspend 1 Cycle Clock Suspend 2 Cycles
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3=Idle
Activate Command Bank 0
Read Command Bank 0
Clock Suspend 3 Cycles
\
May, 2001
REV 1.0
(Burst length = 8, CAS latency = 3; tRCD = 3)
T3 T11 T12 T13 T 14 T15 T 16 T 17 T 18 T19 T20 T21 T 22 T4 T5 T6 T7 T8 T9 T10
T0
T1
T2
CK
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
tCK3
CKE
256Mb Synchronous DRAM
CS
RAS
CAS
Clock Suspension / DQM During Burst Write
WE
50
CA x DAx0 DAx1 DAx2 DAx3 D Ax5
* BA1
A10
R Ax
A0-A9, A11, A12
R Ax
DQM
Hi-Z
D Ax6 D Ax7
DQ
* BA0=" L"
Write Co mman d Bank 0
(c) NANYA TECHNOLOGY CORP. All rights reserved. Clock S usp end 1 Cycle Clock Suspen d 2 Cycles
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3=Idle
Activate Comma nd Ba nk 0
Clock S usp end 3 Cycles
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 2)
T3 T 11 T 13 T14 T 15 T 16 T 18 T19 T 20 T 22 T4 T5 T6 T7 T8 T9 T10 T12 T17 T 21
T0
T1
T2
CK tCES t SB
VALID
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
tCES
tCK2 tCES
CKE
256Mb Synchronous DRAM
CS
RAS
Power Down Mode and Clock Suspend
CAS
WE
51
CAx
* BA1
A10
RAx
A0 -A9, A11,A12
RAx
DQM tHZ
A x0 Ax1 Ax2 Ax3
DQ
Hi-Z
tSB
* BA0=" L"
NOP R ead Com mand Bank 0
Activate C omm and Bank 0 ACT IVE STAN DBY
Cloc k Suspension Start
Cloc k Suspension End
Prec harge C omm and Bank 0
PR ECH ARGE STAND BY NOP Any Com mand
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3=Idle
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Auto Refresh (CBR)
\
(CAS latency = 2)
T14
T15
T16
T17
T18
T19
T20
T21
T22
T11
T12
tRC
T13
T7
T8
T4
T5
tRC
T6
tCK2
T1
tRP
A0-A9, A11,A12
CKE
RAS
CAS
WE
REV 1.0
May, 2001
52
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DQM
CK
A10
DQ
CS
BS
Hi-Z
Precharge Command All Banks
T0
Au to Refresh Command
T2
T3
Auto Refresh Command
T9
T10
\
May, 2001
REV 1.0
(Note: The CK signal must be reestablished prior to CKE returning high.)
T3 T4 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 T m+10 Tm+11 T m+12 Tm +13 Tm +14 Tm+15
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK tCES
t CES
CKE
256Mb Synchronous DRAM
Self Refresh (Entry and Exit)
CS
RAS
CAS
WE
53
tS RE X
Self Refresh Exit Power Down Exit
BS
A10
A0-A9, A11,A12
DQM
DQ
Hi-Z
t SB
tRC
Any Command
All Banks must be idle
Self Refresh Entry
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Power Down Entry
\
May, 2001
REV 1.0
(Burst length = 8, CAS latency = 3; tRCD , tRP = 3)
T3 T11 T 12 T 13 T14 T 15 T16 T17 T18 T 19 T20 T 21 T22 T4 T5 T6 T7 T8 T9 T10
R Ax R By R Ax C Ax R By C By
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK3
CKE
H igh
256Mb Synchronous DRAM
CS
RAS
CAS
WE
Random Row Read (Interleaving Banks) with Precharge
54
tAC3
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 A x0 Ax1
* BA1
A10
RBx
A0-A9, A11,A12
RBx
CBx
DQM
tRCD
Hi-Z
Ax4 Ax5 Ax6 Ax7 By0
DQ
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Activate Com mand Bank 0 R ead C ommand Bank 0
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
*
BA0=" L" Bank2,3=Idle
Ac tiv ate Comm and Bank 1
Read Comm and Bank 1
Precharge Com mand Bank 1
Activate C om mand Bank 1
Read C ommand Bank 1
Prec harge C ommand Bank 0
\
May, 2001
REV 1.0
(Burst length = 8, AS latency = 3; tRCD , tRP = 3) C
T3 T10 T11 T 12 T 13 T14 T15 T16 T17 T18 T 19 T20 T 21 T22 T4 T5 T6 T7 T8 T9 Start Auto Prec harge Bank 1 Start Auto Precharge Bank 0
RA x R Ax
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK3
CKE
H igh
256Mb Synchronous DRAM
CS
RAS
CAS
WE
Random Row Read (Interleaving Banks) with Auto-Precharge
55
RB y
RA x R Ax
* BA1
A10
RB x
A0-A9, A11,A12
CAx
RB x
CB x
RB y
CB y
DQM
tRCD
tAC3
H i-Z
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 A x0 Ax1 Ax4 Ax5 Ax6 Ax7 By0
DQ
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Activate Com mand Bank 0 R ead with Auto Prec harge C ommand Bank 0
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
* BA0=" L" B ank2,3 =Idle
Ac tivate Comm and Bank 1
Read w ith Auto Precharge Comm and Bank 1
Activ ate Com mand Bank 1
Read w ith Auto Precharge Com mand Bank 1
\
May, 2001
REV 1.0
(Burst length = 8, CAS latency = 3; tRCD , tRP = 3)
T3 T 11 T12 T 13 T 14 T15 T16 T17 T18 T 19 T20 T 21 T22 T4 T5 T6 T7 T8 T9 T10
R Bx RAy
T0
T1
T2
CK
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
tCK3
CKE
High
256Mb Synchronous DRAM
CS
RAS
CAS
WE
Random Row Write (Interleaving Banks) with Auto-Precharge
56
R Bx CBx RAy CAy
* BA1
A10
R Ax
A0-A9, A11,A12
R Ax
C AX
DQM
tRCD
tDAL
tDAL
Hi-Z
DAx1 D Ax4 DAx5 D Ax6 DAx7 D Bx0 DBx1 D Bx2 D Bx3 D Bx4 DBx5 DBx6 D Bx7 D Ay0 D Ay1 DAy2
DQ
D Ax0
Activ ate Com mand Bank 0 Activate Com mand Bank 1
Write with Auto Precharge Com mand Bank 0
W rite with Auto Precharge C omm and Bank 1
Activate C ommand Bank 0
W rite with Auto Precharge C ommand Bank 0
* BA 0=" L" Bank2,3=Idle
Number of clocks depen ds on clock cycle time and speed sort. See the Clock Freque ncy and Latency table. Bank ma y be reactivated at the comp leti on of tD AL.
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
\
May, 2001
REV 1.0
(Burst length = 8,CAS latency = 3; tRCD , tRP = 3)
T4 T11 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T5 T6 T7 T8 T9 T10 T12
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
T0
T1
T2
T3
CK
tCK3
256Mb Synchronous DRAM
CKE
High
CS
RAS
CAS
Random Row Write (Interleaving Banks) with Precharge
57
R Bx RAy R Bx C Bx RAy
WE
* BA1
A10
RAx
A0-A9, A11,A12
RAx
C AX
CAy
tRCD
tRP
tDPL
DQM
Hi -Z
DA x4 DAx5 DAx6 DAx7 D Bx0 DB x1 DB x2 DB x3 D Bx4 D Bx5 D Bx6 D Bx7 DAy0 D Ay1 DAy2
DQ
D Ax0
D Ax1
(c) NANYA TECHNOLOGY CORP. All rights reserved. Activate Comma nd Bank 1 Write Command Bank 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Activate Command * BA0=" L" Bank 0 Bank2,3=Idle
Write Command Bank 0
Precharge Command Bank 0
Activate Command Bank 0
Write Command Bank 0 P recharge Command Bank 1
\
May, 2001
REV 1.0
(Burst length = 8, CAS latency = 3; tRCD , tRP = 3)
T4 T11 T 13 T 14 T15 T16 T18 T19 T 20 T22 T5 T6 T7 T8 T9 T10 T12 T17 T21
T0
T1
T2
T3
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
Read / Write Cycle
tCK3
CKE
256Mb Synchronous DRAM
CS
RAS
CAS
WE
58
CAx C Ay Ax0 Ax1 Ax2 Ax3 D Ay0 D Ay1 DAy3 DA y4
* BA1
A10
RA x
A0-A9, A11,A12
RA x
DQM
DQ
H i-Z
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
* BA0 =" L" Bank2,3=Idle
Ac tiv ate Comm and Bank0
Read Com mand Bank 0
The Read D ata Write T he Write D ata is Mask ed w ith a Comm and is M asked with a T wo C lock Bank 0 Zero C lock Latenc y Latency
Precharge Com mand Bank 0
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 3; tRCD , tRP = 3)
T4 T11 T13 T1 4 T15 T16 T18 T19 T20 T22 T5 T6 T7 T8 T9 T10 T12 T17 T21 Start Auto Precharge Bank 0
T0
T1
T2
T3
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK3
CKE
256Mb Synchronous DRAM
CS
Interleaved Column Read Cycle
RAS
CAS
WE
59
R Bx R Bx CB x C By CB z C Ay
* BA1
A10
R Ax
A0-A9, A11,A12 t AC3
R Ax
C Ax
DQM
t RCD
Hi-Z
Ax0 Ax1 A x2 Ax3 Bx0 B x1 By0 By1 Bz0 Bz1 A y0 Ay1 Ay2 Ay3
DQ
*
Activate Command Bank 1
Activate
(c) NANYA TECHNOLOGY CORP. All rights reserved. Read Command Bank 1 Read Command Ban k 1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
BA0=" L" Command Bank 0 Bank2,3=Idle
Read Comman d Bank 0
Read with Read Prechar ge Command A uto Prech arge Comma nd Command Bank 1 Bank 1 B ank 0
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 3; tRCD , tRP = 3)
T3 T10 T13 T14 T15 T16 T18 T19 T20 T22 T11 T12 T17 T2 1 T4 T5 T6 T7 T8 T9
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK3
CKE High
256Mb Synchronous DRAM
CS
Auto Precharge after Read Burst
RAS
CAS
WE
60
RBx R By R Bx C Bx C Ay RB y
* BA1
A10
R Ax
A0-A9, A11,A12
R Ax
CA x
CBy
DQM
Start Auto Pre charge Ban k 1
Start Auto Precharge Bank 0
Star t Auto Precharge Bank 1
Hi-Z
A x0 Ax1 Ax2 Ax3 B x0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1
DQ
(c) NANYA TECHNOLOGY CORP. All rights reserved. A ctivate Comma nd Bank 1 Read with Auto Precharge Command Bank 1 Read with Auto Precharge Command Bank 0
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Activate Command * BA 0=" L" Bank 0 Bank2,3=Idle
Activa te Co mmand Bank 1
Read Command Bank 0
Read with Auto Precharg e Command Ban k 1
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 2)
T3 T10 T 11 T 12 T13 T14 T 15 T 16 T17 T 18 T19 T20 T21 T22 T4 T5 T6 T7 T8 T9
R Bx RBy RAz R Bx CBx RBy CAy CBy RAz CAz
T0
T1
T2
CK
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
tCK2
CKE
High
256Mb Synchronous DRAM
CS
Auto Precharge after Write Burst
RAS
CAS
WE
61
tDAL tDAL
DAx2 DAx3 DBx0 DBx1 DBx2 D Bx3 DAy0 DAy1 DAy2 D Ay3 DBy0 DBy1 D By2 D By3
* BA1
A10
R Ax
A0-A9, A11,A12
R Ax
CAx
DQM
tD AL
H i-Z
D Az0 DAz1 DAz2 DAz3
DQ
D Ax0
DAx1
Activ ate C ommand Bank 0
Write Command Bank 0
Write with Activate C ommand Auto Precharge Comm and Bank 1 Bank 1
Write with Auto Precharge Comm and Bank 0
Write with Activate Command Auto Precharge Comm and Bank 1 Bank 1
Write with Activate Command Auto Precharge Comm and Bank 0 Bank 0 Num ber of cloc ks depends on clock c ycle and speed sort. See the Clock F requenc y and Latency table. Bank may be reac tiv ated at the com pletion of tD AL.
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
*
BA0=" L" Bank2,3=Idle
\
May, 2001
REV 1.0
(Burst length = 4, CAS latency = 2)
T3 T 11 T13 T 14 T15 T 16 T 17 T 18 T19 T 20 T21 T22 T4 T5 T6 T7 T8 T9 T 10 T12
T0
T1
T2
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK2
CKE
High
256Mb Synchronous DRAM
CS
RAS
CAS
Burst Read and Single Write Operation
WE
* BA1
62
CAw CAx CAy Av0 Av1 Av2 Av3 DAw 0 Ay0 Av0 Av1 Av2 Av3 DAw0 DAx0 Ay0
A10
R Av
A0-A9, A11, A12
R Av
CAv
CAz
LDQM
UDQM
H i-Z
Ay1 Ay3 DAz0
DQ 0 - DQ 7
H i-Z
DQ 8 - DQ 15
A y2
Ay3
DAz0
* BA0=" L"
(c) NANYA TECHNOLOGY CORP. All rights reserved.
Single Write C omm and Bank 0
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Bank2,3=Idle
Activate C ommand Bank 0
R ead C ommand Bank 0
Single Write C ommand Bank 0
Low er Byte R ead is m ask ed C ommand Upper By te Bank 0 is mas ked
Single Write Comm and Bank 0
Low er Byte is mask ed
\
May, 2001
REV 1.0
(at 100MHz Burst Length = 4, CAS Latency = 3, tRCD , tRP = 3)
T4 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T5 T6 T7 T8 T9 T10
T0
T1
T2
T3
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
CK
tCK3
CKE
256Mb Synchronous DRAM
CS
RAS
CAS
CS Function (Only CS signal needs to be asserted at minimum rate)
63
C Ax C Ay Ax0 Ax1 Ax2 Ax3 D Ay0 D Ay1 DA y2 D Ay3
WE
BA0,BA1
A10, A12
RA x
A0-A9, A11
RA x
DQM Low tDPL
tRCD
DQ
Hi-Z
(c) NANYA TECHNOLOGY CORP. All rights reserved. Read Command Ba nk A
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Activate Command Bank A
Write Command Bank A
Prechar ge Comma nd Bank A
NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L)
256Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package)
22.22
0.13
Detail A
10.1 6 0 .13 Lead #1
11.76 Seating Plane 0.10
0.80 Basic
0.35
+ 0.10 - 0.05
0.71REF
0.20
Detail A
1.20 Ma x 0.25 Basic Gage Plane
0.5 0.05 Min
0.1
REV 1.0
May, 2001
64
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(R)
(c) Nanya Technology Corporation.
All rights reserved. Printed in Taiwan, R.O.C. May 2001
The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both. NANYA NANYA logo
Other company, product and service names may be trademarks or services maeks of others.
NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com

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