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E2U0058-18-85
Semiconductor MSM7719-01
Semiconductor Echo Canceler with ADPCM Transcoder
This version: Aug. 1998 MSM7719-01
GENERAL DESCRIPTION
The MSM7719, developed for PHS (Personal Handyphone System) applications, is an LSI device and contains a line echo canceler, an acoustic echo canceler (for handsfree conversation), and a single channel full-duplex ADPCM transcoder. This device includes DTMF tone and several types of tone generation, transmit/receive data mute and gain control, and VOX function and is best suited for PHS applications.
FEATURES
* Single 5 V power supply VDD : 4.5 V to 5.5 V * ADPCM : ITU-T Recommendations G.726 * PCM interface coding format : -law * Built-in 2-channel (line and acoustic) echo canceler Line echo canceler Acoustic echo canceler (for handsfree conversation) Echo attenuation : 30 dB (typ.) Cancelable echo delay time : 27 ms (max.) for line echo canceler +27 ms (max.) for acoustic echo canceler Line echo canceler mode only : 54 ms (max.) * Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps * Low supply current Operating mode : Typically 50 mA (VDD = 5.0 V) Power-down mode : Typically 0.2 mA (VDD = 5.0 V) * Master clock frequency : 9.6 to 10.0 MHz/19.2 to 20.0 MHz * Transmit/receive mute, transmit/receive programmable gain control * Built-in DTMF tone generator and various tones generator * Control through parallel microcontroller interface Pin control available for line and acoustic echo cancelers * Built-in VOX control Transmit side : Voice/silence detect Receive side : Background noise generation at the absence of voice signal * Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7719-01TS-K)
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Semiconductor
MSM7719-01
BLOCK DIAGRAM
Tone Generator (DTMF etc). ATTtgrx ATTtgtx
SinL
ATTsL
ATTgL Center Clip SoutL ATTrA GainA
RoutA
+
ATTIL
+
+
RinA
Power Calc. Howling Detector
Double Talk Detector
Line Adaptive FIR Filter (LAFF)
Power Calc. Howling Detector
Double Talk Detector
Acoustic Adaptive FIR Filter (AAFF)
RinL
SoutA
Center Clip
ATTIA
+
RoutL GainL ATTrL
+
ATTsA
-
+
SinA
ATTgA
Line Echo Canceler
Acoustic Echo Canceler
Mute
DETSL DETT DETP
Note Gen. Power Detect
MLV0-2 MUTE VOXI VOXO
LTHR LDCL LCCL LHD LCLP LHLD LATT LGC LATTG2-0 LATTL2-0 ECMODE ATHR ADCL ACCL AHD ACLP AHLD AATT AGC AATTG2-0 AATTL2-0
Voice Detect
VREF
SG BCLKA SYNCA
Line Echo Canceler Controller ADPCM TRANSCODER
ADPCM CODER
Timing Gen.
P/S & S/P
IS
ADPCM DECODER
IR CONTA IOSL0-1 VDDD1-3
Acoustic Echo Canceler Controller N/L L/N N/L L/N N/L L/N I/O Controller
VDDA DG1-3 AG
MCU I/F
P/S&S/P
Timing Gen.
Clock Gen.
Test I/F
PCMADI
PCMADO
PCMLNI
PCMLNO
PCMACI
PCMACO
PDN/RST
MCUSL
TSTI1-6
MTYPE
PCMSL
SYNCP
MCKSL
BCLKP
PDWN
D7-0
DTHR
A4-0
WR
INT
RD
MCK
CS
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Semiconductor
MSM7719-01
PIN CONFIGURATION (TOP VIEW)
89 PDN/RST 79 ECMODE
91 SYNCP
90 SYNCA
80 DETSL
87 PDWN
78 IOSL1
77 IOSL0
86 TSTI1
84 TSTI2
88 VDDD3
83 DETP
81 DETT
82 DG3
85 INT
NC WR RD A0 A1 A2 VDDD1 LDCL LCCL
1 2 3 4 5 6 7 8 9
100 NC
76 NC 75 A4 74 CS 73 A3 72 VOX0 71 MCUSL 70 PCMSL 69 IS 68 PCMLN0 67 PCMAD0 66 PCMAC0 65 VDDD2 64 MUTE 63 VOXI 62 TSTI6 61 TSTI5 60 BCLKP 59 BCLKA 58 MTYPE 57 DTHR 56 MLV0 55 MLV1 54 MLV2 53 AG 52 NC 51 NC MCK 50
99 D7
98 D6
97 D5
96 D4
95 D3
94 D2 LATTG0 32
93 D1 AATTL2 33
LHD 10 LCLP 11 DG1 12 LHLD 13 LATT 14 LTHR 15 LGC 16 AGC 17 ATHR 18 AATT 19 AHLD 20 ACLP 21 AHD 22 ACCL 23 ADCL 24 NC 25 28 29 LATTG2 30 LATTG1 31 AATTL1 34 AATTL0 35 DG2 36 AATTG2 37 AATTG1 38 AATTG0 39 PCMACI 40 PCMADI 41 IR 42 PCMLNI 43 CONTA 44 VDDA 45 SG 46 TSTI4 47 TSTI3 48 LATTL2 27 MCKSL 49 26
NC
LATTL1
LATTL0
100-Pin Plastic TQFP
92 D0
NC: No-connect pin
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Semiconductor
MSM7719-01
PIN FUNCTIONAL DESCRIPTION
SG Outputs of the analog signal ground voltage. The output voltage is approximately 2.4 V. Connect bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. During power-down, the output changes to 0 V. AG Analog ground. DG1, 2, 3 Digital ground. VDDA +5 V power supply for analog circuits. VDDD1, 2, 3 +5 V power supply for digital circuits. PDN/RST Power-down reset control input. A logic "0" makes the LSI device enter a power-down state. At the same time, all control register data are reset to the initial state. Set this pin to a logic "1" during normal operating mode. Since this pin is ORed with CR0-B5 (bit 5 (B5) of control register CR0), set CR0-B5 to logic "0" when using this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "1". PDWN Power-down control input. The device changes to the power-down state, and each bit of control register and internal variables of control register are not reset when set to a logic "0". During normal operation, set this pin to logic "1". Since this pin is ORed with CR0-B6 (bit 6 (B6) of control register CR0), set CR0-B6 to logic "0" when using this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "1". MCK Master clock input. The frequency must be 9.6 to 10.0 MHz/19.2 to 20.0 MHz. The master clock signal is allowed to be asynchronous with SYNCP, SYNCA, BCLKP, and BCLKA.
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Semiconductor MCKSL
MSM7719-01
Master clock selection input. Set MCKSL to logic "0" when the master clock frequency is 9.6 to 10.0 MHz, and to logic "1" when it is 19.2 to 20.0 MHz. PCMACO PCM data output of the echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic "1", this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the echo canceler signal output mode for this pin changes depending on the setting of IOSL0-1. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5. PCMACI PCM data input of the echo canceler. PCM is shifted in at the falling edge of BCLKP and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic "1", this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Note that the echo canceler signal input mode for this pin changes depending on the setting of IOSL0-1. Refer to Figs. 1-5. PCMADO PCM data output. PCM is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic "1", this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the signal ouput mode for this pin changes and the I/O control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5. PCMADI PCM data input. PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic "1", this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Note that the signal input mode for this pin changes and the I/O control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. Refer to Figs. 1-5.
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Semiconductor IOSL0-1
MSM7719-01
These pins specify PCM signal I/O mode for the PCMACO, PCMACI, PCMADO, and PCMADI pins. Since The IOSL0 and IOSL1 pins are ORed with the control register bits CR3-B6 and B5, set these bits to logic "0" before using these pins. When this pin control is not used (i.e., in the case of control with the control register), set these pins to logic "0". Refer to Figs. 1-5. IS Transmit ADPCM data output. This data is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA. This pin is in a high impedance state except during 4-bit ADPCM output. When CONTA is set to logic "1", this pin becomes an 8-bit output and the data that passed through the ADPCM transcoder is output. In this case, this pin is in a high impedance state except during 8-bit output. (This pin is also in a high imedance state during power-down or initial mode.) Refer to Figs. 1-5. IR Receive ADPCM data input. ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input data orderly from MSB. When CONTA is set to logic "1", this pin becomes an 8-bit input and the data is passed through the ADPCM transcoder and processed. This pin is provided with a 500-kW pull-up resistor. PCMLNO PCM receive data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic "1", this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5. PCMLNI PCM transmit data input of the line echo canceler. PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic "1", this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Refer to Figs. 1-5.
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Semiconductor BCLKA Shift clock input for the ADPCM data (IS, IR). The frequency is from 64 kHz to 2048 kHz. SYNCA
MSM7719-01
8 kHz synchronous signal input for ADPCM data. Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial ADPCM data stream. BCLKP Shift clock input for the PCM data (PCMLNO/PCMLNI, PCMACO/PCMACI, PCMADO/ PCMADI). The frequency is set in the range of 64 kHz to 2048 kHz. SYNCP 8 kHz synchronous signal input for PCM data. This signal must be synchronized with the BCLKP signal. MCUSL, MTYPE If the microcontroller interface is not to be used, set the MCUSL input pin to logic "1". This setting skips the intitial mode as the operating mode. For the MTYPE pin, which is the microcontroller interface selection pin, logic "0" sets the read/write independent control mode and logic "1" sets read/write shared control mode. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". CS, RD, WR A 19-byte control register is provided in this LSI device. Data is read and written by using these pins from the external microcontroller. See the microcontroller write and read timing diagrams in the Electrical Characteristics. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "1". A4-A0, D7-D0 A4-A0 are address input pins of the control register, and D7-D0 are data I/O pins. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". INT Reserved. PCMSL Reserved. 7/40
Semiconductor CONTA
MSM7719-01
ADPCM transcoder setting pin. When this pin is set to logic "1", the transcoder-through mode is set. In this mode, the IS and IR pins become 8-bit PCM serial input and output pins. Since this pin is ORed with the control register bit CR1-B7, set CR1-B7 to logic "0" to use this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "0". Refer to Figs. 1-5. DTHR Through mode setting pin. When this pin is set to logic "1", the entire circuit is put in the through mode. In this mode, the PCM input and output pins become 4-bit serial input and output pins and all functions of the echo canceler, ADPCM transcoder, and MUTEVOX are disabled. Use this pin when making 32-kbps data communication. Since this pin is ORed with the control register bit CR1-B5, set CR1-B5 to logic "0" to use this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "0". Note that 64-kbps data communication is not supported in this device. Refer to Figs. 1-5.
Echo Canceler (54ms) Line Echo Canceler (27ms) Acoustic Echo Canceler (27ms)
(a)
ADPCM
(b)
(a)
(b)
Transcoder
(c)
(c)
Output Control
Input Control
Input Control
Output Control
Output Control
Input Control
Input Control
Output Control
(c) SYNCP BCLKP CR2-B3, B2
(c) PCMACI PCMACO PCMADO PCMADI
(b) IR
(b) IS SYNCA BCLKA
PCMLNO PCMLNI
Figure 1 Signal I/O Control 1 IOSL1="0", IOSL0="0" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5
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Semiconductor
MSM7719-01
Echo Canceler (54ms) Line Echo Canceler (27ms) Acoustic Echo Canceler (27ms)
(a)
ADPCM
(b)
(a)
(b)
Transcoder
(c)
(c)
Output Control
Input Control
Input Control
Output Control
Output Control
Input Control
Input Control
Output Control
(c) SYNCP BCLKP CR2-B3, B2
(c) SYNCP BCLKP
(c)
(c) PCMADO PCMADI SYNCP BCLKP CR2-B4
(b) IR
(b) IS SYNCA BCLKA
PCMLNO PCMLNI
PCMACI PCMACO
CR2-B1, B0
Figure 2 Signal I/O Control 2 IOSL1="0", IOSL0="1" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5
(b)
Line Echo Canceler (27ms) Acoustic Echo Canceler (27ms)
ADPCM Transcoder
(b)
Output Control
Input Control
Input Control
Output Control
Output Control
Input Control
Input Control
Output Control
(b)
SYNCP BCLKP CR2-B3, B2 PCMLNO PCMLNI SYNCP PCMACI BCLKP CR2-B1, B0 PCMACO
(b) IR IS SYNCA BCLKA
PCMADO
PCMADI SYNCP
BCLKP CR2-B4
Figure 3 Signal I/O Control 3 IOSL1="1", IOSL0="0" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5
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Semiconductor
MSM7719-01
(b)
Line Echo Canceler (27ms) Acoustic Echo (b) Canceler (27ms)
ADPCM Transcoder
(c)
(c)
(c)
(c)
Output Control
Input Control
Input Control
Output Control
Output Control
Input Control
Input Control
Output Control
(c)
SYNCP BCLKP CR2-B3, B2 PCMLNO
(c)
PCMLNI SYNCP BCLKP
(c)
PCMACI
(c)
PCMACO
(c)
PCMADO
(c)
PCMADI SYNCA BCLKA CR2-B4
(b)
IR
(b)
IS SYNCA BCLKA
CR2-B1, B0
Figure 4 Signal I/O Control 4 IOSL1="1", IOSL0="1" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5
SYNCP/SYNCA BCLKP/BCLKA PCM multiplexing PCMADI/O data (DTHR="0") PCMADI/O data (DTHR="1") PCMLNI/O data PCMACI/O data (DTHR="0") PCMLNI/O data PCMACI/O data (DTHR="1") IR/IS data (CONTA="1") IR/IS data (CONTA="0") time slot 1 time slot 2 time slot 3 time slot 4
1234567812345678 MSB 1234 MSB 1234
12345678123456781234567812345678 MSB 1234 MSB 12345678 MSB 1234 MSB 1234 1234
Note: The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to time slot 1 or 2. The PCM signals (PCMLNI, PCMLNO, PCMACI, and PCMACO) of the echo canceler can be assigned to one of the time slots 1 to 4. The ADPCM signals (IR and IS) of the ADPCM transcoder are always assigned to time slot 1. Figure 5 PCM Multiplexing/ADPCM Timing 10/40
Semiconductor ECMODE
MSM7719-01
This pin specifies the operating mode of the echo canceler. When set to logic "0", this device operates as a line echo canceler (with cancelable echo delay time of 27 ms max.) + an acoustic echo canceler (with cancelabel echo delay time of 27 ms max.); when set to logic "1", it operates as a line echo canceler (with cancelable echo delay time of 54 ms max.). When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". LTHR, ATHR (L: Line A: Acoustic) These pins control the through mode of the echo canceler. In this mode, SinL/A data and RinL/A data is output directly to SoutL/A and RoutL/A respectively, while retaining their echo canceler coefficients. 0: Normal mode (Echo cancellation) 1: Through mode When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "1". LDCL, ADCL These pins control clearing the coefficient 1 of the adaptive FIR filter used by the echo canceler. If the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to "0") and the coefficient 2 (by setting LCCL/ACCL to "0") of the adaptive FIR filter whenever possible. 0: Resets the coefficient 1: Normal operation When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "1". LCCL, ACCL These pins control clearing the coefficient 2 of the adaptive FIR filter used by the echo canceler. If the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to "0") and the coefficient 2 (by setting LCCL/ACCL to "0") of the adaptive FIR filter whenever possible. 0: Resets the coefficient 1: Normal operation When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "1". LHD, AHD Howling detection ON/OFF control pins. 0: OFF, 1: ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". LCLP, ACLP These pins turn ON or OFF the Center Clipping funciton that forcibly sets the SoutL output of the line echo canceler to minimum positive value when it is -57 dBm0 or less. 0: Center Clipping OFF 1: Center Clipping ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". 11/40
Semiconductor LHLD, AHLD
MSM7719-01
These pins control updating the coefficient of the adaptive FIR filter (AFF) for the echo canceler. 0: Normal mode (updates the coefficient) 1: Coefficient Fixed mode When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". LATT, AATT These pins turn ON or OFF the ATT function that prevents howling from occurring by means of attenuators ATTsL/A and ATTrL/A provided for the RinL/A input and the SoutL/A output of the echo canceler. When a signal is input to RinL/A only, the attenuator ATTsL/A of the SoutL/A output is activated. When a signal is input to SinL/A only or to both SinL/A and RinL/A, the attenuator ATTrL/A of the RinL/A input is activated. The ATT values are both about 6 dB. 0: ATT function ON 1: ATT function OFF When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". LGC, AGC These pins turn ON or OFF the gain control function that controls the RinL/A input level and prevents howling from occurring by the gain controller (GainL/A) provided for the RinL/A input of the echo canceler. The RinL/A input level is adjusted in the attenuation range of 0 to -8.5 dB. This adjusting starts at the RinL/A input level of -24 dBm0. 0: gain control OFF 1: gain control ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". MUTE Receive side voice path mute level enable pin. To set a mute level, set this pin to logic "1". When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "0". MLV0-2 Receive side voice path mute level setting pins. For the control method, refer to the control register (CR1) description. Since this signal is ORed with CR1-B2, B1, and B0 internally, set the bits of the register to logic "0" before using these pins. DETSL Reserved pin. Set this pin to logic "0".
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Semiconductor DETT Reserved pin. Set this pin to logic "0". DETP Reserved pin. Set this pin to logic "0". LATTG2-0, AATTG2-0 Pad setting pins for the echo canceler's SoutL/A output gain.
Level 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB 12 dB 14 dB 0 0 0 0 1 1 1 1 ATTG2 0 0 1 1 0 0 1 1 ATTG1 0 1 0 1 0 1 0 1 ATTG0
MSM7719-01
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". LATTL2-0, AATTL2-0 Pad setting pins for the echo canceler's SinL/A input loss.
Level -0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB 0 0 0 0 1 1 1 1 ATTL2 0 0 1 1 0 0 1 1 ATTL1 0 1 0 1 0 1 0 1 ATTL0
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic "0". TSTI1-6 Test input pins. Tie to logic "0".
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Semiconductor VOXO
MSM7719-01
Signal outut for transmit side VOX function. This pin is effective when CR6-B7 is set to logic "1" (VOX ON). The VOX function recognizes the presence or absence of the transmit voice signal by detecting the level of the transmit signal to the line echo canceler. "1" and "0" levels set to this pin correspond to the presence and the absence of voice, respectively. This result appears also at the register bit CR7B7. The signal energy detect threshold is set by the control register bits CR6-B6, B5. The timing diagram of the VOX function is shown in Figure 3. The transmit signal to the line echo canceler refers to the signal input to the PCMLNI pin. Refer to Figure 6. VOXI Signal input for receive side (acoustic echo canceler Sin side) VOX function. The "1" level at VOXI indicates the presence of a voice signal, the decoder block processes normal receive signal, and the voice signal on the PCMACI pin goes through. The "0" level indicates the absence of a voice signal and the background noise generated in this device is output. The background noise amplitude is set by the control register CR6. Because this signal is ORed with the register bit CR6-B3, set CR6-B3 to logic "0" when using this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic "0". Refer to Figure 6.
Transmit Signal PCMLNI (shown as an analog signal) Voice Silence Voice
VOXO
TVXON Voice Detect
TVXOFF Silence Detect (Hangover time) (a) Transmit Side VOX Function Timing Diagram
VOXI
Voice
Silence
Voice
Receive Signal Acoustic Echo Canceler Sin (shown as an analog signal) Receive Signal Decoded Time Period Background Noise
(b) Receive Side VOX Function Timing Diagram
Figure 6 VOX Function 14/40
Semiconductor
MSM7719-01
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Digital Output Voltage Storage Temperature Symbol VDD VDIN VOUT TSTG Condition -- -- -- -- Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Master Clock Frequency Master Clock Duty Ratio Bit Clock Frequency Clock Duty Cycle (*2) Symbol VDD Ta VIH VIL tIr tIf fMCK DC fBCK DCK tXS Transmit Sync Pulse Setting Time tSX tXO tRS Receive Sync Pulse Setting Time tSR tRO Receive Sync Pulse Setting Time PCM, ADPCM Set-up Time PCM, ADPCM Hold Time tWS tDS tDH Condition -- -- All digital inputs All digital inputs All digital inputs Measurement point=0.8V&2.4V MCK (When MCKSL="1") MCK (When MCKSL="0") MCK BCLKP, BCLKA SYNCP, SYNCA BCLKP, BCLKA BCLKP to SYNCP, BCLKA to SYNCA SYNCP to BCLKP, SYNCA to BCLKA SYNCP to BCLKP, SYNCA to BCLKA BCLKP to SYNCP, BCLKA to SYNCA SYNCP to BCLKP, SYNCA to BCLKA SYNCP to BCLKP, SYNCA to BCLKA SYNCP, SYNCA -- -- (VDD = 4.5 V to 5.5 V, Ta = -25C to +70C) Max. Min. Typ. Unit +4.5 -25 2.4 0 -- -- -100 ppm 40 64 -- 40 100 100 -- 100 100 -- 1 BCLK 100 100 -- +25 -- -- -- -- 19.2-20.0 9.6-10.0 50 -- 8.0 50 -- -- -- -- -- -- -- -- -- +5.5 +70 VDD+0.3 0.8 5 5 V C V V ns ns
+100 ppm MHz 60 2048 -- 60 -- -- 100 -- -- 100 100 -- -- % kHz kHz % ns ns ns ns ns ns ms ns ns
Synchronous Pulse Frequency (*1) fSYNC
*1
*2
If SYNCP and SYNCA are generated from different clocks, be sure to keep the relative timing of the rising edges of SYNCP and SYNCA (that is, which rising edge is earlier) after releasing the reset. The recommended condition (values) for the clock duty cycle need not be observed if the clock duty cycle fulfills the digital interface timing. 15/40
Semiconductor
MSM7719-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Power Supply Current 1 Power Supply Current 2 Input Leakage current High Level Digital Output Voltage Low Level Digital Output Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IIL VOH VOL ILO CIN (VDD=5 V) Power down mode (VDD=5 V, only the master clock is input) VI= VDD IOH= -0.4 nA IOL=3.2 mA VI=VDD/0 V -- Condition Operating mode, no signal Min. -- -- -10 4.2 0 -- -- Typ. 50 0.2 -- -- 0.2 -- 5 Max. 80 1 +10 VDD 0.4 10 -- Unit mA mA mA V V mA pF
Analog Interface Characteristics
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter SG Output Voltage SG Output Impedance Symbol VSG RSG SG SG Condition Min. 2.35 -- Typ. 2.4 40 Max. 2.45 80 Unit V kW
Reset Timing
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Reset Signal Width Reset Start Time Reset Termination Time
Symbol
Condition -- -- --
Min. 1 -- --
Typ. -- -- --
Max. -- 1 200
Unit ms ms ms
tRSTW tRSTS tRSTE
Note: Values in the table are common to the PDN/RST pin and the control register bit CR0-B5. * Reset timing
tRSTW PDN/RST Internal Processing tRSTS Reset tRSTE Initial mode
16/40
Semiconductor Echo Canceler Coefficient Reset Timing
MSM7719-01
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter
Echo Canceler Reset Signal Width Echo Canceler Reset Operating Time
Symbol
Condition -- -- --
Min. 125 0 --
Typ. -- -- --
Max. -- 125 125
Unit ms ms ms
tECRSTW tECRST
Echo Canceler Reset Detection Time tECRSTD
Note: Values in the table are common to the PDN/RST pin and the control register bit CR0-B5. * Echo canceler coefficient reset timing
LDCL ADCL LCCL ACCL Detect (8 kHz sampling) Reset
Coefficient reset processing (tECRST)
tECRSTW
tECRSTD
tECRSTD
Echo canceler operating
Note : In the above timing, the LDCL, ADCL, LCCL, and ACCL register bits are active high, and the LDCL, ADCL, LCCL, and ACCL pins are active low.
Control Pin Timing
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Control Signal Width Control Signal Detection Time Operation Start Time
Symbol
tSETUPW tSETUPD tSETUPS
Condition -- -- --
Min. 125 0 0
Typ. -- -- --
Max. -- 125 125
Unit ms ms ms
Note: The control pins / register bits are as follows: DETSL, DETT, DETP, (A/L)THR, (A/L)DCL, (A/L)CCL, (A/L)HLD, (A/L)ATT, (A/L) GC, (A/L)ATTG2-0, (A/L)ATTL2-0, PCMSL, DTHR, IOSL0-1, CINTA, MUTE, MLV0-2 * Control pin timing
tSETUPW Control Pin Detect (8 kHz sampling) Internal Processing
tSETUPS tSETUPS
tSETUPD
tSETUPD
Internal Processing
Internal Processing
17/40
Semiconductor Digital Interface Characteristics
MSM7719-01
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Digital Output Delay Time PCM, ADPCM Interface Symbol tSDX, tSDR tXD1, tRD1 tXD2, tRD2 tXD3, tRD3 -- Condition Min. 0 0 0 0 Typ. -- -- -- -- Max.
100 100 100 100
Unit ns ns ns ns
* PCM/ADPCM output timing
BCLKP SYNCP High-Z PCMO tSDX 0 tXS tXO 1 tSX tXD1 2 tWS tXD2 MSB 3 4 5 6 7 8 9 10
tXD3 LSB
High-Z
BCLKA SYNCA IS
0 tXS tXO
1 tSX tXD1
2
3
4
5
6
7
8
9
10
tXD2 MSB LSB
High-Z
tXD3
High-Z
tSDX
* PCM/ADPCM input timing
BCLKA SYNCA IR BCLKP SYNCP PCMI 0 tRS 1 tSR tRO MSB 0 tRS 1 tSR tRO tDS
MSB
2 tWS tDS tDH
3
4
5
6
7
8
9
10
LSB 2 tWS tDH
LSB
3
4
5
6
7
8
9
10
18/40
Semiconductor AC Characteristics (Gain Settings)
Parameter Transmit/Receive Gain Setting Accuracy Symbol DG Condition For all gain set values
MSM7719-01
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Min. Typ. Max. Unit -1 0 +1 dB
AC Characteristics (VOX Function)
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Transmit VOX Detection Time Transmit VOX Detection Level Accuracy (Voice Detection Level) Symbol tVXON Condition SilenceAEvoice VoiceAEsilence CR6-B6,B5
VOXO pin:see Fig.6 Voice/silence differential:10 dB
Min. --
Typ. 5
Max. --
Unit ms ms dB
(Voice Signal ON/OFF Detect Time) tVXOFF DVX
140/300 160/320 180/340 -2.5 0 +2.5
For detection level set values by
AC Characteristics (DTMF and Other Tones)
Parameter Frequency Deviation Symbol DfT1 DfT2 VTL Tone Reference Output Level (*1) Relative Value of DTMF Tones VTH VRL VRH RDTMF Transmit side tone Receive side tone Condition DTMF Tones Other various tones
(VDD = 2.7 to 3.6 V, Ta = -25 to +70C) Min. Typ. Max. Unit -1.5 -1.5 -10 -8 -10 -8 1 -- -- -8 -6 -8 -6 2 +1.5 +1.5 % %
DTMF (Low group) DTMF (Low group)
-6 dBm0 -4 dBm0 -6 dBm0 -4 dBm0 3 dB
(Gain set value:0dB) DTMF (High group), Others (Gain set value:0dB) DTMF (High group), Others VTH/VTL, VRH/VRL
*1
Not including programmable gain set values
19/40
Semiconductor Microcontroller Interface (WR and RD Pins Controlled Independently)
MSM7719-01
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Address and Chip Select Setup Time (with respect to the falling edge of WR) Address and Chip Select Setup Time (with respect to the rising edge of WR) WR Pulse Width Data Input Setup Time Data Input Hold Time Address and Chip Select Setup Time (with respect to the falling edge of RD) Address and Chip Select Setup Time (with respect to the rising edge of RD) RD Pulse Width Data Output Setup Time Data Output Hold Time
Symbol
Condition
Min. 30 15 45 30 15 30 15 45 -- 0
Typ. -- -- -- -- -- -- -- -- -- --
Max. -- -- -- -- -- -- -- -- 40 --
Unit
tCWS tCWH tWW tDWS tDWH tCRS tCRH tRW tDOD tDOH MTYPE=0
ns
* Microcontroller write timing (WR and RD controlled independently)
A4-0 CS tCWS WR High-Z High-Z tWW tCWH
D7-0
tDWS
tDOH
* Microcontroller read timing (WR and RD controlled independently)
A4-0 CS tCRS RD High-Z High-Z tRW tCRH
D7-0
tDOD
tDOH
20/40
Semiconductor Microcontroller Interface (Shared Control of WR and RD Pins)
MSM7719-01
(VDD = 4.5 to 5.5 V, Ta = -25 to +70C) Parameter Address Setup Time (with respect to the falling edge of WR) Address Setup Time (with respect to the rising edge of WR) WR Pulse Width Address Setup Time (with respect to the falling edge of CS) Address Setup Time (with respect to the rising edge of CS) CS Pulse width Data Input Setup Time Data Input Hold Time Address Setup Time (with respect to the falling edge of CS) Address Setup Time (with respect to the rising edge of CS) Data Output Delay Time Data Output Hold Time
Symbol
Condition
Min. 30 15 45 30 15
Typ. -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- -- -- -- -- -- -- -- -- 40 --
Unit
tWRWS tWRWH tWRW tCSWS tCSWH tCSW tDWS tDWH tCSRS tCSRH tDOD tDOH MTYPE=1
45 30 15 30 15 -- 0
ns
* Microcontroller write timing (shared control of WR and RD)
A4-0 tCSWS CS tWRWS WR High-Z tWRW tCSW tWRWH tCSWH
D7-0
tDWS
tDWH
High-Z
* Microcontroller read timing (shared control of WR and RD)
A4-0 RD tCSRS CS tCSW tCSRH
D7-0
High-Z
tDOD
tDOH
High-Z
21/40
Semiconductor Echo return loss (E. R. L.) vs. echo attenuation Conditions: - Input level of white noise of -10 dBm, 3.4 kHz band at Rin - Echo delay time: 2 ms - ATT, GC, NLP: Off
40 35
MSM7719-01
E. R. L. vs. Echo Attenuation
Echo Attenuation [dB]
30 25 20 15 10 5 0 -40 -30 -20 E. R. L. [dBm] -10 0
Rin input vs. echo attenuation Conditions: - Input level of 3.4 kHz-band white noise at Rin - Echo delay time: 2 ms E. R. L.=-6 dBm - ATT, GC, NLP: Off
40 35 Echo Attenuation [dB] 30 25 20 15 10 5 0 -50 -40 -30 -20 Rin Input Level [dBm] -10 0
Rin Input Level vs. Echo Attenuation
22/40
Semiconductor
MSM7719-01
Echo delay time vs. echo attenuation Conditions: - Input level of white noise of -10 dBm, 3.4 kHz band at Rin E. R. L.= -6 dBm - ATT, GC, NLP: Off ECMODE=27 ms
40 35
Echo Delay Time vs. Echo Attenuation
Echo Attenuation [dB]
30 25 20 15 10 5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
Echo Delay Time [ms]
Conditions: - Input level of white noise of -10 dBm, 3.4 kHz band at Rin E. R. L.= -6 dBm - ATT, GC, NLP: Off ECMODE=54 ms
40 35
Echo Attenuation [dB]
Echo Delay Time vs. Echo Attenuation
30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Echo Delay Time [ms]
23/40
Semiconductor
MSM7719-01
FUNCTIONAL DESCRIPTION
Control Registers Table 1 Control Register Map
Address Reg Name A4 A3 A2 A1 A0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Contents B7 -- B6 PDWN B5 PDN/ RST DTHR -- IOSL0 B4 -- B3 B2 B1 B0 R/W
CONTA ADPCM RESET -- PCMSL -- IOSL1
OPE OPE OPE OPE MODE3 MODE2 MODE1 MODE0 R/W TX RX RX RX RX MUTE MUTE MLV2 MLV1 MLV0 R/W PCM AD PCM LN PCM LN PCM AC PCM AC SEL SEL1 SEL0 SEL1 SEL0 R/W -- DETSL
DETAUTO
DETT
DETP
R/W
TX TONE TX TONE TX TONE TX TONE RX TONE GAIN3 GAIN2 GAIN1 GAIN0 GAIN3 DTMF/OTHERS TX TONE RX TONE SEL SEND SEND TONE4 TONE3 ON OFF VOX VOX ON LVL0 TIME IN ON/OFF LVL1 DET VOX Silence Level Silence Level INT CPT OUT 1 0 LTHR ATHR -- LDCL ADCL -- LCCL ACCL -- LHD AHD
RX TONE RX TONE RX TONE GAIN2 GAIN1 GAIN0 R/W TONE2 TONE1 TONE0 R/W
RX. NOISE RX. NOISE RX. NOISE LEVEL SEL LVL1 LVL0 R/W DET DETL DETA R DTMF LATT (ATT)* AATT (ATT)* LGC R/W (GC)* AGC R/W (GC)*
LCLP LHLD (NLP)* (ADP)* ACLP AHLD (NLP)* (APD)*
DMWR D TONE3 D TONE2 D TONE1 D TONE0 R/W -- -- A9 A1 D9 D1 -- -- -- -- A8 A0 D8 D0 -- -- R/W R/W R/W R/W R/W R/W R/W R/W
LATTL2 LATTL1 LATTL0 LATTG2 LATTG1 LATTG0 AATTL2 AATTL1 AATTL0 AATTG2 AATTG1 AATTG0 A15 A7 D15 D7 -- -- A14 A6 D14 D6 -- -- A13 A5 D13 D5 -- -- A12 A4 D12 D4 -- -- A11 A3 D11 D3 -- -- A10 A2 D10 D2 -- --
R/W : Read/Write enable R : Read only register * : These are the symbols of control pins used in the MSM7602 (echo canceler LSI device).
24/40
Semiconductor (1)CR0 (Basic operating mode settings)
B7 CR0 Initial value * -- 0 B6 PDWN 0 B5 PDN/RST 0 B4 -- 0 B3 OPE MODE3 0 B2 OPE MODE2 0
MSM7719-01
B1 OPE MODE1 0
B0 OPE MODE0 0
*:
Indicates the value to be set when a resetting is made through the PDN/RST pin. (Also when reset by bit 5 (B5, PDN/RST), the other bits of CR0 are reset to initial values.)
B7 ... Not used B6 ... Power-down (entire system) 0: Power-on 1: Power-down ORed with the inverted external power-down signals Set the PDWN pin to "1" when this register is used. The control registers and their internal variables are retained. B5 ... Power-down reset (entire system)0: Power-on 1: Power-down reset ORed with the inverted external power-down reset signals Set the PDN/RST pin to "1" when this register is used. The control registers and their internal variables are reset. B4 ... Not used B3, 2, 1, 0 ... Selection of an operating mode (0, 0, 0, 0) : Initial mode This mode enables a change (see Fig. 5) in memory that contains internal default values such as tone generation frequencies. In this mode, the PCM output pin acts to output idle patterns and the PCM input pin acts to input idle patterns; the echo canceler and the ADPCM transcoder do not operate. When power-down reset occurs or when power-down is released, the device enters the initial mode about 200 ms after that. When the MCUSL pin is set to "1", this mode is skipped. This mode is released by setting any of the following modes: (0, 1, 0, 0) : Handsfree conversation mode The tone detector, the ADPCM encoder/decoder, the tone generator, the line echo canceler, and the acoustic echo canceler become operative and can be controlled by the contents of the control registers. (0, 1, 0, 1) : Line echo canceler expansion mode The tone detector, the ADPCM encoder/decoder, the tone generator, and the line echo canceler (54 ms) become operative and can be controlled according to the contents of the control registers. (Others): Not used This register is internally processed by a logical OR of the MCUSL pin and B2, and between the ECMODE pin and B0.
25/40
Semiconductor (2) CR1 (Setting of ADPCM operating mode and PCM I/O signals)
B7 CR1 Initial value CONTA 0 B6 ADPCM RESET 0 B5 DTHR 0 B4 TX MUTE 0 B3 RX MUTE 0 B2 RX MLV2 0
MSM7719-01
B1 RX MLV1 0
B0 RX MLV0 0
B7 ... Control of through mode for the ADPCM CODEC 0: Normal mode 1: Through mode This bit is valid when the CONTA pin is set to "0". B6 ... Transmitter/receiver ADPCM resetting (conforming to G.721) 1: Reset B5 ... Control of through mode for transmit/receive signal (4-bit) through the entire circuit 0: Normal mode 1: Through mode When set to "1", the device enters the through mode for 4-bit transmit/receive signal through the entire circuit, and the PCM input and output pins are configured to be 4-bit serial input and output. All the functions of the echo canceler, ADPCM transcoder, MUTE, and VOX become invalid. Use this bit when making 32-kbps data communication. Note that 64-kbps data communication is not supported in this device. B4 ... Muting of transmitter ADPCM data 1: Mute B3 ... Muting of receiver ADPCM data 1: Muting specified by bits B2, B1, and B0 is enabled. This bit is valid when the MUTE pin is set to "0". B2, B1, B0... Setting of a receiver voice path mute level (MLV2, MLV1, MLV0) = (0, 0, 0) : (0, 0, 1) : (0, 1, 0) : (0, 1, 1) : (1, 0, 0) : (1, 0, 1) : (1, 1, 0) : (1, 1, 1) : Through - 6 dB -12 dB -18 dB -24 dB -30 dB -36 dB MUTE
26/40
Semiconductor (3) CR2 (Setting of PCM I/O multiplex control)
B7 CR2 Initial value -- 0 B6 -- 0 B5 -- 0 B4 PCM AD SEL 0 B3 PCM LN SEL1 0 B2 PCM LN SEL0 0
MSM7719-01
B1 PCM AC SEL1 0
B0 PCM AC SEL0 0
B7, 6, 5... Not used B4 ... PCM I/O multiplex timing control (PCMADI and PCMADO pins) of the ADPCM transcoder. 0: Time Slot 1 1: Time Slot 2 B3, 2 ... PCM I/O multiplex timing control (PCMLNI, PCMLNO pins) of the line echo canceler (See Table 2.) B1, 0 ... PCM I/O multiplex timing control (PCMACI and PCMACO pins) of the acoustic echo canceler (See Table 2.)
Table 2 PCM Multiplex Timing Control Table
B3 (B1 0 0 1 1 B2 B0) 0 1 0 1 Corresponding time slot 1 2 3 4
Note : The outputs are all in high impedance state for all time slots from the time a resetting is made to the initial mode.
27/40
Semiconductor (4) CR3 (Setting of PCM signal I/O)
B7 CR3 Initial value PCMSL 0 B6 IOSL1 0 B5 IOSL0 0 B4 -- 0 B3 DETSL 0 B2 DETAUTO 0
MSM7719-01
B1 DETT 0
B0 DETP 0
B7 ... Reserved B6, 5 ... PCM signal I/O control (see Figs. 1 to 4) B4 ... Not used B3, 2, 1, 0... Reserved
28/40
Semiconductor (5) CR4 (Adjustment of tone generator gain)
B7 CR4 Initial value TX TONE GAIN3 0 B6 TX TONE GAIN2 0 B5 TX TONE GAIN1 0 B4 TX TONE GAIN0 0 B3 RX TONE GAIN3 0 B2 RX TONE GAIN2 0
MSM7719-01
B1 RX TONE GAIN1 0
B0 RX TONE GAIN0 0
B7, 6, 5, 4 ... Transmit side gain adjustment for the tone generator [ATTtgtx] (See Table 3.) B3, 2, 1, 0 ... Receive side gain adjustment for the tone generator [ATTtgrx] (See Table 4.) Table 3 Setting of Transmit Side Gain of Tone Generator
B7 0 0 0 0 0 0 0 0 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Tone generator gain -36 dB -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B7 1 1 1 1 1 1 1 1 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Tone generator gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB
Table 4 Setting of Receive Side Gain of Tone Generator
B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone generator gain -36 dB -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone generator gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB
Settings of Table 4 are made in relation to the following tone levels: DTMF tone (Low frequency group) : -2 dBm0 DTMF tone (High frequency group) and other tone : 0 dBm0 For example, when bits B3, B2, B1, and B0 are set to "1, 1, 1, 1" (-6 dB), the PCMLNO pin outputs a tone of the following levels: DTMF tone (Low frequency group) : -8 dBm0 DTMF tone (High frequency group) and other tone : -6 dBm0 The default value change command enables the gain adjustment by -1 dB step. Writing "390Ah" into the address 16Dh adds a gain of -1 dB to the values in the above table. The default value is "4000h".
29/40
Semiconductor (6) CR5 (Setting of tone generator operating mode and tone frequency)
B7 CR5 Initial value SEL 0 B6 SEND 0 B5 RX TONE SEND 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0
MSM7719-01
B1 TONE1 0
B0 TONE0 0
DTMF/OTHERS TX TONE
B7 ... Selection of DTMF signal and S stone 0: Others 1: DTMF signal B6 ... Transmission of transmit side tone 0: Not transmit 1: Transmit B5 ... Transmission of receive side tone 0: Not transmit 1: Transmit B4, 3, 2, 1, 0... Setting of a tone frequency (See Table 5.) Table 5 Setting of Tone Generator Frequencies (a) When B7 = "1" (DTMF tone)
B4 B3 B2 B1 B0 * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description 697 Hz + 1209 Hz (1) 697 Hz + 1336 Hz (2) 697 Hz + 1477 Hz (3) 697 Hz + 1633 Hz (A) 770 Hz + 1209 Hz (4) 770 Hz + 1336 Hz (5) 770 Hz + 1477 Hz (6) 770 Hz + 1633 Hz (B) B4 B3 B2 B1 B0 * * * * * * * * 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description 852 Hz + 1209 Hz (7) 852 Hz + 1336 Hz (8) 852 Hz + 1477 Hz (9) 852 Hz + 1633 Hz (C) 941 Hz + 1209 Hz (*) 941 Hz + 1336 Hz (0) 941 Hz + 1477 Hz (#) 941 Hz + 1633 Hz (D)
(b) When B7 = "0" (Others) The table below lists default frequencies. Eight tones from "10000" to "10111" are single tones. For procedures to change frequencies, see the next page.
B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 400 Hz Single tone 1000 Hz Single tone 2000 Hz Single tone 2667 Hz Single tone 1300 Hz Single tone 2080 Hz Single tone *Hz Single tone *Hz Single tone -- -- -- -- -- -- -- --
* User specified frequency (see Table 6) 30/40
Semiconductor
MSM7719-01
Frequencies of tones (other than DTMF signals) to be generated by the tone generator can be changed. Tone frequencies can be changed in the Initial mode. See Figure 8 for procedures to change tone frequencies. The related subaddresses are shown below. Note: Transmitted Tone Frequency = A 8.192 (A = frequency) ex. When frequency = 1000 Hz, 1000 8.192 = 9011.2 = 9011d (eliminate after the decimal point) = 2333h Table 6 Tone Generator Subaddresses Single tone
B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Subaddress 1 (Frequency 1) (See Note above) 178h 179h 17Ah 17Bh 17Ch 17Dh 17Eh 17Fh Transmit single tone
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Semiconductor (7)CR6 (VOX function control)
B7 CR6 Initial value VOX ON/OFF 0 B6 ON LVL1 0 B5 ON LVL0 0 B4 OFF TIME 0 B3 VOX IN 0 B2 RX. NOISE LEVEL SEL 0
MSM7719-01
B1 RX. NOISE LVL1 0
B0 RX. NOISE LVL0 0
B7 ... Turns ON or OFF the VOX function 0: OFF, 1: ON B6,5 ...Setting of transmit side voice or silence detection level (0, 0) : -20 dBm0 (0, 1) : -25 dBm0 (1, 0) : -30 dBm0 (1, 1) : -35 dBm0 Note: * The detection level is changeable by inserting the pad of -1dB to -5dB in addion to the alove values. * Write 16384 10(-A/20) at address "2DEh". Example: When -1dB pad is inserted, 16384 10(- (-1)/20) =18383.15=18383d (eliminate after the decimal point)=47CFh B4 ... Setting of hangover time (TVXOFF) (See Figure 6.) 0: 160 ms 1: 320 ms B3 ... VOX input signal (receiver side) 0: Transmits an internal background noise. 1: Transmits a voice reception signal. Set the VOXI pin to "0" to use this data. B2 ... Setting of a receiver side background noise level 0: Reserved B1, 0... Externally-set background noise level (0, 0) : No noise (0, 1) : -55 dBm0 (1, 0) : -45 dBm0 (1, 1) : -35 dBm0 (8) CR7 (Detection register : read-only)
B7 CR7 Initial value VOX OUT 0 B6 1 0 B5 0 0 B4 INT 0 B3 DET CPT 0 B2 DET DTMF 0 B1 DETL 0 B0 DETA 0
Silence level Silence level
B7... Detection of transmit side voice or noise 0: Silence 1: Voice B6, 5... Transmit side silence level (Indicator) (0, 0) : -10dB or less with respect to the detection level defined by CR6-B6, B5. (0, 1) : -5 to -10 dB with respect to the detection level defined by CR6-B6, B5. (1, 0) : -0 to -5 dB with respect to the detection level defined by CR6-B6, B5. (1, 1) : -0 dB or more with respect to the detection level defined by CR6-B6, B5. Note : The above outputs are valid only when the VOX function is enabled by bit 7 of CR6. B4, 3, 2, 1, 0 ... Reserved
32/40
Semiconductor (9) CR8 (Setting of line echo canceler operating mode)
B7 CR8 Initial value LTHR 1 B6 LDCL 0 B5 LCCL 0 B4 LHD 0 B3 LCLP (NLP)*1 0 B2 LHLD (ADP)*1 0
MSM7719-01
B1 LATT (ATT)*1 0
B0 LGC (GC)*1 0
*1 Name of a control pin used by the MSM7602 B7 ... Through mode control bit for the line echo canceler In this mode, RinL data and SinL data is output directly to RoutL and SoutL respectively. The coefficient is not cleared. 1: Through mode 0: Normal mode (echo cancellation) B6 ... Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (LAFF) used by the line echo canceler. 1: Resets the coefficient 0: Normal operation B5 ... Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (LAFF) used by the line echo canceler. 1: Resets the coefficient 0: Normal operation B4 ... Howling detector (HD) ON/OFF control 1: ON 0: OFF B3 ... Turns ON or OFF the Center Clipping function which forcibly sets the SoutL output of the line echo canceler to minimum positive value when it is -57 dBm0 or less. 1: Center Clipping ON 0: Center Clipping OFF B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (LAFF) for the line echo canceler. 1: Coefficient Fixed mode 0: Normal mode (updates the coefficient.) B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of attenuators ATTsL and ATTrL provided for the RinL input and the SoutL output of the line echo canceler. When a signal is input to RinL only, the attenuator ATTsL of the SoutL output is activated. When a signal is input to SinL only or to both SinL and RinL, the attenuator ATTrL of the RinL input is activated. Their ATT values are both about 6 dB. 1: ATT function OFF 0: ATT function ON B0 ... Turns ON or OFF the gain control function which controls the RinL input level and prevents howling from occurring by the gain controller (GainL) for the RinL input of the line echo canceler. The RinL/A input level is adjusted in the attenuation range of 0 to -8.5 dB. This adjusting starts at the RinL/A input level of -24 dBm0. 1: Gain control function ON 0: Gain control function OFF
33/40
Semiconductor
MSM7719-01
(10) CR9 (Setting of acoustic echo canceler operating mode)
B7 CR9 Initial value ATHR 1 B6 ADCL 0 B5 ACCL 0 B4 AHD 0 B3 ACLP (NLP)*1 0 B2 AHLD (ADP)*1 0 B1 AATT (ATT)*1 0 B0 AGC (GC)*1 0
*1 Name of a control pin used by the MSM7602 B7 ... Through mode control bit for acoustic echo canceler. In this mode, RinA data and SinA data is output directly to RoutL and SoutL respectively. The coefficient is not cleared. 1: Through mode 0: Normal mode (echo cancellation) B6 ... Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (AAFF) for the acoustic echo canceler. 1: Resets the coefficient 0: Normal operation B5 ... Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (AAFF) for the acoustic echo canceler. 1: Resets the coefficient 0: Normal operation B4 ... Howling detector (HD) ON/OFF control 1: ON 0: OFF B3 ... Turns ON or OFF the Center Clipping function which forcibly sets the Sout output of the acoustic echo canceler to a minimum positive value when it is -57 dBm0 or less. 1: Center Clipping ON 2: Center Clipping OFF B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (AAFF) for the acoustic echo canceler. 1: Coefficient fixed mode 0: Normal mode (updates the coefficient.) B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of attenuators ATTrA and ATTsA provided for the RinA input and the SoutA output of the acoustic echo canceler. When a signal is input to RinA only, the attenuator ATTsA of the SoutA output is activated. When a signal is input to SinA only or to both SinA and RinA, the attenuator ATTrA of the RinA input is activated. Their ATT values are both about 6 dB. 1: ATT function OFF 0: ATT function ON B0 ... Turns ON or OFF the gain control function which controls the RinA input level and prevents howling from occurring by the gain controller (GainA) for the RinA input of the acoustic echo canceler. The RinL/A input level is adjusted in the attenuation range of 0 to -8.5 dB. This adjusting starts at the RinL/A input level of -24 dBm0. 1: Gain control ON 0: Gain control OFF
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Semiconductor (11) CR10 (Tone detection frequency)
B7 CR10 Initial value -- 0 B6 -- 0 B5 -- 0 B4 DMWR 0 B3 D TONE3 0 B2 D TONE2 0
MSM7719-01
B1 D TONE1 0
B0 D TONE0 0
B7, 6, 5 ... Not used B4 ... Controls changing the default value in default store memory 1: Write Writes the 16-bit data that is set in CR15 (D15-D8) and CR16 (D7-D0) into the 16-bit addresses that are set in CR13 (A15-A8) and CR14 (A7-A0) B3, 2, 1, 0 ... Reserved
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Semiconductor
MSM7719-01
(12) CR11 (Transmit side pad control)
B7 CR11 Initial value LATTL2 0 B6 LATTL1 0 B5 LATTL0 0 B4 LATTG2 0 B3 LATTG1 0 B2 LATTG0 0 B1 -- 0 B0 -- 0
B7, 6, 5 ... Setting of pad for transmit loss (0, 0, 0) : 0 dB (0, 0, 1) : -2 dB (0, 1, 0) : -4 dB (0, 1, 1) : -6 dB (1, 0, 0) : -8 dB (1, 0, 1) : -10 dB (1, 1, 0) : -12 dB (1, 1, 1) : -14 dB B4, 3, 2 ... Setting of pad for transmit gain (0, 0, 0) : 0 dB (0, 0, 1) : 2 dB (0, 1, 0) : 4 dB (0, 1, 1) : 6 dB (1, 0, 0) : 8 dB (1, 0, 1) : 10 dB (1, 1, 0) : 12 dB (1, 1, 1) : 14 dB (13) CR12 (Receive side pad control)
B7 CR12 Initial value AATTL2 0 B6 AATTL1 0 B5 AATTL0 0 B4 AATTG2 0 B3 AATTG1 0 B2 AATTG0 0 B1 -- 0 B0 -- 0
B7, 6, 5 ... Setting of pad for receive loss (0, 0, 0) : 0 dB (0, 0, 1) : -2 dB (0, 1, 0) : -4 dB (0, 1, 1) : -6 dB (1, 0, 0) : -8 dB (1, 0, 1) : -10 dB (1, 1, 0) : -12 dB (1, 1, 1) : -14 dB B4, 3, 2 ... Setting of pad for receive gain (0, 0, 0) : 0 dB (0, 0, 1) : 2 dB (0, 1, 0) : 4 dB (0, 1, 1) : 6 dB (1, 0, 0) : 8 dB (1, 0, 1) : 10 dB (1, 1, 0) : 12 dB (1, 1, 1) : 14 dB
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Semiconductor (14) CR13, 14, 15, 16 (Default value store registers)
B7 CR13 Initial value A15 0 B6 A14 0 B5 A13 0 B4 A12 0 B3 A11 0 B2 A10 0
MSM7719-01
B1 A9 0
B0 A8 0
B7 CR14 Initial value A7 0
B6 A6 0
B5 A5 0
B4 A4 0
B3 A3 0
B2 A2 0
B1 A1 0
B0 A0 0
B7 CR15 Initial value D15 0
B6 D14 0
B5 D13 0
B4 D12 0
B3 D11 0
B2 D10 0
B1 D9 0
B0 D8 0
B7 CR16 Initial value D7 0
B6 D6 0
B5 D5 0
B4 D4 0
B3 D3 0
B2 D2 0
B1 D1 0
B0 D0 0
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Semiconductor Direct Access to Default Store Memory The contents of the default store memory can be changed (e.g., to change tone detection levels and tone generation frequencies) in the initial mode (CR0-B3 to CR0-B0="0000"). Refer to the following procedure: * Set the default value store memory address (CR13, CR14). * Set the write data into CR15 and CR16. * Set the DMWR (change default) command (CR10-B4="1").
Default Value Store Memory Direct Access Set address. Set write data. Set command to write in upper byte (DMWR)
MSM7719-01
(1) CR13, CR14 CR15, CR16
(2) CR10
Yes
Continue to write? No END
Figure 8 Flow Chart of Default Value Store Memory Direct Access
Default Value Store Memory
Data (CR15, CR16)
Address (CR13, CR14)
Figure 7 Memory Map for Default Value Store Memory Direct Access
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Semiconductor
MSM7719-01
Resetting of Echo Canceler Coefficient In cases where an echo path changes, the echo canceler may be slow in converging. In such cases, resetting the coefficient of the echo canceler can force it to converge immediately. In addtion, if the echo path changes after the coefficient is reset, the echo canceler may again be slow in converging. There are four resetting modes available, as shown in the table below. If an echo path changes, execute coefficient reset both by LDCL/ADCL and by LCCL/ACCL pin control (Reset 3) whenever possible, because resetting by both of them do not affect any echo path state.
Degree of Effect on Echo Route Significant
Control No reset (LTHR/ATHR) Reset 1 (LDCL/ADCL) Reset 2 (LCCL/ACCL) Reset 3 (both LDCL/ADCL and LCCL/ACCL)
Echo Convergence Time Fast
Slow
No effect
Notes on Data Communication Use the following setting when making data communication: For 4-bit (32 kbps) data communication: DTHR="1" (common to handsfree communication mode and line echo canceler expansion mode) Notes: 1. The MSM7719 does not support 8-bit (64 kbps) data communication. 2. Data dropouts or a data error of a few SYNCs occurs upon switching between data communication and voice communication. 3. Of the voice data through modes, ATHR and LTHR converts PCM data "7Fh" into "FFh".
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Semiconductor
MSM7719-01
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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