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Color TFT LCD Driver
MN838898
1. Type
CMOS LSI source driver for color TFT LCD panels
2. Overview
This LSI converts the digital display data from a personal computer, portable device, or other source into analog signals for driving a color TFT LCD panel.
3. Features
(1) Power saving driver (2) Built in DA converter accepting 6-bit digital input (for 262,144 colors) (3) Choice of 360 and 324 drive outputs (4) Input data bus at pixel level (5) Choice of output data format: gray scale or binary (6) Eleven reference voltage inputs for producing 10 segment gamma adjustment graph. (7) Set output voltage inflection points at data values 00, 01, 07, 0F, 17, 1F, 27, 2F, 37, 3E, and 3F. (8) Prechargeless drive circuits (9) Support for serial cascade connections (10) Automatic internal clock stop after fixed number of data inputs (11) Choice of shift register shift direction: right or left (12) Gray scale data inversion available every clock cycle (13) Low voltage operation: 2.5 V (typ.) for logic circuits; 3.5 V (typ.) for analog circuits (14) Maximum operating clock frequency: 15 MHz (15) Power save function for cutting off current to outputs, fixing them at high impedance
Publication date: August 2002
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4. Internal Block Diagram
YY1 YX1 YZ1 YX120 YZ120 YY120
AVDD2 AVSS2 AVDD1 AVSS1
Output circuits
AVDD AVSS VREF 0 to 10 PS 6 MODE2 LD 6 6 6 6 6 360/324
11
DA converter
Two line latches, 360/324 x 6 bits
INV DX0 to 5 DY0 to 5 DZ0 to 5
6 6 6
Latch
6
6
6
6
6
6
1 STHR STHL
120
Shift register, 120/108 bits
NTEST
FY
MODE1
RL
DVSS
DV DD
Figure 4.1 Block Diagram
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5. ) Descriptions Pin
Pin Name
I/O Direction
Table 5.1 Pin Descriptions
Pin Function Gray scale digital data input pins Description
Input pins for gray scale (MODE2 = Low) digital data, 6 bits each for R, G, and B. DX5, DY5, and DZ5 represent the MSB; DX0, DY0, and DZ0, the LSB. Input pins for binary (MODE2 = High) digital data, 1 bit each for R, G, and B. Always drive the unused pins (DX4 to DX0, DY4 to DY0, and DZ4 to DZ0) at either High or Low level.
DX0 to 5, DY0 to 5, DZ0 to 5
Input
Binary digital data input pins (DX5, DY5, and DZ5)
YX1 to 120, YY1 to 120, YZ1 to 120
Output
Analog image output pins These signals drive the LCD panel.
These I/O pins are for the internal shift register's start pulses. The following table indicates data shift direction by start pulses during face up.
STH R, STHL
I/O
Start pulse I/O pins
RL =H STHR STHL
Right shift input Right shift output
RL=L
Left shift output
Left shift input
RL FY LD INV MODE1
Input Input Input Input Input
Shift direction input pin Shift clock input pin Data load input pin Data inversion control input pin Number of drive outputs select pin
This specifies the shift direction: High level for right; Low level for left. H: Right shift input (YX,YY,YZ1 120) L: Left shift input (YX,YY,YZ120 1) This accepts the transfer clock for the shift register High level input enables transfer, synchronized with rising edges in the FY signal, of the LCD drive data from the builtin DA converter.
The data logic when the INV input is at Low level is AVDD for Low level and AVSS for High level. Driving INV at High level reverses the data logic. This specifies the number of LCD panel drive outputs: High level for 360, Low level for 324, disabling YX55 to YX66, YY55 to YY66, and YZ55 to YZ66. (For further details, see Section 6.1 "Functional Description.") This specifies the data input format: gray scale or binary. High level: Binary. DX5, DY5, and DZ5 only. The DA converter is off. Low level: Gray scale. DX, DY, and DZ5 to DZ0. The DA converter is on. High level input at a rising edge in the FY signal cuts off current to outputs, fixing them at high-impedance. High level: High-impedance outputs. No current to operational amplifier or other components. Low level: Normal operation Normally fix this input at High level. High level: Normal operation Low level: Test mode
MODE2
Input
Input format select pin
PS
Input
Power save function select pin
NTEST
VREF0 to 10 AVDD, AVSS AVDD1, AVSS1 AVDD2, AVSS2 DVDD, DVSS
Input Input Input Input Input Input
Test input pin (with built-in pull-up resistance) Gamma adjustment potential input pin Analog power supply Analog power supply Analog power supply Digital power supply
This input is the gamma adjustment potential input pin for the DA converter. This is the power supply for the DA converter's analog circuits. This is the power supply for the output analog circuits. This is the power supply for the circuits protecting the output circuits. This is the power supply for the digital circuits.
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6. Description of Operation
6.1 Functional Description
The MODE2 pin offers a choice of 6-bit gray scale data or 1-bit binary data. The MODE1 pin specifies the number of outputs. The following Table summarizes the effects of MODE1 and MODE2, and RL input levels on I/O.
Table 6.1 MODE1 and MODE2, and RL Settings
MODE1 MODE2 RL Input pins FX : 1 DX0 - 5 Low level (gray scale input) High level (360 Outputs) H DY0 - 5 DZ0 - 5 DX0 - 5 L DY0 - 5 DZ0 - 5 DX5 H High level (binary input) L DY5 DZ5 DX5 DY5 DZ5 YX1 YY1 YZ1 2 3 Data transfer direction - 54 55 - - 118 - 119 - 120 Data Output format
- YX2 - YY2 - YZ2
- YX3 - - YX54 - YX55 - - YX118 - YX119 - YX120 - YY3 - - YY54 - YY55 - - YY118 - YY119 - YY120 - YZ3 - - YZ54 - YZ55 - - YZ118 - YZ119 - YZ120 - YX2 - YY2 - YZ2 - YX3 - YY3 - YZ3 64-level analog outputs
YX120 - YX119 - YX118 - - YX67 - YX66 - - YX1 YY120 - YY119 - YY118 - - YY67 - YY66 - - YY1 YZ120 - YZ119 - YZ118 - - YZ67 - YZ66 - - YZ1 YX1 YY1 YZ1 - YX2 - YY2 - YZ2
- YX3 - - YX54 - YX55 - - YX118 - YX119 - YX120 - YY3 - - YY54 - YY55 - - YY118 - YY119 - YY120 - YZ3 - - YZ54 - YZ55 - - YZ118 - YZ119 - YZ120 - YX2 - YY2 - YZ2 - YX3 - YY3 - YZ3 - 108 Binary digital outputs
YX120 - YX119 - YX118 - - YX67 - YX66 - - YX1 YY120 - YY119 - YY118 - - YY67 - YY66 - - YY1 YZ120 - YZ119 - YZ118 - - YZ67 - YZ66 - - YZ1 FX : 1 2 3 - 54 55
- - 106 - 107
DX0 - 5 Low level (gray scale input) Low level (324 Outputs) H High level (binary input) L H DY0 - 5 DZ0 - 5 DX0 - 5 L DY0 - 5 DZ0 - 5 DX5 DY5 DZ5 DX5 DY5 DZ5
YX1 YY1 YZ1
- YX2 - YY2 - YZ2
- YX3 - - YX54 - YX67 - - YX118 - YX119 - YX120 - YY3 - - YY54 - YY67 - - YY118 - YY119 - YY120 - YZ3 - - YZ54 - YZ67 - - YZ118 - YZ119 - YZ120 - YX2 - YY2 - YZ2 - YX3 - YY3 - YZ3 64-level analog outputs
YX120 - YX119 - YX118 - - YX67 - YX54 - - YX1 YY120 - YY119 - YY118 - - YY67 - YY54 - - YY1 YZ120 - YZ119 - YZ118 - - YZ67 - YZ54 - - YZ1 YX1 YY1 YZ1 - YX2 - YY2 - YZ2
- YX3 - - YX54 - YX67 - - YX118 - YX119 - YX120 - YY3 - - YY54 - YY67 - - YY118 - YY119 - YY120 - YZ3 - - YZ54 - YZ67 - - YZ118 - YZ119 - YZ120 - YX2 - YY2 - YZ2 - YX3 - YY3 - YZ3 Binary digital outputs
YX120 - YX119 - YX118 - - YX67 - YX54 - - YX1 YY120 - YY119 - YY118 - - YY67 - YY54 - - YY1 YZ120 - YZ119 - YZ118 - - YZ67 - YZ54 - - YZ1
MODE1 = Low (324 outputs) produces invalid output from YX55 - YX66, YY55 - YY66, and YZ55 - YZ66.
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MN838898 6.2 Relationships Between Data Input and Output Pins
(1) Gray scale data input (MODE2 = Low) The following summarizes the relationships between data input and output pins for gray scale data input (MODE2 = Low). So, binary data input is naturally ignored during gray scale data input. MODE2 = Low, RL = High Rn Bn Gn
6 6 6 DX0 to 5 DY0 to 5 324 outputs
Source driver shifts right (RL = High) DZ0 to 5 YX1 YY1 YZ1 YX2 YY2 YZ2 n=1, 2, ,120 (108)
YX120YY120 YZ120
R1 R1
B1 B1
G1 G1
R2 R2
B2 B2
G2 G2
(R108) (B108) (G108)
R120 B120 G120 R120 B120 G120
(R108) (B108) (G108)
R1
B1
G1
R2
B2
G2
(R108) (B108) (G108)
R120 B120 G120
MODE2 = Low, RL = Low
R1 R1 B1 B1 G1 G1 R2 R2 B2 B2 G2 G2
324 outputs
(R108) (B108) (G108) (R108) (B108) (G108)
R120 B120 G120
R120 B120 G120
R1
B1
G1
R2
B2
G2
(R108) (B108) (G108)
R120 B120 G120
Rn Bn Gn
6 6 6
YZ120 YY120YX120YZ119YY119YX119 DZ0 to 5 DY0 to 5 DX0 to 5
YZ1 YY1 YX1
Source driver shifts left (RL = Low)
n=1, 2, ,120 (108)
(2) Binary input (MODE2 = High) Binary input uses only the pins DX5, DY5, and DZ5. The relationships between data input and output pins are otherwise the same. So, binary data input is naturally ignored during gray scale data input.
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MN838898 6.3 Power Save Function
This signal can be switched anywhere except the latch signal, rising edges in the FY signal.
FY LD PS YX01 to 120, YY01 to 120, YZ01 to 120
Hi-Z
Figure 6.3 High-Impedance Output Interval
6.4 Blanking Interval The following timing chart summarizes the relationships between the load data (LD) and start pulse (STHR and STHL) inputs and the blanking interval.
FY Start pulse inputs STHR (RL = High) STHL (RL = Low) LD
1 FY (Max)
2 FY (Min)
1FY
DX/DY/DZ0 to 5
N-4
N-3
N-2
N-1
N
2FY(Min)
1
2
3
4
Final data input Blanking interval
First data input for first line 1
Figure 6.4 Blanking Interval 6.5 Data Inverse Function
Driving the INV input at High level inverts all bits in the data input.
FY DX 0 to 5 INV
Internal IDX0 data 00 00 00 07 3F 3F 3F 00 00 05 08
to 5
3F
00
3F
07
3F
00
3F
00
00
05
08
Driving the INV input at High level inverts all bits in the data input.
Figure 6.5 Data Inverse Function
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MN838898 6.6 Switching Input Formats
The following timing chart summarizes the relationships between changes in input format and the subsequent changes in output. FY Start pulse inputs STHR (RL = High) STHL (RL = Low) MODE2 LD
Valid input data
Binary data input
Gray scale data input
YX1 to 120, YY1 to 120, YZ1 to 120
Binary data output
Gray scale data output
Figure 6.6.1 Switching Formats (1/2)
The LSI drives the output pins at high-impedance for one FY cycle when changing output formats. FY LD
YX1 to 120, Binary data output YY1 to 120, (or gray scale YZ1 to 120 data output)
Hi-Z
Binary data output (or gray scale data output)
Output switching interval
Figure 6.6.2 Switching Formats (2/2)
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MN838898 6.7 Cascade Connection
(1) RL = High
Driver A starts latching data one FY cycle after receiving a start pulse (STHR). It asserts the carry signal (STHL) one FY cycle before latching the last data and then stopping. MODE1 = High (360 outputs): 119 FY cycles MODE1 = Low (324 outputs): 107 FY cycles Cascade Connection Driver B starts latching data one FY cycle after receiving the carry signal (STHL) from driver A. Note: Although the carry signal (STHL) pulses are two FY cycles long, only the first cycle counts. The next driver treats the two cycles as a single pulse.
119 FY cycles (360 outputs) FY 1FY Pulse #1 1FY 1FY Pulse #2
1 2 3 119 120 121 122 123 124
DATA
LCD controller 6-bit RGB data or 1-bit data
Data latched by driver A
Data latched by driver B
(1)
Start pulse
STHR SRH L
(2)
STHR STHL STHR STHL
Driver A
Driver B Figure 6.7 Serial Cascade Connection
Driver C
(2) RL = Low
The start pulse input is from STHL; the carry output, from STHR. Apart from that, operation is the same as for RL = High.
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6.8 Relationship between Input Data and Output Voltage 6.8.1 Built-In Gamma Adjustment Resistors
The output voltage depends on the input data and thirteen gamma adjustment voltages (VREF x, x = H, 0 to 10, L). See graph and conversion table on the next two pages. The LSI contains ten divider resistances and two switches between VREGF0 and VREGF10. Table 6.8 summarizes the formulas for calculating the output voltages from the voltages applied to pins VREF x, x = 0 to 10. Applying voltages only to VREF0 and VREF10 produces the default graph shown in Figure 6.8.2. Note that we recommend the use of an operational amplifier or similar means to guarantee low-impedance input to the VREF pins. Direct input sometimes fails to produce the desired output voltages.
Inside LSI VREF0 R0
VREF1
VREF2
R1
VREF3
R2
(Note 1)
VREF4
R3
The adjustment voltages (VREF x, x = H, 0 to 10) must satisfy one of the following two relationships.
VREF5 VREF6
R4
or
AVDD > VREF0 VREF1 VREF2 VREF9 VREFL10 > AVSS AVDD > VREF10 VREF9 VREF8 VREF1 VREF0 > AVSS
R5
VREF7
R6 R7
Do not change these voltages while the chip is in operation.
VREF8
The following are the values for the internal resistances R0 to R9 for R2=1.0. Gamma Adjustment Resistances R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 1.15 1.09 1.00 1.00 1.00 1.00 1.00 1.00 1.09 1.15
VREF9
R8
VREF10
R9
Figure 6.8.1 Built-In Gamma Adjustment Resistors
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6.8.2 Relationship between Input Data and Output Voltage
The following Figure gives the gamma adjustment curve for INV = Low.
AVDD VREF 0
VREF 1
VREF 2
VREF 3
Output voltage
VREF 4
VREF 5
VREF 6
VREF 7
VREF 8
VREF 9
VREF 10 AVSS
00 01
07
0F
17
1F Input data
27
2F
37
3E3F
Figure 6.8.2 Relationship between Input Data and Output Voltage
(AVDD > VREF0 VREF1 VREF2 ... ... VREF9 VREF10 > AVSS )
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6.8.3 Relationship between Reference Voltages and Output Voltages The following Table gives the formulas for converting input data for INV = Low.
Table 6.8 Relationship between Reference Voltages and Output Voltages
(AVDD> VREF0 VREF1 VREF2 ... ... VREF9 VREF10 > AVSS ) Input data 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Formula for calculating output voltage VREF0 VREF2 + (VREF1 to VREF2) x 6/7 VREF2 + (VREF1 to VREF2) x 5/7 VREF2 + (VREF1 to VREF2) x 4/7 VREF2 + (VREF1 to VREF2) x 3/7 VREF2 + (VREF1 to VREF2) x 2/7 VREF2 + (VREF1 to VREF2) x 1/7 VREF2 VREF3 + (VREF2 to VREF3) x 7/8 VREF3 + (VREF2 to VREF3) x 6/8 VREF3 + (VREF2 to VREF3) x 5/8 VREF3 + (VREF2 to VREF3) x 4/8 VREF3 + (VREF2 to VREF3) x 3/8 VREF3 + (VREF2 to VREF3) x 2/8 VREF3 + (VREF2 to VREF3) x 1/8 VREF3 VREF4 + (VREF3 to VREF4) x 7/8 VREF4 + (VREF3 to VREF4) x 6/8 VREF4 + (VREF3 to VREF4) x 5/8 VREF4 + (VREF3 to VREF4) x 4/8 VREF4 + (VREF3 to VREF4) x 3/8 VREF4 + (VREF3 to VREF4) x 2/8 VREF4 + (VREF3 to VREF4) x 1/8 VREF4 VREF5 + (VREF4 to VREF5) x 7/8 VREF5 + (VREF4 to VREF5) x 6/8 VREF5 + (VREF4 to VREF5) x 5/8 VREF5 + (VREF4 to VREF5) x 4/8 VREF5 + (VREF4 to VREF5) x 3/8 VREF5 + (VREF4 to VREF5) x 2/8 VREF5 + (VREF4 to VREF5) x 1/8 VREF5 Input data 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Formula for calculating output voltage VREF6 + (VREF5 to VREF6) x 7/8 VREF6 + (VREF5 to VREF6) x 6/8 VREF6 + (VREF5 to VREF6) x 5/8 VREF6 + (VREF5 to VREF6) x 4/8 VREF6 + (VREF5 to VREF6) x 3/8 VREF6 + (VREF5 to VREF6) x 2/8 VREF6 + (VREF5 to VREF6) x 1/8 VREF6 VREF7 + (VREF6 to VREF7) x 7/8 VREF7 + (VREF6 to VREF7) x 6/8 VREF7 + (VREF6 to VREF7) x 5/8 VREF7 + (VREF6 to VREF7) x 4/8 VREF7 + (VREF6 to VREF7) x 3/8 VREF7 + (VREF6 to VREF7) x 2/8 VREF7 + (VREF6 to VREF7) x 1/8 VREF7 VREF8 + (VREF7 to VREF8) x 7/8 VREF8 + (VREF7 to VREF8) x 6/8 VREF8 + (VREF7 to VREF8) x 5/8 VREF8 + (VREF7 to VREF8) x 4/8 VREF8 + (VREF7 to VREF8) x 3/8 VREF8 + (VREF7 to VREF8) x 2/8 VREF8 + (VREF7 to VREF8) x 1/8 VREF8 VREF9 + (VREF8 to VREF9) x 6/7 VREF9 + (VREF8 to VREF9) x 5/7 VREF9 + (VREF8 to VREF9) x 4/7 VREF9 + (VREF8 to VREF9) x 3/7 VREF9 + (VREF8 to VREF9) x 2/7 VREF9 + (VREF8 to VREF9) x 1/7 VREF9 VREF10
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7. Product Standards
A. Absolute Maximum Ratings
Item A1 A2 A3 A4 A5 A6 A7 A8 A9
Digital power supply voltage
Analog power supply voltage
AVSS = DVSS = 0V
Symbol DVDD AVDD VI1 VI2 VO1 VO2 Topr Ta T stg
Rating - 0.3 to 6.5 - 0.3 to 6.5 - 0.3 to DVDD +0.3 - 0.3 to AVDD +0.3 - 0.3 to DVDD +0.3 - 0.3 to AVDD +0.3 - 30 to +85 - 20 to +75 - 40 to +125
Unit V V V V V V C C C
Digital input voltage Analog input voltage Digital output voltage Analog output voltage
Operating storage temperature
Operating ambient temperature
Storage temperature
Note: The above absolute maximum ratings represent limits for avoiding damage to the product. They do not guarantee operation. * The above standards apply only to our standard package for the product.
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B. Operating Conditions
Item Digital power supply voltage Analog power supply voltage Gamma adjustment reference voltages Operating frequency Drive load capacity Digital signal input capacity Symbol Conditions DVDD AVDD VREF X f FY CY C IN
1 MHz
Ta = - 20 C to +75 C AVSS = DVSS = 0V
Rating MIN 1.65 3.0 0.1 TYP 2.5 3.3 MAX 3.6 5.5
AVDD - 0.1
Unit V V V MHz pF pF
B1 B2 B3 B4 B5 B6
15 50 7 15
Notes (1) Use only direct connections to power supply pins sharing the same symbol (AVDD, DVDD). (2) Use only direct connections to ground pins sharing the same symbol (AVSS and DVSS). (3) Apply voltages in the following order: DVDD pins, logic input pins, AVDD pins, and VREF X. Remove them in the reverse order. * The above standards apply only to our standard package for the product.
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C. Electrical Characteristics 1 DC Characteristics
Item C1 C2 C3 C4 C5
Analog operation power supply current (1) Analog operation power supply current (2) DVDD = 2.5V, AVDD = 3.3V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Symbol Conditions Notes 5 and 6
CL = 15pF, R = 2k Notes 5, 6 and 8
MIN
TYP 1.5 1.2
MAX 3.0
Unit
ISS1 ISS2 ISS3 ISS4 ISS5
mA mA
Analog standby power supply current Digital operation power supply voltage Digital standby power supply current
PS = High Notes 4 and 5 Clock signal off 0.5
10 1.0 10
A mA A
(4) Typical conditions
FY frequency of 15 MHz, raster period of 15 kHz, data pattern alternating between 00 and 3F every raster period, fixed VREF x (5) Maximum conditions FY frequency of 15 MHz, raster period of 15 kHz, data pattern alternating between 00 and 3F every raster period, fixed VREF x ISS1 ISS2 ISS3 ISS4
A A AVDD DVDD
DUT
YX1 YY1 YZ1 XY2 YY2 AVSS YZ120
75 pF
AVSS DVSS
DUT : Device Under Test 0V
(6) The loads on the analog output pins are as shown. Note that the numbers for those load circuits sometimes change. (7) The following is the formula for calculating the power consumption with the loads described in note 5 above. ISS1 x AVDD + I SS4 x DVDD (8) When C = 15pF, R = 2k, this value is for reference only. It is not guaranteed. * The above standards apply only to our standard package for the product.
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DVDD = 2.5V, AVDD = 3.3V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Item Symbol Conditions MIN TYP MAX Unit
1) Input pins (RL, LD, DX0 to 5, DY0 to 5, DZ0 to 5, FY, INV, PS, MODE1 , MODE2)
1.65 V DVDD DVDD < 2.5 V 2.5 V DVDD DVDD 3.6 V 1.65 V DVDD DVDD < 2.5 V
0.8 x DVDD 0.7 x DVDD
DVDD DVDD 0.2 x DVDD 0.3 x DVDD
V V V V A
C6
High level input
V IH1
0 0 - 10
C7
Low level input
VIL1
2.5 V DVDD DVDD 3.6 V
C8
Input leak current
I LI1
10
2) I/O pins (STHR, STHL)
1.65 V DVDD DVDD < 2.5 V
0.8 x DVDD 0.7 x DVDD
DVDD DVDD 0.2 x DVDD 0.3 x DVDD
V V V V V
C9
High level input
VIH2
2.5 V DVDD DVDD 3.6 V 1.65 V DVDD
C10 C11 C12 C13
Low level input High level output Low level output Input leak current
VIL2 VOH1 VOL1 I LI2
DVDD < 2.5 V 2.5 V DVDD DVDD 3.6 V DVDD = 2.5 V IO = -1.0 m A
0 0
DVDD - 0.5
DVDD = 2.5 V
IO = 1.0 m A
0.5 - 10 10
V A
3) Pull down pins (NTEST) C14 High level input
1.65 V DVDD
VIH3
DVDD < 2.5 V 2.5 V DVDD DVDD 3.6 V
0.8 x DVDD 0.7 x DVDD
DV DD DV DD 0.2 x DVDD 0.3 x DVDD
V V V V k
C15
Low level input
1.65 V DVDD
VIL3
0 0 160
DVDD < 2.5 V 2.5 V DVDD DVDD 3.6 V
C16
Pull down resistances
R PD
* The above standards apply only to our standard package for the product.
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DVDD = 2.5V, AVDD = 3.3V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Item Symbol Conditions MIN TYP MAX Unit
(3) Gamma adjustment resistances C17 Resistance R
Between VREF 0 and VREF 10
23
36
49
k
(4) Analog output pins (YX1 to 120, YY1 to 120, YZ1 to 120) High level output current (gray scale output) V x = 3.2 V VOUT = 2.2 V
Note 9
C18
I OH1
- 0.05
mA
C19
Low level output current (gray scale output)
I OL1
V x = 0.1 V VOUT = 1.1 V
Note 9 2.5 V V x
0.05 15 10 15 30 20 30
mA
C20
Average output voltage deviation
VO
0.8 V < V x < 2.5 V
mV
V x 0.8 V
C21 Output voltage range
VO V x = 3.3 V VOUT = 2.3V
Note 9
AVSS +0.1
AVDD - 0.1
V
C22
High level output current (binary output)
I OH2
- 0.1
mA
C23
Low level output current (binary output)
I OL2
V x = 0.0 V VOUT = 1.0 V
Note 9
0.1
mA
9) VX is the output voltage for the analog output pin;
VOUT, the voltage applied to the pin. * The above standards apply only to our standard package for the product.
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(2) AC Characteristics
Item C24 FY period C25 FY High level pulse width C26 FY Low level pulse width C27 Data/INV setup time C28 Data/INV hold time C29 Start pulse setup time C30 Start pulse hold time C31 Start pulse Low level pulse width C32 Carry output delay time C33 LD signal High level pulse width C34 LD signal Low level pulse width C35
LD signal-start pulse setup time
DVDD = 3.3V, AVDD = 3.3V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Symbol Conditions MIN 66.6 27 27 15 15 15 15 2
CL = 15 pF
TYP
MAX
Unit ns ns ns ns ns ns ns
FY period
tp t wcH t wcL t st1 t hd1 t st2 t hd2 t wsL t d1 t wldH t wldL t st3 tst4 t sd5 t st5 t hd5 t st6 t hd6 t ng1 t ng2 t d2 t d3 t d4
Duty = 50 %
40 2 2 2 15 15
ns
FY period FY period FY period
C36 LD-FY setup time C37 LD-FY hold time C38 MODE2 setup time C39 MODE2 hold time C40 PS setup time C41 PS hold time C42 Data input invalid interval C43 Final data timing C44 LCD drive signal delay 1 C45 LCD drive signal delay 2 C46 LCD drive signal stop time
ns ns ns ns ns ns 1 1
FY period FY period s s s
Note 10) Note 10)
15 15 15 15
C L = 15 pF, R=2K, Note 10) CL = 15 pF, R = 2K,
Note 11), Note 12)
20 20 5
CL = 15 pF, R = 2K
10) The reference point is the first FY rising edge after the rising edge in the start signal (STHR or STHL). 11) This time is defined as that taken for the driver output voltage to reach, within 6-bit precision, the target voltage. 12) The target output voltage shall be the output voltage just before the power save function takes effectthat is, the latter shall be assumed to have reached the target. * The above standards apply only to our standard package for the product.
SDF00030AEM 17
MN838898
AC Characteristics Timing Chart 1
tp
V IL
DX0 to 5 DY0 to 5 DZ0 to 5 INV1
t wcH
VIH
t wcL
t st1
t hd1
t st2
Input STHR (RL = High), STHL (RL = Low) Output STHL (RL = High) STHR (RL = Low)
t hd2
t wsL
t d1
VOH
t st3
LD
t wldH
FY
Input STHR(RL = High), STHL(RL = Low)
t wldL
t st2
t ng1
tst1
DX0 to 5, DY0 to 5, DZ0 to 5, INV1
thd1
t st5
t hd5
MODE2
Note In the absence of any indication to the contrary, the following levels are assumed. VIH = VOH = 0.8 x DVDD VIL = VOL = 0.2 x DVDD
SDF00030AEM
18
MN838898
AC Characteristics Timing Chart 2
FY
t st4
LD
t hd4
t d2
YX1 to 120, YY1 to 120, YZ1 to 120 Target output voltages
FY
t ng2
LD
DX0 to 5 DY0 to 5 DZ0 to 5 INV1
t st1
VALID VALID VALID
t hd1
INVALID
VALID
FY
t st6
PS
t hd6
t d4
YX1 to 120, YY1 to 120, YZ1 to 120 High-impedance output
t d3
Note In the absence of any indication to the contrary, the following levels are assumed. VIH = VOH = 0.8 x DVDD VIL = VOL = 0.2 x DVDD
SDF00030AEM
19
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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