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500 mA PWM Step-Down DC-DC with Synchronous Rectifier ADP3051
FEATURES
Current mode control for simple loop compensation Input voltage range: 2.7 V to 5.5 V Output voltage range: 0.8 V to 5.5 V Tri-ModeTM operation for high efficiency 550 kHz PWM operating frequency High accuracy over line, load, and temperature Micropower shutdown mode Space-saving MSOP-8 package
GENERAL DESCRIPTION
The ADP3051 is a low noise, current mode, pulse width modulator (PWM) step-down converter capable of supplying over 500 mA to output voltages as low as 0.8 V. This device integrates a low resistance power switch and synchronous rectifier, providing excellent efficiency over the entire output voltage range and eliminating the need for a large and costly external Schottky rectifier. Its 550 kHz switching frequency permits the use of small external components. Current mode control and external compensation allow the regulator to be easily optimized for a wide range of operating conditions. The ADP3051 operates at a constant 550 kHz frequency at medium to heavy loads; it smoothly transitions into Tri-Mode operation to save power at light loads. A pincontrolled micropower shutdown mode is also included. The ADP3051's 2.7 V to 5.5 V input operating range makes it ideal for both battery-powered applications as well as those with 3.3 V or 5 V supply buses. It is available in a space-saving, 8-lead MSOP package.
APPLICATIONS
Li-ion powered handhelds MP3 players PDAs and palmtops Consumer electronics
TYPICAL APPLICATION CIRCUIT
VIN 3.3V
4
ADP3051
IN SHDN COMP FB
5
10H SW 3 12.5k
VOUT 1.8V
7
6
10F 10k
10F
10k 27pF 270pF
PGND
2
GND
8
04768-0-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADP3051 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ........................................................................ 9 PWM Control Mode .................................................................... 9 Tri-Mode Operation..................................................................... 9 100% Duty Cycle Operation ..................................................... 10 Shutdown..................................................................................... 10 Undervoltage Lockout (UVLO) ............................................... 10 Short-Circuit Protection and Recovery................................... 10 Applications..................................................................................... 11 Recommended Components .................................................... 11 Design Procedure ....................................................................... 11 Output Capacitor Selection....................................................... 12 Circuit Board Layout Considerations...................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
6/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3051 SPECIFICATIONS1
VIN = 3.6 V @ TA = -40C to +85C, unless otherwise noted. Table 1.
Parameter SUPPLY Input Voltage Range Quiescent Supply Current Shutdown Supply Current PWM COMPARATOR Minimum Duty Ratio Maximum Duty Ratio OSCILLATOR Oscillator Frequency Foldback Frequency OUTPUT STAGE On Resistance, N Channel Switch Leakage Current, N Channel On Resistance, P Channel Switch Leakage Current, P Channel Current Limit Threshold ERROR AMPLIFIER Feedback Regulation Voltage Feedback Input Bias Current Current Sense Gain Transconductance Maximum Sink Current Maximum Source Current UNDERVOLTAGE LOCKOUT Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis SHDN INPUT THRESHOLD VOLTAGES Input High Threshold Voltage Input Low Threshold Voltage Conditions Min 2.7 VFB = 1.0 V SHDN = 0 V 180 10 0 100 VCOMP 1.5 V, VOUT = 0.7 V VOUT < 0.3 V ISW = 150 mA VIN = 5.0 V, VSW = 0 V FB = GND VSW = 5.0 V 680 TA = 25C 783 770 410 550 200 150 1 190 1 1000 800 5 2.9 0.32 33 33 VIN rising 1.9 55 Referenced to IN 0.4 -0.5 2.6 690 Typ Max 5.5 300 25 Unit V A A % % kHz kHz m A m A mA mV mV nA mS A A V mV V V
1320 821 830
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Rev. 0 | Page 3 of 16
ADP3051 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter IN, SHDN, COMP, SW, FB to GND SW to IN PGND to GND Operating Ambient Temperature Operating Junction Temperature Storage Temperature JA, 2-Layer (SEMI standard board) JA, 4-Layer (JEDEC standard board) Lead Temperature Range Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +6 V -6 V to +0.3 V -0.3 V to +0.3 V -40C to +85C -40C to +125C -65C to +150C 159C/W 116C/W 300C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADP3051 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1 PGND 2 SW 3
8
GND SHDN
04768-0-021
ADP3051
7
TOP VIEW 6 COMP (Not to Scale) 5 FB IN 4
Figure 2. 8-Lead MSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic NC PGND SW IN FB Description No Connect. Not internally connected. Power Ground. Connect PGND to GND at a single point. Use separate power ground and quiet ground planes for the power and sensitive analog circuitry, respectively. See the Circuit Board Layout Considerations section. Switching Output. SW connects to the drain of the internal power switch and synchronous rectifier. Connect the output inductor between SW and the load. Power Source Input. IN is the source of the high side P-channel MOSFET switch, and supplies the internal power to the ADP3051. Bypass IN to GND with a 0.1 F or greater ceramic capacitor, placed as close as possible to IN. Feedback Voltage Sense Input. FB senses the output voltage. To set the output voltage, connect a resistive voltage divider from the output voltage to FB. The feedback threshold is 0.8 V. See the Setting the Output Voltage section. Feedback Loop Compensation Node. COMP is the output of the internal transconductance error amplifier. Place a series RC network from COMP to GND to compensate the regulator. See the Compensation Design section. Shutdown Input. Drive SHDN low to turn off the ADP3051; drive SHDN to within 0.5 V of VIN to turn on the ADP3051. See the Shutdown section. Ground.
6 7 8
COMP SHDN GND
Rev. 0 | Page 5 of 16
ADP3051 TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6V, VOUT = 3.3V, circuit of Figure 20, component values of Table 4, TA = 25C, unless otherwise specified.
100
0.5 0.4
90
VIN = 3.6V VIN = 5.5V
0.3
OUTPUT ACCURACY (%)
EFFICIENCY (%)
80
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
VOUT = 2.5V VIN = 3.6V
70
VOUT = 3.3V L = 22H
60
50
04768-0-002
1
10 ILOAD (mA)
100
1000
0
100
200
300
400
500
ILOAD (mA)
Figure 3. Output Efficiency vs. Load Current, VOUT = 3.3 V
100
Figure 6. Output Voltage Error vs. Load Current
600
90
VIN = 2.7V
580 VIN = 2.7V VIN = 5.5V 540 VIN = 3.6V
EFFICIENCY (%)
80
FREQUENCY (kHz)
560
70
VIN = 3.6V
VOUT = 2.5V L = 22H COUT = 22F
60 VIN = 5.5V 50
520 VOUT = 1.2V ILOAD = 500mA 500
04768-0-003
1
10 ILOAD (mA)
100
1000
-15
10
35
60
85
TEMPERATURE (C)
Figure 4. Output Efficiency vs. Load Current, VOUT = 2.5 V
100
Figure 7. Oscillator Frequency vs. Temperature
600 550
OSCILLATOR FREQUENCY (kHz)
90
VIN = 3.6V
500 450 400 350 300 250 200 150 100 50
EFFICIENCY (%)
80
VIN = 2.5V
70
VIN = 5.5V
VOUT = 1.2V L = 10H COUT = 22F
60
50
04768-0-004
1
10 ILOAD (mA)
100
1000
0
100
200
300
400
500
ILOAD (mA)
Figure 5. Output Efficiency vs. Load Current, VOUT = 1.2 V
Figure 8. Oscillator Frequency vs. Load Current, VIN = 3.6 V, VOUT = 1.2 V
Rev. 0 | Page 6 of 16
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40
0
04768-0-006
40
480 -40
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40
-0.5
ADP3051
04768-0-008
CH1 = VIN, CH2 = SW, CH3 = VOUT, CH4 = IL (1A/DIV) VIN = 3.6V, VOUT = 1.2V, ILOAD = 500mA
CH1 = COMP, CH3 = VOUT, CH4 = ILOAD (50mA TO 490mA) VIN = 3.6V, VOUT = 2.5V, COUT = 22F, CC = 150pF, RC = 100k
Figure 9. Start-Up Behavior
Figure 12. Load Transient Response
04768-0-009
CH2 = IL (100mA/DIV), CH4 = SW VIN = 3.6V, VOUT = 2.5V, L = 22H, IOUT = 50mA
CH1 = VIN, CH2 = VOUT VIN = 3V TO 4V, VOUT = 2.5V, ILOAD = 500mA
Figure 10. Light Load Switching Waveforms
210 200 190
Figure 13. Line Transient Response
PMOS 180
RDSON (m)
170 160 150 140 130 120 NMOS VOUT = 2.5V IOUT = 500mA
04768-0-010
CH2 = IL (500mA/DIV), CH4 = SW VIN = 3.6V, VOUT = 2.5V, L = 22H, IOUT = 500mA
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
Figure 11. Heavy Load Switching Waveforms
Figure 14. Switch On Resistance vs. Input Voltage
Rev. 0 | Page 7 of 16
04768-0-013
110 2.7
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ADP3051
240 220 200
SUPPLY CURRENT (A)
1200
TA = +85C
1150 1100
VIN = 5.5V
180 160 140 120 100 80
CURRENT LIMIT (A)
TA = +25C
1050 VIN = 3.6V 1000 950 900 850 VOUT = 1.2V 800 750 VIN = 2.7V
TA = -40C
VOUT = 1.2V ILOAD = 0mA
3.1
3.5
3.9
4.3
4.7
5.1
5.5
04768-0-014
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
Figure 15. Quiescent Current vs. Input Voltage
Figure 16. Current Limit vs. Input Voltage, VOUT = 1.2 V
Rev. 0 | Page 8 of 16
04768-0-015
60 2.7
700 -40
ADP3051 THEORY OF OPERATION
The ADP3051 is a monolithic current mode buck converter with an integrated high-side switch and low-side synchronous rectifier. It operates with input voltages between 2.7 V and 5.5 V, regulates an output voltage down to 0.8 V, and supplies more than 500 mA of load current. The ADP3051 features patented Tri-Mode technology to operate in fixed frequency PWM mode at medium to heavy loads. This improves light-load efficiency by smoothly transitioning into a variable frequency PWM mode, and into a single-pulse, current-limited variable frequency mode at very light loads. COMP, which sets inductor peak current. The error amplifier, and thus the output voltage, controls the inductor peak current to regulate the output voltage. An internally generated slope compensation circuit ensures that the inner current control loop maintains stable operation over the entire input and output voltage range.
TRI-MODE OPERATION
The ADP3051 features patented Tri-Mode technology which allows fixed-frequency, current mode, PWM operation at medium and heavy loads; smoothly transitions to variable frequency PWM operation to improve light-load efficiency; and operates in a single-pulse, current-limited variable frequency mode at very light loads. These three modes work together to provide high efficiency over a wide range of load current conditions without the frequency jitter, increased output voltage ripple, and audible noise generation exhibited by other lightload control schemes. The ADP3051's internal oscillator is a key component of its Tri-Mode operation. Under medium-heavy load conditions, the oscillator operates at a constant 550 kHz. Under light-load conditions, the oscillator frequency is decreased to minimize switching losses, thus improving light-load efficiency. At very light loads, the oscillator is disabled and the ADP3051 switches only as required to supply the load current for good light-load efficiency. In addition to Tri-Mode operation, the ADP3051 operates in the 200 kHz frequency foldback mode when the voltage at FB is below 0.3 V for enhanced control of the inductor current under short-circuit and startup conditions. See the Short-Circuit Protection and Recovery section.
4 IN
PWM CONTROL MODE
At moderate to high output currents, the ADP3051 operates in a fixed frequency, peak current control mode to regulate the output voltage. At the beginning of each cycle, the P-channel output switch turns on and remains on until the inductor current exceeds the threshold set by the voltage at COMP. When the P-channel switch turns off, the N-channel synchronous rectifier turns on for the remainder of the cycle, after which the cycle repeats. In current mode, two cascaded control loops combine to regulate the output voltage. The outer voltage control loop senses the voltage at FB and compares it to the internal 0.8 V reference. The internal transconductance amplifier forces a current at COMP proportional to the voltage difference between the reference and FB. By selecting the components between COMP and GND, the frequency characteristics of the control system give a stable regulation system. The inner peak-current control loop monitors the current flowing through the P-channel MOSFET and converts that to a voltage. This voltage is internally compared to the voltage at
SHDN 7 FREQUENCY FOLDBACK COMPARATOR CONTROL LOGIC UVLO CURRENT SENSE VOLTAGE REFERENCE
0.4V
OSCILLATOR
COMP 6 ERROR AMPLIFIER FB 5
PWM COMPARATOR
S R
Q
GATE DRIVERS
3 SW
gm
04768-0-016
ADP3051
0.8V 1 NC 8 GND
2 PGND
Figure 17. Simplified Block Diagram
Rev. 0 | Page 9 of 16
ADP3051
100% DUTY CYCLE OPERATION
The ADP3051 is capable of operating at 100% duty cycle, allowing it to regulate output voltages that are very close to the input voltage. In 100% duty cycle operation, the P-channel switch remains continuously on, and the dropout voltage is simply the output current multiplied by the on resistance of the internal switch and inductor, typically 200 mV at full loads (500 mA).
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP3051 includes an internal undervoltage lockout (UVLO) circuit that turns off the converter if the input voltage drops below the 2.2 V UVLO threshold. This prevents uncontrolled behavior if the input voltage drops below the 2.7 V minimum allowable voltage range. The UVLO circuit includes 55mV of hysteresis to prevent oscillation at the UVLO threshold.
SHUTDOWN
The ADP3051 is enabled and disabled via its SHDN input. SHDN easily interfaces to open-drain and three-state logic GPIOs. To enable the ADP3051, drive SHDN to within 0.5 V of the voltage at IN; to disable the ADP3051, drive SHDN below 0.4 V. The circuit of Figure 18 shows a simple means of driving SHDN to the proper high and low input states in cases where no open-drain or three-state GPIO is available.
SHORT-CIRCUIT PROTECTION AND RECOVERY
When starting up or when the output is short circuited, the low voltage drop across the synchronous rectifier may allow the inductor current to run away because it rises more during the on time than it falls during the off time. To protect against this, the ADP3051 automatically initiates a frequency foldback operation when the voltage at FB drops below 0.3 V, allowing the ADP3051 to maintain control of the inductor current under these conditions. When operating at higher input voltages (for example, from a 5 V bus), the ADP3051 may exhibit output voltage overshoot upon startup or after release of an overload condition (see Figure 9). In such cases, the ADP3051's limited COMP slew rate can slow its recovery as the output approaches regulation, allowing the output voltage to overshoot. If overshoot cannot be tolerated in an application, the COMP voltage can be limited by placing a Zener diode from COMP to GND, as shown in Figure 19.
IN
100k
SHDN
SHDN CONTROL
ADP3051
04768-0-017
COMP 6
Figure 18. Shutdown Control Circuit
CMPZ4683-ADC
ADP3051
Figure 19. COMP Zener Clamp to Prevent Short-Circuit Recovery Output Voltage Overshoot
Rev. 0 | Page 10 of 16
04768-0-023
ADP3051 APPLICATIONS
RECOMMENDED COMPONENTS
External component selection for the application circuit shown in Figure 20 depends on the load current requirements. Certain tradeoffs between different performance parameters can also be made. Recommended external component values are given in Table 4.
ADP3051
VIN CIN
4
Where VOUT is the output voltage and VFB is the 0.8 V feedback regulation threshold. RB controls the voltage divider current, IDIV, which is calculated by
I DIV = VFB RB
L VOUT RA
IN SHDN
SW 3
Using higher divider current increases accuracy due to the 5 nA FB input bias current. With RB = 100 k, the accuracy is degraded by 0.0625%. For a given RB, choose the value of RA to set the output voltage by the equation
V RA = RB OUT - 1 VFB
VOUT
7
FB 5
8
COUT RB RC
GND
COMP 6 PGND
2
C2 C1
04768-0-018
ADP3051
5
RA FB
Figure 20. Typical Application Circuit
DESIGN PROCEDURE
For applications where specific performance is required, component combinations other than those listed in Table 4 may be more appropriate. A design procedure for selecting the components is provided in the following sections.
gm
REF ERROR AMPLIFIER
6
COMP
RB
RC C2 C1
04768-0-019
Setting the Output Voltage
The regulated output voltage of the ADP3051 is set by selecting the resistive voltage divider formed by RA and RB (see Figure 21). The voltage divider drops the output voltage to the voltage at FB by the equation
Figure 21. Typical Compensation Network
R VOUT = VFB 1 + A RB
Table 4. Recommended External Components for Popular Input/Output Voltage Conditions (Based on ILOAD = 500 mA Max and a 60 kHz Crossover Frequency)
VIN 2.5 3.6 VOUT 1.0 1.8 1.0 1.8 2.5 1.0 1.8 2.5 3.3 L (H) 6.8 6.8 6.8 8.2 8.2 8.2 10 10 12 COUT (F) 10 10 10 10 10 10 10 10 10 CIN (F) 10 10 10 10 10 10 10 10 10 RA (k) 2.5 12.5 2.5 12.5 21.3 2.5 12.5 21.3 31.3 RB (k) 10 10 10 10 10 10 10 10 10 RC (k) 4.7 10 4.7 10 15 5.7 10 15 18 C1 (pF) 470 270 470 270 180 470 270 180 150 C2 (pF) 47 27 47 27 18 47 27 18 15
5.0
Rev. 0 | Page 11 of 16
ADP3051
Inductor Selection
The ADP3051's high switching frequency allows the use of a physically small inductor. The inductor ripple current is determined by
Where VRIPPLE is the peak-to-peak output ripple voltage and ESRCOUT is the output capacitor ESR. For capacitors with relatively small capacitance and/or resistance, the capacitance dominates the output voltage ripple. In this case, choose the output capacitor by the capacitance using the equation COUT C OUT
I L =
VOUT x (VIN - VOUT ) VIN x f SW x L
(2 x f SW )2 x L x VRIPPLE
I L 8 f SW VOUT
VIN
Where IL is the peak-to-peak inductor ripple current and fSW is the switching frequency. As a guideline, the inductor peak-topeak current ripple is typically set to be one-third the maximum dc load current. Using this guideline and solving for L,
3 x VOUT x (VIN - VOUT ) L= VIN x f SW x I LOAD ( MAX ) Simplifying for the known constants L = 5 H x VOUT x (VIN - VOUT ) VIN x I LOAD( MAX )
Multilayer ceramic (MLC), tantalum, OS-CON, or similar low ESR capacitors are recommended. Table 5 lists some vendors that make suitable capacitors.
Table 5. Capacitor Suppliers
Manufacturer AVX Murata Sanyo Taiyo-Yuden Capacitor Type Tantalum MLCC OS-CON MLCC Contact Info www.avxcorp.com www.murata.com www.sanyovideo.com www.t-yuden.com
It is important to ensure that the inductor is capable of handling the maximum peak inductor current, ILPK, determined by
I I LPK = I LOAD ( MAX ) + L 2 Finally, the ADP3051's internal slope compensation is designed to ensure stability of the inner current mode control loop when the inductor is chosen so that the down-slope of the inductor current is less than 320 mA/s L VOUT 320 mA / s
Input Capacitor Selection
The input capacitor reduces input voltage ripple caused by switch currents. Select an input capacitor capable of withstanding the rms input current I CIN ( RMS ) I LOAD( MAX ) VOUT (VIN - VOUT ) VIN
OUTPUT CAPACITOR SELECTION
The output capacitor should be chosen to meet output voltage ripple requirements for the application. Output voltage ripple is a function of the inductor ripple current and the impedance of the output capacitor at the switching frequency. The magnitude of the capacitive impedance is
X COUT = 1 2 x COUT x f SW
Where ICIN(RMS) is the rms ripple rating of the input capacitor. As with the output capacitor, a low ESR capacitor is recommended to help to minimize input voltage ripple.
Compensation Design
The ADP3051's external compensation network allows designers to easily optimize the part's performance for a particular application with just a series RC network (RC and C1 of Figure 21) from COMP to GND typically required to compensate the regulator. The dc loop gain is given by the equation
AVDC = VFB x G EA x ROEA x RLOAD VOUT x RCS
For capacitors with relatively large capacitance or high equivalent series resistance (ESR), e.g., tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency; therefore, the output ripple voltage is mainly a function of ESR. In this case, the output capacitor should be chosen based on the ESR by the equation
ESRCOUT VRIPPLE I L
where: VFB is the feedback voltage regulation threshold, 0.8 V. GEA is the error amplifier transconductance, 320 s. ROEA is the error amplifier output impedance (10 M). RCS is the 2.9 current sense gain. RLOAD is the equivalent output resistance, equal to the output voltage divided by the load current.
Rev. 0 | Page 12 of 16
ADP3051
The system has three poles and a zero that dominate its frequency response. The first compensation pole is given by
f PC1 =
1 2 x ROEA x C1
CIRCUIT BOARD LAYOUT CONSIDERATIONS
A good circuit board layout aids in extracting the most performance from the ADP3051. Poor circuit layout degrades the output ripple and the electromagnetic interference (EMI) or electromagnetic compatibility (EMC) performance. The evaluation board layout of Figure 24 is optimized for the ADP3051. Use this layout for best performance. If this layout needs changing, use the following guidelines: 1. Use separate analog and power ground planes. Connect the sensitive analog circuitry (such as compensation and voltage divider components) to analog ground; connect the power components (such as input and output bypass capacitors) to power ground. Connect the two ground planes together near the load to reduce the effects of voltage dropped on circuit board traces. Locate CIN as close to the IN pin as possible, and use separate input bypass capacitors for the analog and power grounds indicated in Guideline 1. Route the high current path from CIN, through L, to the SW and PGND pins as short as possible. Route the high current path from CIN through L and COUT as short as possible. Keep high current traces as short and as wide as possible. Place the feedback resistors as close as possible to the FB pin to prevent noise pickup. Place the compensation components as close as possible to the COMP pin. Avoid routing high impedance traces, such as FB and COMP, near the high current traces and components or near the switch node (SW). If high impedance traces are routed near high current and/or the SW node, place a ground plane shield between the traces.
The output pole is given by f POUT = 1 2 x RLOAD x COUT
If used, the optional second compensation pole is given by f PC 2 = 1 2 x RC x C 2
Finally, the zero can be calculated as
f ZC =
1 2 x RC x C1
2.
Note that the dc loop gain is the inverse of the output load current, while the output pole, fPOUT, is proportional to the load current. Thus, the crossover frequency, which is proportional to the product of the dc loop gain and the output pole frequency, remains the same. To choose the compensation components, first choose the regulator loop crossover frequency (the frequency where the loop gain drops to 1 V/V or 0 dB). To determine the desired crossover frequency, chose it for about one-tenth of the switching frequency or 60 kHz. The required compensation resistor, RC, can be determined from the equation RC = 2 x f C x VOUT x RCS x COUT VREF x G EA
3. 4. 5. 6. 7. 8.
Where fC is the crossover frequency. To make sure the phase margin is suitable, choose the first compensation capacitor to set the zero frequency to one-fourth the crossover frequency, or C1 = 4 2 x f C x RC
9.
An optional second compensation capacitor reduces the high frequency gain to reduce the high frequency noise. If used, choose the second compensation capacitor to set the second compensation pole to the switching frequency, or
C2 =
1 2 x f SW x RC
Rev. 0 | Page 13 of 16
ADP3051
Figure 22. Sample Application Circuit Board Layout (Silkscreen Layer)
04768-0-024
Figure 24. Sample Application Circuit Board Layout (Bottom Layer)
Figure 23. Sample Application Circuit Board Layout (Top Layer)
Rev. 0 | Page 14 of 16
04768-0-026
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ADP3051 OUTLINE DIMENSIONS
3.00 BSC
8
5
3.00 BSC
4
4.90 BSC
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.15 0.00 0.38 0.22 COPLANARITY 0.10
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 25. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3051ARMZ-REEL71 Temperature Range -40C to +85C Package Description 8-Lead Mini Small Outline Package [MSOP] Package Outline RM-8 Branding P3A
1
Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADP3051 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04768-0-6/04(0)
Rev. 0 | Page 16 of 16

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