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Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FEATURES
* Fully integrated PLL * 4 differential 3.3V or 2.5V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS TEST_CLK input * Output frequency range: 62.5MHz to 350MHz * VCO range: 250MHz to 700MHz * Parallel interface for programming counter and output dividers during power-up * Serial 3 wire interface * Cycle-to-cycle jitter: 23ps (typical) * Output skew: 16ps (typical) * Output duty cycle: 49% < odc < 51%, fout 125MHz * Full 3.3V or mixed 3.3V core, 2.5V operating supply * 0C to 85C ambient operating temperature * Lead-Free package available
GENERAL DESCRIPTION
The ICS84314 is a general purpose quad output frequency synthesizer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. When the device uses parallel loading, the M bits are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 2 or divide by 4, providing a frequency range of 62.5MHz to 350MHz. The low cyclecycle jitter and broad frequency range of the ICS84314 make it an ideal clock generator for a variety of demanding applications which require high performance.
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL2 XTAL1 M3 M2 M1 M0
VCO_SEL
32 31 30 29 28 27 26 25
XTAL_SEL
M4
TEST_CLK XTAL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
24 23 22
TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO
0
M5 M6
OSC
XTAL2
1
/ 16
M7 M8 VEE VCC
ICS84314
21 20 19 18 17
PLL
PHASE DETECTOR
MR
VCCO
Q0 nQ0
0 1
VCO /M
/2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8
/2 /4
Q1 nQ1 Q2 nQ2 Q3 nQ3
CONFIGURATION INTERFACE LOGIC
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. C JANUARY 27, 2005
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
nP_LOAD input is initially LOW. The data on inputs M0 through M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M bits can be hardwired to set the M divider to a specific default state that will automatically occur during power-up. In parallel mode, the N output divider is set to 2. In serial mode, the N output divider can be set for either /2 or /4. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 M 350. The frequency out is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1 N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK.
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84314 support two input modes to program the M divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the
SERIAL LOADING
S_CLOCK
S_DATA S_LOAD
*NULL *NULL *NULL *NULL
t
S
**N
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8
M
nP_LOAD
t
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
N Logic Value 0 1 Output Divide /2 /4
*NOTE: The NULL timing slot must be observed. **NOTE: "N" can only be controlled through serial loading.
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REV. C JANUARY 27, 2005
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Type Input Input Power Power Power Output Output Output Output Description
TABLE 2. PIN DESCRIPTIONS
Number 1, 2, 3, 4, 29, 30, 31, 32 5 6 7 8, 17 9, 10 11, 12 13, 14 15, 16 Name M4, M5, M6, M7, M0, M1, M2, M3 M8 VEE VCC VCCO Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Negative supply pin. Core power supply pin.
Output supply pins. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted 18 MR Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 19 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge 20 S_DATA Input Pulldown of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. 21 S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. 22 VCCA Power Analog supply pin. Selects between the crystal oscillator or test clock as the PLL 23 XTAL_SEL Input Pullup reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 24 TEST_CLK Input Pulldown Test clock input. LVCMOS interface levels. Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. 25, 26 XTAL1, XTAL2 Input Parallel load input. Determines when data present at M8:M0 27 nP_LOAD Input Pulldown is loaded into the M divider. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 28 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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REV. C JANUARY 27, 2005
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 4A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M inputs passed directly to the M divider. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked.
MR H L L L L L L
nP_LOAD X L H H H H
M X Data Data X X X X
S_LOAD X X L L L
L H X H NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 250 252 254 256 * M Divide 125 126 127 128 * 256 M8 0 0 0 0 * 128 M7 0 0 0 1 * 64 M6 1 1 1 0 * 32 M5 1 1 1 0 * 16 M4 1 1 1 0 * 8 M3 1 1 1 0 * 4 M2 1 1 1 0 * 2 M1 0 1 1 0 * 1 M0 1 0 1 0 *
* * 696 348 698 349 700 350 NOTE 1: These M divide values and frequency of 16MHz.
* * * * * 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 the resulting frequencies correspond to
* * * * 1 1 0 0 1 1 0 1 1 1 1 0 cr ystal or TEST_CLK input
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input N Logic 0 1 N Divide 2 4 Output Frequency (MHz) Qx, nQx Minimum Maximum 12 5 350 62.5 175
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REV. C JANUARY 27, 2005
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol VCC VCCA VCCO I EE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 150 17 Units V V V V mA mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol Input High Voltage Parameter TEST_CLK; NOTE 1 VIH VCO_SEL, XTAL_SEL, nP_LOAD, MR, M0:M8, S_LOAD, S_DATA, S_CLOCK TEST_CLK; NOTE 1 VIL Input Low Voltage VCO_SEL, XTAL_SEL, nP_LOAD, MR, M0:M8, S_LOAD, S_DATA, S_CLOCK M0:M7, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD M8, XTAL_SEL, VCO_SEL TEST_CLK M0:M7, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD M8, XTAL_SEL, VCO_SEL NOTE:1 Characterized with 1ns input edge rate. Test Conditions Minimum 2.35 2 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.95 0.8 Units V V V V
IIH
Input High Current
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150
150 5 200
A A A A A
IIL
Input Low Current
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Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit".
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 85C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL1, XTAL2; NOTE 1 Test Conditions Minimum 10 12 Typical Maximum 40 40 Units MHz MHz
S_CLOCK 50 MHz NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 M 466. Using the maximum frequency of 40MHz, valid values of M are 50 M 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 12 Test Conditions Minimum Typical Maximum 40 50 7 Units MHz pF
Fundamental
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum Typical 23 16 20% to 80% 200 5 5 5 5 5 5 fOUT > 125MHz fOUT 125MHz 48 49 50 50 52 51 1 Maximum 350 35 8 30 700 Units MHz ps ps ps ps ns ns ns ns ns ns % % ms
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 85C
Symbol FMAX Parameter Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD odc Output Duty Cycle
tjit(cc) tjit(per) tsk(o)
tR / tF
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 85C
Symbol FMAX Parameter Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD odc Output Duty Cycle fOUT > 125MHz fOUT 125MHz 20% to 80% 200 5 5 5 5 5 5 48 49 50 50 52 51 1 16 23 Test Conditions Minimum Typical Maximum 350 35 7 35 700 Units MHz ps ps ps ps ns ns ns ns ns ns % % ms
tjit(cc) tjit(per) tsk(o)
tR / tF
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V 2.8V0.04V V CC, VCCA, VCCO
Qx
2V
SCOPE
VCC, VCCA V CCO
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
nQx Qx
tcycle
n
tsk(o)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
VOH VREF
CYCLE-TO-CYCLE JITTER
80%
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
Clock Outputs
Histogram
20% tR tF
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
nQx Qx
Pulse Width t
PERIOD
OUTPUT RISE/FALL TIME
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
80% VSW I N G 20%
REV. C JANUARY 27, 2005
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84314 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
ground level. The R3 in Figure 4A can be eliminated and the termination is shown in Figure 4C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCCO=2.5V
2.5V
2.5V
Zo = 50 Ohm
VCCO=2.5V
+
Zo = 50 Ohm
R1 250
R3 250
Zo = 50 Ohm
+
2,5V LVPECL Driv er
R1 50
Zo = 50 Ohm
-
R2 50
2,5V LVPECL Driv er
R2 62.5
R4 62.5
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
CRYSTAL INPUT INTERFACE
The ICS84314 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 5 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL2
C1 22p
X1 18pF Parallel Cry stal
XTAL1
C2 22p
Figure 5. CRYSTAL INPUt INTERFACE
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS84314 layout example used in this layout guideline is shown in Figure 6A. The ICS84314 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
Logic Input Pin Examples
C1
X1
C2
VCC=3.3V
VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
U3
32 31 30 29 28 27 26 25
ICS84314
VCC
R7 10
M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL2 XTAL1
VCC
1 2 3 4 5 6 7 8
VCC
M4 M5 M6 M7 M8 VEE VCC VCCO
TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO
24 23 22 21 20 19 18 17
To Logic Input pins
RD1 Not Install
RD2 1K
To Logic Input pins
VCCA
C11 0.01u
C16 10u
VCC
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
C4 0.1u
9 10 11 12 13 14 15 16
C5 0.1u
C3 0.1u
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2 50
R1 50
C6 (Option) 0.1u
R3 50
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R5 50
R4 50
C7 (Option) 0.1u
R6 50
FIGURE 6A. SCHEMATIC
OF
3.3V/3.3V RECOMMENDED LAYOUT
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
* The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 25 (XTAL1) and 26 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
X1
GND
C1
C2
VCC
VIA
U1
PIN 1
C11
C16
VCCA R7
C5
C4
C3
FIGURE 6B. PCB BOARD LAYOUT
FOR
ICS84314
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Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84314. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS84314 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.7mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 519.7mW + 120mW = 639.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.640W * 42.1C/W = 111.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84314AY
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Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
- 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = V (V
CCO_MAX
OL_MAX
=V
CCO_MAX
- 1.7V
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER RELIABILITY INFORMATION
TABLE 10. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314 is: 3509
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc
Reference Document: JEDEC Publication 95, MS-026
84314AY
MINIMUM
NOMINAL 32
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0 0.60 0.75 7 0.10
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0.15 1.40 0.37 1.45 0.45 0.20
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Marking ICS84314AY ICS84314AY ICS84314AYLF ICS84314AYLF Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C
TABLE 12. ORDERING INFORMATION
Part/Order Number ICS84314AY ICS84314AYT ICS84314AYLF ICS84314AYLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84314AY
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Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
REVISION HISTORY SHEET Description of Change LVPECL table - changed VOH max. from VCC - 1.0V to VCC - 0.9V. Changed equations in Power Considerations to correlate with Table 5C. LVCMOS/LVTTL TEST_CLK changed to LVCMOS TEST_CLK. Added Lead-Free bullet . Pin Descriptions Table - Pin 24, TEST_CLK, description changed from LVCMOS/LVTTL interface levels to LVCMOS interface levels. LVCMOS DC Characteristics - TEST_CLK VIH (min.) changed from 2V to 2.35V; VIL (max.) changed from 1.3V to 0.95V. Added Lead-Free par t number to Ordering Information Table. LVCMOS DC Characteristics Table - added VIH/VIL NOTE 1. 1/27/05 Date 2/4/04
Rev B
Table T5C
Page 6 13 - 14 1 3 5 17 5
T1 C T5B T12 T5B
11/5/04
C
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