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74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1992 Revised March 2005
74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT574 is an octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The device is functionally identical to the ABT374 but has broadside pinouts.
Features
s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to ABT374 s 3-STATE outputs for bus-oriented applications s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT574CSC 74ABT574CSJ 74ABT574CMSA 74ABT574CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description
(c) 2005 Fairchild Semiconductor Corporation
DS011511
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74ABT574
Functional Description
The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.
Function Table
Inputs OE H H H H L L L L
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition NC No Change
Internal D L H L H L H L H Q NC NC L H L H NC NC
Outputs O Z Z Z Z L H NC NC Hold Hold Load Load
Function
CP H or L H or L

Data Available Data Available No Change in Data No Change in Data
H or L H or L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT574
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA)
65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns
40qC to 85qC 4.5V to 5.5V
0.5V to 5.5V 0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 Min 2.0 0.8 Typ Max Units V V V V V Min Min Min VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID
1.2
18 mA 3 mA 32 mA
64 mA 2.7V (Note 3) VCC 7.0V 0.5V (Note 3) 0.0V 1.9 PA
PA PA PA
V
Max Max Max 0.0 0 5.5V 0 5.5V Max Max 0.0 Max Max Max
1 1
All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE 10
PA PA
mA
VOUT VOUT VOUT VOUT VOUT
2.7V; OE 0.5V; OE 0.0V VCC
2.0V 2.0V
10 100 275
50 100 50 30 50 2.5 2.5 2.5
PA PA PA
mA
5.5V; All Other GND
All Outputs HIGH All Outputs LOW OE VI VCC V CC 2.1V VCC 2.1V VCC 2.1V
PA
mA mA mA
All Others at VCC or GND Max Enable Input VI Data Input VI
All Others at VCC or GND ICCD Dynamic ICC (Note 3)
Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD 0.8 mA/MHz.
No Load 0.30
mA/ MHz
Max
Outputs Open, OE 50% Duty Cycle
GND,
One Bit Toggling (Note 4),
3
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74ABT574
DC Electrical Characteristics
(SOIC Package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage Min Typ 0.7 Max 1.0 Units V V V V 0.8 V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL TA TA TA TA TA 50 pF, RL 500:
25qC (Note 5) 25qC (Note 5) 25qC (Note 6) 25qC (Note 7) 25qC (Note 7)
1.5
2.5 2.0
1.1
3.0 1.6 1.2
Note 5: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package) TA Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 150 2.0 2.0 1.5 1.5 1.5 1.5 VCC CL
25qC 5.0V
50 pF Typ 200 3.2 3.3 3.1 3.1 3.6 3.4 5.0 5.0 5.3 5.3 5.4 5.4 Max
TA
55qC to 125qC
4.5V to 5.5V 50 pF Max 7.0 7.4 6.5 7.2 7.2 6.7 CL Min 150 1.5 1.5 1.0 1.0 1.0 1.0
TA VCC
40qC to 85qC
4.5V to 5.5V CL 50 pF Max MHz 5.0 5.0 5.3 5.3 5.4 5.4 ns ns ns Units
VCC
Min 150 2.0 2.0 1.5 1.5 1.5 1.5
AC Operating Requirements
TA Symbol Parameter VCC CL Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP, HIGH or LOW 1.0 1.5 1.0 1.0 3.0 3.0
25qC 5.0V
50 pF Max
TA
55qC to 125qC
4.5V to 5.5V CL Min 1.5 2.0 2.0 2.0 3.3 3.3 50 pF Max
TA VCC
40qC to 85qC
4.5V to 5.5V 50 pF Max ns ns ns CL Units
VCC
Min 1.0 1.5 1.0 1.0 3.0 3.0
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74ABT574
Extended AC Electrical Characteristics
(SOIC Package) TA VCC Symbol Parameter
40qC to 85qC
4.5V to 5.5V 50 pF CL
TA VCC
40qC to 85qC
4.5V to 5.5V 250 pF CL
TA VCC
40qC to 85qC
4.5V to 5.5V 250 pF Units CL
8 Outputs Switching (Note 8) Min tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay CP to On Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Max 5.7 5.7 6.2 6.2 5.5 5.5
(Note 9) Min 2.0 2.0 2.0 2.0 (Note 11) Max 7.8 7.8 8.0 8.0
8 Outputs Switching (Note 10) Min 2.0 2.0 2.0 2.0 Max 10.0 10.0 10.5 10.5 ns ns ns
(Note 11)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE Delay Times are dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Skew (Note 12)
(SOIC package) TA
40qC to 85qC
4.5V-5.5V 50 pF CL
TA
40qC to 85qC
4.5V-5.5V 250 pF Units CL
VCC Symbol Parameter
VCC
8 Outputs Switching (Note 12) Max tOSHL (Note 14) tOSLH (Note 14) tPS (Note 15) tOST (Note 14) tPV (Note 16) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.0 1.0 1.8 2.0 2.5
8 Outputs Switching (Note 13) Max 1.8 1.8 4.3 4.3 4.6 ns ns ns ns ns
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested.
Capacitance
Conditions Symbol CIN COUT (Note 17) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0
1 MHz, per MIL-STD-883, Method 3012.
Units pF pF V CC V CC 0V 5.0V
TA
25qC
Note 17: COUT is measured at frequency f
5
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74ABT574
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns
FIGURE 2. VM
1.5V
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT574
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74ABT574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ABT574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
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74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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