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K5A3x40YT(B)C
Document Title
Multi-Chip Package MEMORY
Preliminary MCP MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
November 6, 2002
Remark
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 0.0 November 2002
K5A3x40YT(B)C
Multi-Chip Package MEMORY
Preliminary MCP MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
FEATURES
* Power Supply voltage : 2.7V to 3.3V * Organization - Flash : 4,194,304 x 8 / 2,097,152 x 16 bit - SRAM : 524,288 x 8 / 262,144 x 16 bit * Access Time (@2.7V) - Flash : 70 ns, SRAM : 55 ns * Power Consumption (typical value) - Flash Read Current : 14 mA (@5MHz) Program/Erase Current : 15 mA Standby mode/Autosleep mode : 5 A Read while Program or Read while Erase : 25 mA - SRAM Operating Current : 20 mA Standby Current : 0.5 A * Secode(Security Code) Block : Extra 64KB Block (Flash) * Block Group Protection / Unprotection (Flash) * Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb * Flash Endurance : 100,000 Program/Erase Cycles Minimum * SRAM Data Retention : 1.5 V (min.) * Industrial Temperature : -40C ~ 85C * Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch 1.2mm(max.) Thickness
GENERAL DESCRIPTION
The K5A3x40YT(B)C featuring single 3.0V power supply is a Multi Chip Package Memory which combines 32Mbit Dual Bank Flash and 4Mbit fCMOS SRAM. The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit and 4Mbit SRAM is organized as 512K x8 or 256K x16 bit. The memory architecture of flash memory is designed to divide its memory arrays into 71 blocks and this provides highly flexible erase and program capability. This device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization. The Flash memory performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed for typically 0.7sec. The 4Mbit SRAM supports low data retention voltage for battery backup operation with low data retention current. The K5A3x40YT(B)C is suitable for the memory of mobile communication system to reduce mount area. This device is available in 69-ball TBGA Type package.
BALL CONFIGURATION
BALL DESCRIPTION
Ball Name A0 to A17 Description Address Input Balls (Common) Address Input Balls (Flash Memory) Data Input/Output Balls (Common) Hardware Reset (Flash Memory) Write Protection / Acceleration Program (Flash Memory) Power Supply (SRAM) Power Supply (Flash Memory) Ground (Common) Upper Byte Enable (SRAM) Lower Byte Enable (SRAM) BYTES Control (SRAM) BYTEF Control (Flash Memory) Address Inputs (SRAM) Chip Enable (Flash Memory) Chip Enable (SRAM Low Active) Chip Enable (SRAM High Active) Write Enable (Common) Output Enable (Common) Ready/Busy (Flash memory) No Connection
1 A B C D E F G H J K
N.C N.C N.C
2
3
4
5
N.C
6
7
8
9
10
A-1, A18 to A20 DQ0 to DQ15
N.C
N.C
RESET WP/ACC
N.C
A7
LB
WP/ ACC
WE
A8
A11
A3
A6
UB
RESET CS2S
A19
A12
A15
VccS VccF Vss UB LB
A2
A5
A18
RY/BY
A20
A9
A13
N.C
A1
A4
A17
A10
A14
N.C
N.C
N.C
A0
Vss
DQ1
DQ6
SA
A16
N.C
BYTES
DQ3 DQ4 DQ13 DQ15 BYTE F /A-1 DQ7 Vss
CEF
OE
DQ9
BYTEF SA CEF
CS1S
DQ0
DQ10
VccF
VccS
DQ12
DQ8
DQ2
DQ11
BYTES
DQ5
DQ14
CS1S CS2S
N.C
N.C
N.C
WE OE
69 Ball TBGA , 0.8mm Pitch
RY/BY N.C
Top View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2Revision 0.0 November 2002
K5A3x40YT(B)C
ORDERING INFORMATION
Preliminary MCP MEMORY
K 5 A 3 x 4 0 Y T C - T 7 55
Samsung MCP Memory Device Type Dual Bank Boot Block NOR + fCMOS SRAM NOR Flash Density (Bank Size), (Organization) 32 : 32Mbit, (8Mb, 24Mb) (x8/x16 Selectable) 33 : 32Mbit, (16Mb, 16Mb) (x8/x16 Selectable) SRAM Density , Organization 4Mbit, x8/x16 Selectable Operating Voltage Range 2.7V to 3.3V Block Architecture T = Top Boot Block B = Bottom Boot Block SRAM Access Time 55 = 55 ns Flash Access Time 7 = 70 ns 8 = 80 ns Package T = 69 TBGA Version C = 4th Generation
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VccF Vss RESET RD/BY A0 to A17 (Common) A-1,A18 to A20 BYTEF WP/ACC CEF OE WE
I/O Interface & Bank Control Bank1 Address X Dec Bank1 Cell Array Y Dec
Bank1 Data-In/Out Bank2 Data-In/Out
Latch & Control
Y Dec Bank2 Address X Dec Bank2 Cell Array Erase Control Program Control
Latch & Control
High Voltage Gen.
Clk gen.
Precharge circuit.
DQ0 to DQ7 DQ8 to DQ15
SA UB LB BYTES CS1S CS2S VccS Vss
Row select
SRAM Main Cell Array
(256K x16, 512K x8)
Control logic
Data control
I/O Circuit Column select Bottom Boot Block
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K5A3x40YT(B)C
K5 A3240 YT K5 A3340 YT Block Address Block A20 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 Bank1 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 Bank1 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 Bank2 BA41 BA40 BA39 BA38 BA37 BA36 BA35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 A17 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 A16 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 A15 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 A14 1 1 1 1 0 0 0 0 X X X X X X X X X X A13 1 1 0 0 1 1 0 0 X X X X X X X X X X A12 1 0 1 0 1 0 1 0 X X X X X X X X X X
Preliminary MCP MEMORY
Address Range Byte Mode 3FE000H-3FFFFFH 3FC000H-3FDFFFH 3FA000H-3FBFFFH 3F8000H-3F9FFFH 3F6000H-3F7FFFH 3F4000H-3F5FFFH 3F2000H-3F3FFFH 3F0000H-3F1FFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2FFFFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH Word Mode 1FF000H-1FFFFFH 1FE000H-1FEFFFH 1FD000H-1FDFFFH 1FC000H-1FCFFFH 1FB000H-1FBFFFH 1FA000H-1FAFFFH 1F9000H-1F9FFFH 1F8000H-1F8FFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH
Table 1. Flash Memory Top Boot Block Address (K5A3240YT/K5A3340YT)
Block Size (KB/KW) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
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K5 A3240 YT K5 A3340 YT Block Address Block A20 BA34 Bank1 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 Bank2 Bank2 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 BA17 BA16 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A17 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X
Preliminary MCP MEMORY
Address Range Byte Mode 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH Word Mode 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 000000H-007FFFH
Table 1. Flash Memory Top Boot Block Address (K5A3240YT/K5A3340YT)
Block Size (KB/KW) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
NOTE: The address range is A20 A-1 in the byte mode ( BYTEF = VIL ) or A20 A0 in the word mode ( BYTEF = VIH ).
The bank address bits is A20 A19 for K5A3240YT, A20 for K5A3340YT.
Table 2. Secode Block Addresses for Top Boot Devices
Device K5A3240YT/K5A3340YT Block Address A20-A12 111111xxx Block Size 64/32 (X8) Address Range 3F0000H-3FFFFFH (X16) Address Range 1F8000H-1FFFFFH
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K5A3x40YT(B)C
K5 A3240 YB K5 A3340 YB Block Address Block A20 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 Bank2 Bank2 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 A18 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Preliminary MCP MEMORY
Address Range Byte Mode 3F0000H-3FFFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2F1FFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH Word Mode 1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH
Table 3. Flash Memory Bottom Boot Block Address (K5A3240YB/K5A3340YB)
Block Size (KB/KW) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
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K5A3x40YT(B)C
K5 A3240 YB K5 A3340 YB Block Address Block A20 BA34 BA33 BA32 BA31 BA30 BA29 Bank2 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 Bank1 BA17 BA16 BA15 BA14 BA13 BA12 Bank1 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 0 0 0 0 0 0 A19 1 1 1 1 1 1 A18 1 1 1 1 0 0 A17 0 0 0 0 1 1 A16 1 1 0 0 1 1 A15 1 0 1 0 1 0 A14 X X X X X X A13 X X X X X X A12 X X X X X X
Preliminary MCP MEMORY
Address Range Byte Mode 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 00E000H-00FFFFH 00C000H-00DFFFH 00A000H-00BFFFH 008000H-009FFFH 006000H-007FFFH 004000H-005FFFH 002000H-003FFFH 000000H-001FFFH Word Mode 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 007000H-007FFFH 006000H-006FFFH 005000H-005FFFH 004000H-004FFFH 003000H-003FFFH 002000H-002FFFH 001000H-001FFFH 000000H-000FFFH
Table 3. Flash Memory Bottom Boot Block Address (K5A3240YB/K5A3340YB)
Block Size (KB/KW) 64/32 64/32 64/32 64/32 64/32 64/32
NOTE: The address range is A20 A-1 in the byte mode ( BYTEF = VIL ) or A20 A0 in the word mode ( BYTEF = VIH ).
The bank address bits is A20 A19 for K5A3240YB, A20 for K5A3340YB.
Table 4. Secode Block Addresses for Bottom Boot Devices
Device K5A3240YB/K5A3340YB Block Address A20-A12 000000xxx Block Size 64/32 (X8) Address Range 000000H-00FFFFH (X16) Address Range 000000H-007FFFH
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K5A3x40YT(B)C
Flash MEMORY COMMAND DEFINITIONS
Preliminary MCP MEMORY
Flash memory operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 5. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress.
Table 5. Command Sequences
1st Cycle Command Sequence Addr Read Data Addr Reset Data Autoselect Manufacturer ID (2,3) Autoselect Device Code (2,3) Autoselect Block Group Protect Verify (2,3) Auto Select Secode Block Factory Protect Verify (2,3) Enter Secode Block Region Exit Secode Block Region Program Data Unlock Bypass Addr 3 Data Unlock Bypass Program Unlock Bypass Reset Chip Erase Data Addr Block Erase Data Block Erase Suspend (4, 5) Block Erase Resume Addr 1 Data Addr 1 Data 30H B0H XXXH 6 AAH XXXH 55H 80H AAH 55H 30H Addr 2 Data Addr 2 Data Addr 6 AAH 555H AAAH 55H 2AAH 555H 555H 80H AAAH AAH 555H AAAH 55H 2AAH 555H 10H BA 555H 90H AAAH 00H 2AAH 555H 555H AAAH 555H AAAH 2AAH 555H 555H AAAH A0H XXXH PD XXXH AAH XXXH 55H PA 20H Addr 4 Data Addr 4 Data Addr 4 Data Addr 4 Data Addr 3 Data Addr 4 Data Addr 4 AAH 555H AAAH 55H 2AAH 555H A0H 555H AAAH PD AAH 555H AAAH 55H 2AAH 555H 555H 90H AAAH 00H PA AAH 555H AAAH 55H 2AAH 555H 555H 88H AAAH XXXH AAH 555H AAAH 55H 2AAH 555H 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H 555H 1 F0H AAAH 2AAH 555H DA/ 555H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H AAAH DA/ X00H DA/ X00H 1 RD XXXH Cycle Word RA Byte Word Byte Word Byte Word Byte Word Byte Word Byte 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle
ECH DA/ X01H DA/ X02H
(See Table 6) BA / X02H BA/ X04H
(See Table 6) DA / X03H DA/ X06H
(See Table 6)
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Revision 0.0 November 2002
K5A3x40YT(B)C
NOTES:
Preliminary MCP MEMORY
1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data DA : Dual Bank Address (A19 - A20), BA : Block Address (A12 - A20), X = Don't care . 2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 3. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. DQ8 - DQ15 are don't care in command sequence, except for RD and PD. 7. A11 - A20 are also don't care, except for the case of special notice.
Table 6. Flash Memory Autoselect Codes
DQ8 to DQ15 Description BYTEF = VIH Manufacturer ID Device Code K5A3240YT (Top Boot Block) Device Code K5A3240YB (Bottom Boot Block) Device Code K5A3340YT (Top Boot Block) Device Code K5A3340YB (Bottom Boot Block) Block Protection Verification X 22H 22H 22H 22H X BYTEF = VIL X X X X X X ECH A0H A2H A1H A3H 01H (Protected), 00H (Unprotected) 80H (Factory locked), 00H (Not factory locked) DQ7 to DQ0
Secode Block Indicator Bit (DQ7)
X
X
Table 7. Flash Memory Operation Table
Operation word Read byte Stand-by Output Disable Reset word Write byte Enable Block Group Protect (3) Enable Block Group Unprotect (3) Temporary Block Group L L L X H H H X L L L X L X X X L/H (4) (4) L VccF 0.3V L X L L X H X H H X H X L L X X X H (4) A9 X X X A6 L H X A1 H H X A0 L L X A-1 X X X High-Z X X X DIN DIN DIN X H VID VID VID (2) L/H L/H CEF L OE L WE H BYTEF H L/H A9 X X X A9 A6 X X X A6 A1 X X X A1 A0 X X X A0 A-1 High-Z High-Z High-Z DIN High-Z High-Z High-Z High-Z DIN DOUT High-Z High-Z High-Z DIN H (2) H L H WP/ ACC A9 A9 A6 A6 A1 A1 A0 A0 DQ15/ A-1 DQ15 DQ8/ DQ14 DOUT DQ0/ DQ7 DOUT RESET H
NOTES: 1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET ball are asserted at VccF0.3 V or Vss0.3 V in the Stand-by mode. 3. Addresses must be composed of the Block address (A12 - A20). The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection". 4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected.
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Table 8. SRAM Operation Table 1. Word Mode
CS1S H X X L L L L L L L L CS2S X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L BYTES X X X VccS VccS VccS VccS VccS VccS VccS VccS SA X X X X X X X X X X X LB X X H L X L H L L H L UB X X H X L H L L H L L D/Q0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din D/Q8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Preliminary MCP MEMORY
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
NOTE: X means dont care. (Must be low or high state)
2. Byte Mode
CS1S H X L L L CS2S X L H H H OE X X H L X WE X X H H L BYTES X X VSS VSS VSS SA X X SA1) SA1) SA1) LB X X DNU DNU DNU UB X X DNU DNU DNU D/Q0~7 High-Z High-Z High-Z Dout Din D/Q8~15 High-Z High-Z DNU DNU DNU Mode Deselected Deselected Output Disabled Lower Byte Read Lower Byte Write Power Standby Standby Active Active Active
NOTE: X means dont care. (Must be low or high state)
DNU = Do Not Use 1) Address input for byte operation.
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Flash DEVICE OPERATION Byte/Word Mode
Preliminary MCP MEMORY
If the BYTEF ball is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTEF ball is set at logical "0" , the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 ball is used as an input for the LSB (A-1) address ball.
Read Mode
Flash memory is controlled by Chip Enable (CEF), Output Enable (OE) and Write Enable (WE). When CEF and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CEF or OE is high.
Standby Mode
Flash memory features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CEF high (CEF = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output balls are in high impedance state.
Automatic Sleep Mode
Flash memory features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5A of current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time.
tAA + 50ns
Address
Outputs
Data
Data
Data
Data
Data Auto Sleep Mode
Data
Figure 2. Auto Sleep Mode Operation Autoselect Mode
Flash memory offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. The manufacturer and device code can be read via the command register. The Command Sequence is shown in Table 5 and Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.
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Preliminary MCP MEMORY
WE
A20A0(x16)/* A20A-1(x8) DQ15DQ0
555H/ AAAH
2AAH/ 555H
555H/ AAAH
00H/ 00H
01H/ 02H 22A0H or 22A2H
AAH
55H
90H
ECH
F0H
Manufacturer Code
Device Code (K5A3240Y)
Return to Read Mode
NOTE: The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code.
Figure 3. Autoselect Operation Write (Program/Erase) Mode
Flash memory executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CEF and WE must be low and OE must be high. Addresses are latched on the falling edge of CEF or WE (whichever occurs last) and the data are latched on the rising edge of CEF or WE (whichever occurs first). The device uses standard microprocessor write timing.
Program
Flash memory can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location.
WE A20A0(x16)/ A20A-1(x8) DQ15-DQ0 RY/BY
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH A0H
Program Address Program Data Program Start
Figure 4. Program Command Sequence
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Unlock Bypass
Preliminary MCP MEMORY
Flash memory provides the unlock bypass mode to save its program time. The mode is invoked by the unlock bypass command sequence. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode
Chip Erase
To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CEF pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A20A0(x16)/ A20A-1(x8) DQ15-DQ0
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 80H
555H AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 10H Chip Erase Start
RY/BY
Figure 5. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CEF, while the Block Erase command is latched on the rising edge of WE or CEF. Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Fig 6. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command.
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WE
Preliminary MCP MEMORY
A20A0(x16)/ A20A-1(x8) DQ15-DQ0
555H/ AAAH AAH
2AAH/ 555H 55H
555H/ AAAH 80H
555H/ AAAH AAH
2AAH/ 555H 55H
Block Address 30H Block Erase Start
RY/BY
Figure 6. Block Erase Command Sequence Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20 us to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.
WE
A20A0(x16)/ A20A-1(x8) DQ15-DQ0
555H/ AAAH AAH
Block Address 30H
XXXH
XXXH
B0H
30H
Block Erase Command Sequence
Block Erase Start
Erase Suspend
Erase Resume
Figure 7. Erase Suspend/Resume Command Sequence
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Read While Write
Preliminary MCP MEMORY
Flash memory provides dual bank memory architecture that divides the memory array into two banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-Program operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.
Block Group Protection & Unprotection
Flash memory feature hardware block group protection. This feature will disable both program and erase operations in any combination of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group protection feature is enabled using programming equipment at the user's site. The device is shipped with all block groups unprotected. This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect operation is executing. The block protection and unprotection can be implemented by the following method.
Table 9. Block Group Protection & Unprotection
Operation Block Group Protect Block Group Unprotect CEF L L OE H H WE L L BYTEF X X A9 X X A6 L H A1 H H A0 L L DQ15/ A-1 X X DQ8/ DQ14 X X DQ0/ DQ7 DIN DIN RESET VID VID
Address must be inputted to the block group address (A12~A20) during block group protection operation. Please refer to Figure 9 (Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operation.
Temporary Block Group Unprotect
The protected blocks of the Flash memory can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET ball. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the RESET ball goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC ball is asserted at VIL , the two outermost boot blocks remain protected.
VID V = VIH or VIL
RESET CEF WE
Program & Erase operation at Protected Block
Figure 8. Temporary Block Group Unprotect Sequence
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START COUNT = 1 RESET=VID Wait 1s
Preliminary MCP MEMORY
First Write Cycle=60h? Yes Yes Block Group Protection ? No No
No
Temporary Block Group Unprotect Mode
Block Protect Algorithm
Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 150s Verify Block Group Protect:Write 40H to Block Group address with A6=0, A1=1,A0=0 Read from Block Group address with A6=0, A1=1,A0=0 No COUNT =25? No
All Block Groups Protected ?
Yes
Block Unprotect Algorithm
Block Group , i= 0 Block Group Unprotect Write 60H with A6=1,A1=1 A0=0 Wait 15ms
Reset COUNT=1 Increment COUNT
Increment COUNT
Verify Block Group Unprotect:Write 40H to Block Group address with A6=1, A1=1,A0=0 Read from Block Group address with A6=1, A1=1,A0=0
No COUNT =1000? No
Set up next Block Group address
Data=01h?
Data=00h?
Yes Yes Device failed Protect another Block Group? No Remove VID from RESET Write RESET command END
Yes Yes Device failed Yes Yes Remove VID from RESET Write RESET command END Last Block Group verified ? No
NOTE: All blocks must be protected before unprotect operation is executing.
Figure 9. Block Group Protection & Unprotection Algorithms
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Table 10. Flash Memory Block Group Address (Top Boot Block)
Block Address Block Group A20 BGA0 0 A19 0 A18 0 A17 0 A16 0 0 BGA1 0 0 0 0 1 1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 BGA8 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 BGA15 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X 0 BGA16 1 1 1 1 0 1 BGA17 BGA18 BGA19 BGA20 BGA21 BGA22 BGA23 BGA24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 X A13 X
Preliminary MCP MEMORY
Block A12 X BA0
X
BA1 to BA3
X X X X X X X X X X X X X X
BA4 to BA7 BA8 to BA11 BA12 to BA15 BA16 to BA19 BA20 to BA23 BA24 to BA27 BA28 to BA31 BA32 to BA35 BA36 to BA39 BA40 to BA43 BA44 to BA47 BA48 to BA51 BA52 to BA55 BA56 to BA59
X
BA60 to BA62
0 1 0 1 0 1 0 1
BA63 BA64 BA65 BA66 BA67 BA68 BA69 BA70
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Table 11. Flash Memory Block Group Address (Bottom Boot Block)
Block Address Block Group A20 BGA0 BGA1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 0 BGA8 0 0 0 0 1 1 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 BGA15 BGA16 BGA17 BGA18 BGA19 BGA20 BGA21 BGA22 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X 0 BGA23 1 1 1 1 0 1 BGA24 1 1 1 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1
Preliminary MCP MEMORY
Block A12 0 1 0 1 0 1 0 1 BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7
X
BA8 to BA10
X X X X X X X X X X X X X X
BA11 to BA14 BA15 to BA18 BA19 to BA22 BA23 to BA26 BA27 to BA30 BA31 to BA34 BA35 to BA38 BA39 to BA42 BA43 to BA46 BA47 to BA50 BA51 to BA54 BA55 to BA58 BA59 to BA62 BA63 to BA66
X
BA67 to BA69
X
BA70
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Write Protect (WP)
Preliminary MCP MEMORY
The WP/ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC ball is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group protection/Unprotection". The write protected blocks can only be read. This is useful method to preserve an important program data. The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (K5A3240YT/K5A3340YT : BA69 and BA70, K5A3240YB/K5A3340YB : BA0 and BA1) When the WP/ACC ball is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected or unprotected using the method described in "Block Group protection/unprotection". Recommend that the WP/ACC ball must not be in the state of floating or unconnected, or the device may be led to malfunction.
Secode(Security Code) Block Region
The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block. The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 5). After the system has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same addresses of the boot blocks (8KBx8). The K5A3240YT/K5A3340YT occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to 1FFFFFH) and the K5A3240YB/K5A3340YB type occupies the address of the byte mode 000000H to 00FFFFH (word mode 000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode.
Accelerated Program Operation
Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC ball. When the WP/ ACC ball is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC ball returns the device to normal operation. Recommend that the WP/ACC ball must not be asserted at VHH except accelerated program operation, or the device may be damaged. In addition, the WP/ACC ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunction.
Software Reset
The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state.
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Hardware Reset
Preliminary MCP MEMORY
Flash memory offers a reset feature by driving the RESET ball to VIL. The RESET ball must be kept low (VIL) for at least 500ns. When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output balls are tri-stated for the duration of the RESET pulse. The RESET ball may be tied to the system reset ball. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory.
Power-up Protection
To avoid initiation of a write cycle during VccF Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode.
Low VccF Write Inhibit
To avoid initiation of a write cycle during VccF power-up and power-down, a write cycle is locked out for VccF less than 1.8V. If VccF < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the VccF level is greater than VLKO. It is the users responsibility to ensure that the control balls are logically correct to prevent unintentional writes when VccF is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CEF, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CEF = VIH or WE = VIH. To initiate a write, CEF and WE must be "0", while OE is "1".
Commom Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.
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Table 12. Common Flash Memory Interface Code
Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH
Preliminary MCP MEMORY
Addresses (Byte Mode) 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H
Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H 0036H 0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0016H 0002H 0000H 0000H 0000H 0002H 0007H 0000H 0020H 0000H 003EH 0000H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp Min. voltage(00H = no Vpp pin present) Vpp Max. voltage(00H = no Vpp pin present) Typical timeout per single byte/word write 2 us Typical timeout for Min. size buffer write 2N us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms(00H = not supported) Max. timeout for byte/word write 2 times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2 times typical Max. timeout for full chip erase 2 times typical(00H = not supported) Device Size = 2 byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device
N N N N N
Erase Block Region 1 Information
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Table 12. Common Flash Memory Interface Code
Description Addresses (Word Mode) 40H 41H 42H 43H 44H 45H
Preliminary MCP MEMORY
Addresses (Byte Mode) 80H 82H 84H 86H 88H 8AH
Data 0050H 0052H 0049H 0033H 0033H 0000H
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 0 = Not Supported, 1 = Number of blocks in per group Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 04=K8D1x16U mode Simultaneous Operation (1) 00 = Not Supported, XX = Number of Blocks in Bank2 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Top/Bottom Boot Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device
NOTE: 1. The number of blocks in Bank2 is device dependent. K5A3240Y(8Mb/24Mb) = 30h (48blocks) K5A3340Y(16Mb/16Mb) = 20h (32blocks)
46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH
8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH
0002H 0001H 0001H 0004H 00XXH 0000H 0000H 0085H 00C5H 000XH
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K5A3x40YT(B)C
DEVICE STATUS FLAGS
Preliminary MCP MEMORY
Flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ balls or the RY/ BY ball. The corresponding DQ balls are DQ7, DQ6, DQ5, DQ3 and DQ2. The status is as follows :
Table 13. Hardware Sequence Flags
Status
Programming Block Erase or Chip Erase Erase Suspend Read In Progress Erase Suspend Read Erase Suspend Program Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block
DQ7
DQ7 0 1 Data DQ7 DQ7 0 DQ7
DQ6
Toggle Toggle 1 Data Toggle Toggle Toggle Toggle
DQ5
0 0 0 Data 0 1 1 1
DQ3
0 1 0 Data 0 0 1 0
DQ2
1 Toggle Toggle (Note 1) Data 1 No Toggle (Note 2) No Toggle
RY/BY
0 0 1 1 0 0 0 0
NOTES: 1. DQ2 will toggle when the device performs successive read operations from the erase suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the Erase Suspend Mode, the status can be detected via the DQ7 ball. If the system tries to read an address which belongs to a block that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode, an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs to a block that is not being erased, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
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K5A3x40YT(B)C
DQ3 : Block Erase Timer
Preliminary MCP MEMORY
The status of the multi-block erase operation can be detected via the DQ3 ball. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation from the program operation.
RY/BY : Ready/Busy
Flash memory has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY ball is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If Flash memory is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. The ball is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation.
Rp VccF
Rp =
Ready / Busy open drain output
VccF (Max.) - VOL (Max.) IOL +
2.9V = 2.1mA + IL
IL
where IL is the sum of the input currents of all devices tied to the Ready / Busy ball.
Vss Device
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K5A3x40YT(B)C
Preliminary MCP MEMORY
Start
Start
Yes
DQ7 = Data ?
No
No
DQ6 = Toggle ?
Yes
No
DQ5 = 1 ?
No
DQ5 = 1 ?
Yes Yes
Yes No
DQ7 = Data ?
DQ6 = Toggle ?
No
Yes
Fail
Pass
Fail
Pass
Figure 10. Data Polling Algorithms
Figure 11. Toggle Bit Algorithms
Start
RESET=VID (Note 1)
Perform Erase or Program Operations
RESET=VIH
Temporary Block Unprotect Completed (Note 2)
Figure 12. Temporary Block Group Unprotect Routine
NOTES: 1. All protected block groups are unprotected. ( If WP/ACC = VIL , the two outermost boot blocks remain protected ) 2. All previously protected block groups are protected once again.
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K5A3x40YT(B)C
ABSOLUTE MAXIMUM RATINGS
Parameter Vcc Voltage on any ball relative to Vss RESET WP/ACC All Other Balls Temperature Under Bias Storage Temperature Operating Temperature Tbias Tstg TA VIN Symbol VccF , VccS Rating -0.3 to +3.6 -0.3 to +12.5 -0.3 to +12.5
Preliminary MCP MEMORY
Unit
V
-0.3 to Vcc+0.3V(Max.3.6V) -40 to +125 -65 to +150 -40 to +85 C C C
NOTES: 1. Minimum DC voltage is -0.3V on Input/ Output balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output balls is Vcc+0.3V(Max. 3.6V) which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2. Minimum DC voltage is -0.3V on RESET and WP/ACC balls. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on RESETandWP/ACC balls are 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to Vss)
Parameter Supply Voltage Supply Voltage Symbol VccF , VccS Vss Min 2.7 0 Typ. 3.0 0 Max 3.3 0 Unit V V
DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Common Input Low Level Input High Level Output Low Level Output High Level RESET Input Leakage Current WP/ACC Input Leakage Current Active Read Current (1) Active Write Current (2) Read While Program Current (3) Read While Erase Current (3) Flash Program While Erase Suspend Current ACC Accelerated Program Current ICC2 ICC3 ICC4 ICC5 IACC Symbol ILI ILO VIL VIH VOL VOH ILIT ILIW ICC1 IOL= 2.1mA, Vcc = Vccmin IOH= -1.0mA, Vcc = Vccmin VccF=Vccmax, RESET=12.5V VccF=Vccmax, WP/ACC=12.5V CEF=VIL, OE=VIH CEF=VIL, OE=VIH CEF=VIL, OE=VIH CEF=VIL, OE=VIH CEF=VIL, OE=VIH CEF=VIL, OE=VIH
ACC Ball VccF Ball
Test Conditions VIN=Vss to Vcc, Vcc=Vccmax VOUT=Vss to Vcc, Vcc=Vccmax, OE=VIH
Min -1.0 -1.0 -0.3 2.2 2.3 -
Typ 14 3 15 25 25 15 5 15
Max +1.0 +1.0 0.5 Vcc +0.3 0.4 35 35 20 6 30 50 50 35 10 30
Unit A A V V V V A A mA mA mA mA mA mA
5MHz 1MHz
VccF=Vccmax, CEF=VccF 0.3V, Standby Current ISB1 WP/ACC=VccF 0.3V or Vss 0.3V Standby Curren During Reset ISB2 VccF=VccFmax, RESET=Vss0.3V, WP/ACC=VccF 0.3V or Vss 0.3V 5 18 A RESET=VccF 0.3V, 5 18 A
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K5A3x40YT(B)C
DC CHARACTERISTICS(Continued)
Parameter Automatic Sleep Mode Voltage for WP/ACC Block Temporarily Unprotect and Flash Program Acceleration (4) Voltage for Autoselect and Block Protect (4) Low VccF Lock-out Voltage (5) Symbol ISB3 VHH Test Conditions VIH=VccF0.3V, VIL=VSS0.3V, OE=VIL, IOL=IOH=0 VccF = 3.0V 0.3V VccF = 3.0V 0.3V
Preliminary MCP MEMORY
Min 8.5 Typ 5 Max 18 12.5 Unit A V
VID VLKO
8.5 1.8
-
12.5 2.5
V V
ICC1 Operating Current SRAM ICC2
Cycle time=1s, 100% duty, CS1S0.2, CS2SVccS-0.2V, LB0.2V and/or UB0.2V All outputs open, VIN0.2V or VINVccS-0.2V, BYTES=VccS 0.3V or Vss 0.3V Cycle time=Min, 100% duty, CS1S=VIL, CS2S=VIH, LB=VIL and/or UB= VIL, All outputs open, VIN=VIL or VIH, BYTES=VccS 0.3V or Vss 0.3V CS1SVccS-0.2V, CS2SVccS-0.2V (CS1S controlled) or CS2S0.2V (CS2S controlled),
-
-
3
mA
-
20
27
mA
Standby Current
ISB
BYTES=VccS 0.3V or Vss 0.3V, Other input =0~VccS
-
0.5
10
A
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). The read current is typically 14 mA (@ VccF=3.0V , OE at VIH.) 2. ICC active during Internal Routine(program or erase) is in progress. 3. ICC active during Read while Write is in progress. 4. The high voltage ( VHH or VID ) must be used in the range of VccF = 3.0V 0.3V 5. Not 100% tested. 6. Typical values are measured at VccF = VccS = 3.0V, Ta=25C , not 100% tested.
CAPACITANCE(TA = 25 C, VccF = VccS = 3.3V, f = 1.0MHz)
Item Input Capacitance Output Capacitance Control Ball Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 18 20 18 Unit pF pF pF
NOTE: Capacitance is periodically sampled and not 100% tested.
AC TEST CONDITION
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to Vcc 5ns Vcc/2 CL = 30pF
Vcc Vcc/2 0V
Input & Output Test Point
Device Vcc/2 CL
* CL= 30pF including Scope and Jig Capacitance
Input Pulse and Test Point
Output Load
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K5A3x40YT(B)C
Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write
Parameter Write Cycle Time (1) Address Setup Time Symbol tWC tAS tASO tAH tAHT tDS tDH tOES tOEH1 tOEH2 tCS tCH tWP tWPH Word Byte Word Byte tPGM 70ns Min 70 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 -
Preliminary MCP MEMORY
80ns Max Min 80 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec s ns ns s ns ns ns s s ns ns ns ns ns
Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time CEF Setup Time CEF Hold Time Write Pulse Width Write Pulse Width High Programming Operation Read (1) Toggle and Data Polling (1)
Accelerated Programming Operation Block Erase Operation (2) VccF Set Up Time Write Recovery Time from RY/BY RESET High Time Before Read RESET to Power Down Time Program/Erase Valid to RY/BY Delay VID Rising and Falling Time RESET Pulse Width RESET Low to RY/BY High
tACCPGM tBERS tVCS tRB tRH tRPD tBUSY tVID tRP tRRB tRSP tRSTS tRSTW tGHWL tCEPH tOEPH
RESET Setup Time for Temporary Unprotect RESET Low Setup Time RESET High to Address Valid Read Recovery Time Before Write CE High during toggling bit polling OE High during toggling bit polling
NOTES: 1. Not 100% tested. 2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
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K5A3x40YT(B)C
Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CEFControlled Writes
Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time WE Setup Time WE Hold Time CEF Pulse Width CEF Pulse Width High Programming Operation Word Byte Word Byte Read (1) Toggle and Data Polling (1) Symbol tWC tAS tAH tDS tDH tOES tOEH1 tOEH2 tWS tWH tCP tCPH tPGM 70ns Min 70 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 Max -
Preliminary MCP MEMORY
80ns Min 80 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec ns
Accelerated Programming Operation Block Erase Operation (2) BYTE Switching Low to Output HIGH-Z
tACCPGM tBERS tFLQZ
NOTES: 1. Not 100% tested. 2.This does not include the preprogramming time.
ERASE AND PROGRAM PERFORMANCE
Parameter Block Erase Time Chip Erase Time Word Programming Time Byte Programming Time Accelerated Byte/Word Program Time Chip Programming Time Erase/Program Endurance Word Mode Byte Mode Word Mode Byte Mode Limits Min 100,000 Typ 0.7 49 14 9 9 7 28 36 Max 15 330 210 210 150 84 108 Unit sec sec s s s s sec sec cycles Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Minimum 100,000 cycles guaranteed Comments Excludes 00H programming prior to erasure
NOTES: 1. 25 C, VccF = 3.0V 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Read Operations
tRC
Preliminary MCP MEMORY
Address
tAA
Address Stable
CEF
tOE tDF
OE
tOEH1
WE
tCE tOH
Outputs
HIGH-Z
Output Valid
HIGH-Z
RY/BY
HIGH
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CEF & OE Disable Time (1) Output Hold Time from Address, CEF or OE OE Hold Time
NOTE: 1. Not 100% tested.
Symbol tRC tAA tCE tOE tDF tOH tOEH1
70ns Min 70 0 0 Max 70 70 25 16 Min 80 0 0
80ns Max 80 80 25 16 -
Unit ns ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Hardware Reset/Read Operations
Preliminary MCP MEMORY
tRC
Address
tAA
Address Stable
CEF
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address, CEF or OE RESET Pulse Width RESET High Time Before Read
Symbol tRC tAA tCE tOH tRP tRH
70ns Min 70 0 500 50 Max 70 70 Min 80 0 500 50
80ns Max 80 80 -
Unit ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Alternate WE Controlled Program Operations
tAS
Preliminary MCP MEMORY
Data Polling
PA tAH PA tRC
Address
555H
CEF
tOES
OE
tWC tCH tWP tPGM
WE
tWPH tCS tDH A0H tDS PD tBUSY Status DOUT tRB tCE tOH tOE tDF
DATA
RY/BY
NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence.
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CEF Setup Time CEF Hold Time OE Setup Time Write Pulse Width Write Pulse Width High Programming Operation Word Byte Word Byte
Symbol tWC tAS tAH tDS tDH tCS tCH tOES tWP tWPH tPGM
70ns Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 70 0 90 0 70 25 16 80 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25
80ns Max -
Unit ns ns ns ns ns ns ns ns ns ns us us s s
14(typ.) 9(typ.) 9(typ.) 7(typ.) 80 25 16 -
Accelerated Programming Operation Read Cycle Time Chip Enable Access Time Output Enable Time CEF & OE Disable Time Output Hold Time from Address, CEF or OE Program/Erase Valide to RY/BY Delay Recovery Time from RY/BY
tACCPGM tRC tCE tOE tDF tOH tBUSY tRB
ns ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Alternate CEF Controlled Program Operations
tAS
Preliminary MCP MEMORY
Data Polling
PA tAH PA
Address
555H
WE
tOES
OE
tWC tCP tPGM
CEF
tWS tDH A0H tDS
tCPH
DATA
PD
Status
DOUT
tBUSY
tRB
RY/BY
NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence.
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time WE Setup Time WE Hold Time CEF Pulse Width CEF Pulse Width High Programming Operation Word Byte Word Byte
Symbol tWC tAS tAH tDS tDH tOES tWS tWH tCP tCPH tPGM
70ns Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 90 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25
80ns Max -
Unit ns ns ns ns ns ns ns ns ns ns s s s s
14(typ.) 9(typ.) 9(typ.) 7(typ.) -
Accelerated Programming Operation Program/Erase Valide to RY/BY Delay Recovery Time from RY/BY
tACCPGM tBUSY tRB
ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Word to Byte Timing Diagram for Read Operation
CEF OE
tCE
Preliminary MCP MEMORY
BYTE
tELFL
DQ0-DQ7 DQ8-DQ14 DQ15/A-1
Data Output (DQ8-DQ14) Data Output (DQ15) tFLQZ
Data Output (DQ0-DQ7)
Address Input (A-1)
Byte to Word Timing Diagram for Read Operation
CEF OE
tCE
BYTE
tELFH Data Output (DQ0-DQ7) Data Output (DQ8-DQ14) Address Input (A-1) tFHQV Data Output (DQ15)
DQ0-DQ7 DQ8-DQ14 DQ15/A-1
BYTE Timing Diagram for Write Operation
CEF
The falling edge of the last WE signal
WE BYTE
tSET (tAS) tHOLD(tAH)
Parameter Chip Enable Access Time CEF to BYTE Switching Low or High BYTE Switching Low to Output HIGH-Z BYTE Switching High to Output Active
Symbol tCE tELFL/tELFH tFLQZ tFHQV
70ns Min Max 70 5 25 25 Min -
80ns Max 80 5 25 25
Unit ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Chip/Block Erase Operations
tAS
Preliminary MCP MEMORY
555H for Chip Erase 2AAH
tAH
Address
555H
555H
555H
2AAH
BA
tRC
CEF
tOES
OE
tWP
tWC
WE
tCS
tWPH tDH
10H for Chip Erase 55H 80H AAH 55H 30H
DATA
AAH
tDS
RY/BY
VccF
tVCS
NOTE: BA : Block Address
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time CEF Setup Time Write Pulse Width Write Pulse Width High Read Cycle Time VccF Set Up Time
Symbol tWC tAS tAH tDS tDH tOES tCS tWP tWPH tRC tVCS
70ns Min 70 0 45 35 0 0 0 35 25 70 50 Max Min 80 0 45 35 0 0 0 35 25 80 50
80ns Max -
Unit ns ns ns ns ns ns ns ns ns ns s
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Read While Write Operations
Read tRC Command tWC DA2 (555H) tAS tAH tAA tCE Read tRC DA1 Command tWC DA2 (PA) Read tRC DA1
Preliminary MCP MEMORY
Read tRC DA2 (PA) tAS tAHT
Address
DA1
CEF
tOE
tCEPH
OE
tOES tWP tDF tOEH2
WE
tDH
tDS
tDF
DQ
Valid Output
Valid Input (A0H)
Valid Output
Valid Input (PD)
Valid Output
Status
NOTE: This is an example in the program-case of the Read While Write function. DA1 : Address of Bank1, DA2 : Address of Bank 2 PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
Parameter Write Cycle Time Write Pulse Width Write Pulse Width High Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE Setup Time OE Hold Time CEF & OE Disable Time Address Hold Time CEF High during toggle bit polling
Symbol tWC tWP tWPH tAS tAH tDS tDH tRC tCE tAA tOE tOES tOEH2 tDF tAHT tCEPH
70ns Min 70 35 25 0 45 35 0 70 0 10 0 20 Max 70 70 25 16 Min 80 35 25 0 45 35 0 80 0 10 0 20
80ns Max 80 80 25 16 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Data Polling During Internal Routine Operation
CEF
tOE
Preliminary MCP MEMORY
tDF
OE
tOEH2
WE
tCE tOH
DQ7
Data In
tPGM or tBERS
DQ7
*DQ7 = Valid Data
HIGH-Z
DQ0-DQ6
Data In
Status Data
Valid Data
HIGH-Z
NOTE: *DQ7=Vaild Data (The device has completed the internal operation).
RY/BY Timing Diagram During Program/Erase Operation
CEF
The rising edge of the last WE signal
WE
Entire progrming or erase operation
RY/BY
tBUSY
Parameter Program/Erase Valid to RY/BY Delay Chip Enable Access Time Output Enable Time CEF & OE Disable Time Output Hold Time from Address, CEF or OE OE Hold Time
Symbol tBUSY tCE tOE tDF tOH tOEH2
70ns Min 90 0 10 Max 70 25 16 Min 90 0 10
80ns Max 80 25 16 -
Unit ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation
tAHT Address* tASO CEF tOEH2 WE tOEPH OE tDH DQ6/DQ2 Data In Status Data tCEPH tAHT tAS
Preliminary MCP MEMORY
tOE
Status Data Status Data Array Data Out
RY/BY
NOTE: Address for the write operation must include a bank address (A19~A20) where the data is written.
Enter Embedded Erasing
Erase Suspend Erase Erase Suspend Read
Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read
Erase Resume Erase Erase Complete
WE
DQ6
DQ2
Toggle DQ2 and DQ6 with OE or CEF NOTE: DQ2 is read from the erase-suspended block.
Parameter Output Enable Access Time OE Hold Time Address Hold Time Address Setup Address Setup Time Data Hold Time CEF High during toggle bit polling OE High during toggle bit polling
Symbol tOE tOEH2 tAHT tASO tAS tDH tCEPH tOEPH
70ns Min 10 0 55 0 0 20 20 Max 25 Min 10 0 55 0 0 20 20
80ns Max 25 -
Unit ns ns ns ns ns ns ns ns
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K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS RESET Timing Diagram
RY/BY
High
Preliminary MCP MEMORY
CEF or OE
tRH
RESET
tRP
tREADY Reset Timings NOT during Internal Routine tREADY
RY/BY
tRB
CEF or OE
tRP
RESET
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
tRSTS
RESET VccF
Address
DATA
tAA
Parameter RESET Pulse Width RESET Low to Valid Data (During Internal Routine) RESET Low to Valid Data (Not during Internal Routine) RESET High Time Before Read RY/BY Recovery Time RESET High to Address Valid RESET Low Set-up Time
Symbol tRP tREADY tREADY tRH tRB tRSTW tRSTS
70ns Min 500 50 0 200 500 Max 20 500 Min 500 50 0 200 500
80ns Max 20 500 -
Unit ns s ns ns ns ns ns
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Revision 0.0 November 2002
K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations
VID
Preliminary MCP MEMORY
RESET
Vss,VIL, or VIH
Vss,VIL, or VIH
BGA,A6 A1,A0
Valid Block Group Protect / Unprotect
Valid Verify 40H
Block Group Protect:150s Block Group UnProtect:15ms
Valid
DATA
60H
60H
Status*
1s CEF
WE
tRB
OE
tBUSY
RY/BY
NOTES: Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H BGA = Block Group Address (A12 ~ A20)
Temporary Block Group Unprotect
VID RESET Vss,VIL, or VIH
Vss,VIL, or VIH
CEF
WE
Program or Erase Command Sequence
tVID
tRSP
tRRB
tVID
RY/BY
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Revision 0.0 November 2002
K5A3x40YT(B)C
SRAM AC CHARACTERISTICS
Parameter List Read cycle time Address access time Chip select to output Output enable to valid output UB, LB Access Time Read Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write UB, LB Valid to End of Write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol Min tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 55 10 10 5 0 0 0 10 55 45 0 45 45 40 0 0 20 0 5
Preliminary MCP MEMORY
55ns Max 55 55 25 55 20 20 20 20 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SRAM DATA RETENTION CHARACTERISTICS
Item VccS for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1SVccS-0.2V VccS=3.0V, CS1SVccS-0.2V See data retention waveform Min 1.5 0 tRC Typ 0.5 Max 3.3 10 Unit V A ns
1. CS1SVccS-0.2V, CS2SVccS-0.2V(CS1S controlled) or CS2S0.2V(CS2S controlled) 2. Typical values are measured at Vcc=3.0V, Ta=25C , not 100% tested.
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Revision 0.0 November 2002
K5A3x40YT(B)C
SRAM TIMING DIAGRAMS
Preliminary MCP MEMORY
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1S=OE=VIL, CS2S=WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 tOH
CS1S
CS2S
tCO2 tHZ tBA tBHZ
UB, LB
OE tOLZ tBLZ tLZ
tOE tOHZ Data Valid
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 0.0 November 2002
K5A3x40YT(B)C
SRAM TIMING DIAGRAMS
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1S tAW CS2S tCW(2) tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tDH tWR(4)
Preliminary MCP MEMORY
UB, LB
High-Z tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1S Controlled)
tWC Address tAS(3) CS1S tAW CS2S tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 0.0 November 2002
K5A3x40YT(B)C
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS1S tAW CS2S UB, LB tCW(2) tBW tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
Preliminary MCP MEMORY
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS1S and low WE. A write begins when CS1S goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1S going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1S or WE going high.
SRAM DATA RETENTION WAVE FORM
CS1S controlled
VccS 2.7V tSDR Data Retention Mode tRDR
2.2V VDR CS1SVccS - 0.2V
CS1S Vss
CS2S controlled
VccS 2.7V CS2S tSDR
Data Retention Mode
tRDR
VDR 0.4V Vss CS2S0.2V
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Revision 0.0 November 2002
K5A3x40YT(B)C
PACKAGE DIMENSION 69-Ball Tape Ball Grid Array Package (measured in millimeters)
Preliminary MCP MEMORY
Top View
Bottom View
8.000.10 8.000.10 (Datum A) 10 9 0.80 A #A1 (Datum B) 11.000.10 8 0.80 x9=7.20
A B
7
6
5
4
3
2
1
C D E F G
0.80
B
3.60
H J K
3.60 69- 0.450.05
0.20 M A B
Side View
0.320.05 1.100.10 0.450.05
0.08MAX
11.000.10
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Revision 0.0 November 2002
0.80x9=7.20
11.000.10

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