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SUMMIT
MICROELECTRONICS, Inc.
S9418
Quad 8-Bit Nonvolatile DACPOTTM Electronic Potentiometer With a Mute Control Input
FEATURES * Four 8-Bit DACS -- Differential Non-linearity - 0.5LSB max -- Integral Non-Linearity Error - 1LSB max * Each DAC has Independent Reference Inputs -- Output Buffer Amplifiers Swing Rail-to-Rail -- Ground to VDD Reference Input Range * Each DAC's Digital Inputs Maintained in EEPROM * Power-On Reset Reloads Registers with Nonvolatile Data * Simple Serial Interface for Reading and Writing DAC values, SPITM and QSPITM compatible. * Fully operational from 2.7V to 5.5V * Low Power, 4mW max at +5V
OVERVIEW The S9418 DACPOTTM is a serial input, voltage output, quad 8-bit digital to analog converter. The S9418 operates from a single +2.7V to +5.5V supply. Internal precision buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. The S9418 integrates four 8-bit DACs and their associated circuits which include; an enhanced unity gain operational amplifier output, an 8-bit data latch, an 8-bit nonvolatile register and an industry standard serial interface for reading and writing data to the DACs' data latches and registers. The DACs are independently programmable and each has its own electrically isolated Vreference inputs.
FUNCTIONAL BLOCK DIAGRAM
Memory Control Programming Memory Controller
8-bit E2PROM
VREFH0 VOUT0
RDY/BSY
Serial Data In
8-bit Data Register
8-bit DAC
AMP
VREFL0 DAC Section 0 Serial Data Out VREFH1 VOUT1 VREFL1
CS DI CLK MUTE VDD GND
Control Logic
DAC Section 1
DAC Section 2
VREFH2 VOUT2 VREFL2 VREFH3 VOUT3 VREFL3 DO
2023 ILL2 1.2
DAC Section 3
SUMMIT MICROELECTRONICS, Inc.
*
300 Orchard City Drive, Suite 131
*
Campbell, CA 95008
*
Telephone 408-378-6461
*
Fax 408-378-6586
*
www.summitmicro.com
(c) SUMMIT MICROELECTRONICS, Inc. 1999 2023 1.5 4/24/99
1
Characteristics subject to change without notice
S9418
PINOUT and SIGNAL DEFINITION Pin Name Function Vreference High: VREFH VDD > VREFL Power Supply Voltage 1, 2 VREFH 20, 19 VREFH1 VREFH0 VDD RDY/BSY CLK CS DI DO MUTE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VREFH2 VREFH3 VOUT0 VOUT1 VOUT2 VOUT3 VREFL3 VREFL2 VREFL1 VREFL0 7 8 9 10 11, 12 13, 14
2023 ILL1 1.2
3 4
VDD
RDY/BSY Ready/Busy: open drain output indicating status of nonvolatile write operations CLK CS Clock Input Pin: used for serial data communication Chip Select: When high deselects the device and places it in a low power mode Data Input: serial data input pin Data Output: serial data output pin When active forces VOUT to VREFL Power Supply Ground Vreference Low DAC Output: buffered D to A converter output
5 6
DI DO MUTE GND VREFL VOUT
15, 16 17, 18
The analog outputs of the S9418 can be programmed to any one of 256 individual voltage steps. Each step value is 1/256th of the voltage differential between VrefH and VrefL of the respective DAC. Once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. Each DAC can be independently read without affecting the output voltage during the read cycle. In addition each output can be adjusted an unlimited number of times without altering the value stored in the nonvolatile memory. DEVICE OPERATION Analog Section The S9418 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. Reference inputs The voltage differential between the VREFL and VREFH inputs sets the full-scale output voltage for its respective DAC. VREFL must be equal to or greater than ground (positive voltage). VREFH must be greater (more positive) than VREFL or equal to VDD.
2023 1.5 4/24/99
Output Buffer Amplifiers The voltage outputs are from precision unity-gain followers that can slew up to 1V/s. The outputs can swing from VREFL to VREFH. With a 0V to 5V output transition the amplifier outputs typically settle to 1LSB in 50s. DIGITAL INTERFACE The S9418 employs a common 4-wire serial interface. It is comprised of a Clock (CLK), Chip Select (CS) and Data In (DI) input and a Data Out (DO) output. Data is clocked into the device on the clock's rising edge and out of the device on the clock's falling edge. Data is shifted in and out MSB first. DO only becomes active after the device has been selected and after a valid read command and address has been received. All data transfers are initiated after CS goes LOW and a logic `1' is clocked into the device. This first data transfer is the start bit and must precede all operations. Following the start bit are two command bits used to specify which of four commands to execute. The next two bits are the address bits used to select one of the four DACs. The action of the next eight clock cycles will be dependent upon the command issued.
2
S9418
S CH CL AH AL 10 0A A 1 1 1 0 1 1 1 0 1 A A A A A A clocks will output on the DO pin the contents of the selected data register. This read will not affect the contents of the register or the output of the DAC. Refer to Figure 1 for an illustration of the sequence of bus conditions for a read operation. WRITE Write operations are initiated by taking CS LOW and clocking in a start bit followed by the write command and the address of the data register to be written. This action is followed by the host clocking eight bits of data into the register, MSB first. The output of the selected DAC will change as the last bit is clocked into the device. At this point the clock counter will reset the command register, requiring a full sequence to be initiated in order to write to the DAC again. NOTE: This write operation does not affect the contents of the nonvolatile register. Therefore, the nonvolatile register can contain the power-on default settings (e.g. volume), and the write DAC command can be used to make situational adjustments. Refer to Figure 2 for an illustration of the sequence of bus conditions for a write operation.
NV Enable - Data Don't Care Write Command - Data In Read - Data Out Recall -Data Don't Care
2023 PGM T1 1.0
TABLE 1. COMMAND FORMAT
Internally there are four DACs and associated with each are two registers. There is one data register that is used by the DAC to hold the digital value it converts. There is also one nonvolatile register that holds the default value that can be recalled into the data register during powerup or by executing the Recall command. READ Read operations are initiated by taking CS LOW and clocking in a start bit followed by the read command and the address of the data register to be read. The next eight
CS CLK
DI
S T A R T
C1
C0
A1
A0
DO
Hi Z
D7
D6
D5
D4
D3
D2
D1
D0
Hi Z
Pulled Up to VDD
RDY/BSY
2023 ILL3 1.0
FIGURE 1. READ SEQUENCE
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S9418
CS CLK
DI
S T A R T
C1
C0
Hi Z
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DO
Pulled Up to VDD
RDY/BSY VOUT
2023 ILL5 1.0
FIGURE 2. WRITE SEQUENCE
Rising Edge Sets NV Write Enable Latch
Rising Edge Starts NV Write
CS CLK
DI
S T A R T
C1
C0
A1
D0
Address and Data are Don't Care
S T A R T
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Pulled Up to VDD
NV Write Enable Latch is Reset
RDY/BSY
2023 ILL4 1.0
FIGURE 3. NONVOLATILE WRITE SEQUENCE
NONVOLATILE WRITE A nonvolatile write is a two step operation: it is initiated by taking CS LOW and clocking in a start bit followed by the NV Write Enable command. At this point the host can take CS back high or continue clocking in data. This data is don't care and will be ignored by the S9418. Next, the host takes CS LOW again and issues a write command and address and then clocks in the eight data bits to be programmed. The host will then bring CS HIGH
and the data will be latched into the data register and a nonvolatile write operation will commence. The status of the nonvolatile write can be monitored on the RDY/BSY pin. A logic low indicates the write is still in progress and the S9418 will not be accessible to the host; a logic high indicates the write has completed and the S9418 is ready for the next command. Refer to Figure 3 for an illustration of the sequence of bus conditions for a nonvolatile write operation.
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4
S9418
RECALL COMMAND The recall command will retrieve data from the selected nonvolatile register and write it into the data register of the associated DAC. This operation is initiated by taking CS LOW and clocking in a start bit followed by the recall command and the address of the nonvolatile register to be recalled. The eight bits of data are don't care, so CS can be taken high any time after the address bits are clocked in. Refer to Figure 4 for an illustration of the sequence of bus conditions for a Recall operation. Power-On Recall Whenever the S9418 is powered on, the VOUT values will be returned to the analog equivalent of the data byte stored in the nonvolatile register. MUTE Operation The MUTE input is active high. Whenever the input is low, the VOUT will reflect the value in the data register. If MUTE is driven high the VOUT outputs will be switched to VREFL. Releasing the MUTE input returns the VOUT outputs to the analog equivalent of the data register contents.
CS CLK
DI
S T A R T
C1
C0
A1
A0
VOUT
2023 ILL6 1.0
FIGURE 4. RECALL COMMAND SEQUENCE
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S9418
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................... -0.5V to +7V Digital Inputs to Gnd ............................................. -0.5V to VDD+0.5V Analog Inputs to ground ........................................ -0.5V to VDD+0.5V Digital Outputs to Gnd ........................................... -0.5V to VDD+0.5V Analog Outputs to Gnd ......................................... -0.5V to VDD+0.5V Temperature Under Bias ........................................... -55C to +125C Storage Temperature ................................................ -65C to +150C Lead Soldering (10 Sec Max) ................................................... 300C Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS Condition Temperature VDD
Min -40C +2.7V
Max +85C +5.5V
2023 PGM T2 1.1
RELIABILITY CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol VZAP ILTH TDR NEND Parameter ESD Susceptibility Latch-Up Data Retention Endurance Min 2000 100 100 1,000,000 Max Unit V mA Years Stores Test Method MS-883, TM 3015 JEDEC Standard 17 MS-883, TM 1008 MS-883, TM 1033
2023 PGM T3 1.1
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol IDD ISB IIH IIL VIH VIL VOH VOL Parameter Supply Current during store, note 1 Standby Supply Current Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage IOH = -400A IOL=1mA, VDD = +5V IOL= 0.4mA, VDD = +2.7V Conditions CS = VIL CS = VIH VIN = VDD VIN =0V 2 0 VDD-0.3 0.4 0.4 V Min Max 1.8 800 10 -10 VDD 0.8 Units mA A A A V V V V
2023 PGM T4 1.2
Note 1: IDD is the supply current drawn while the EEPROM is being updated
2023 1.5 4/24/99
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S9418
AC ELECTRICAL CHARACTERISTICS VDD = +4.5V to +5.5V, VREFH = VDD, VREFL = 0V, TA = -40C to +85C, unless otherwise specified Symbol fC tWH tWL tCS tCSS tCSH tSU tH tV tHO tDIS tBUSY
Notes:
Parameter Clock Frequency Minimum CLK High Time Minimum CLK Low Time Minimum CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Output Valid Time Data Out Hold Time Output Disable Time Write Cycle Time
Conditions
Min. DC 500 300 150 100 0
Typ.
Max. 1
Units MHz ns ns ns ns ns ns ns
CL = 100pF See Note 1
50 50 150 0 400 3.3 5
ns ns ns ms
2023 PGM T5 1.1
1. All timing measurements are defined at the point of signal crossing VDD/2.
tCS
CS
tCSS
CLK
tWL
tWH tCSH
tSU
DI
tH
tV
Hi Z
tHO
tDIS
Hi Z
DO
RDY/BSY
FIGURE 5. AC TIMING DIAGRAM
2023 ILL7 1.0
2023 1.5 4/24/99
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S9418
DAC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40C to +85C, unless specified otherwise
Symbol Parameter Integral Non-Linearity Differential Non-Linearity VrefH Input Voltage VrefL Input Voltage VrefH to VrefL Resistance Temperature Coefficient of RIN Input Resistance Match Full-Scale Gain Error Output Offset Voltage VOUT Temperature Coefficient Amplifier Output Load Current Amplifier Output Resistance VDD = VrefH Power Supply Rejection ILOAD = 10A +5V +3V +5V +3V D = FF D = 00 VDD = +5V, ILOAD = 50A, Guaranteed but not tested 0 -200 10 20 20 20 90 0.08 1 Conditions ILOAD = 100A, ILOAD = 100A, Guaranteed but not tested Min. VrefL Gnd Typ. 0.5 0.1 38K 600 0.5 Max. 1 0.5 VDD VrefH 1 1 20 50 +1000 Units LSB LSB V V ppm/C % LSB mV V/C A LSB/V s s nV/ % HZ
Accuracy
INL DNL
References VrefH
VrefL RIN TCRIN RIN
Analog Output
GEFS VOUTZS TCVOUT IL ROUT PSRR ts eN THD
DAC Setting Time to 1LSB 10pf 10pf Amplifier Output Noise Total Harmonic Distortion f = 1kHz, VDD = +5V
VREFH = 2.5V VDD = +5V VIN = 1V rms, f = 1kHz VDD = +5V VREFH = +2.5V VIN = 100mV rms
BW
Bandwidth - 3dB
-
300
-
kHz
2023 PGM T6 1.5
2023 1.5 4/24/99
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S9418
20 Pin SOIC (.300) Package
0.496 - 0.512 (12.598 - 13.005)
0.394 - 0.419 (10.007 - 10.643)
0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 (0.254 - 0.737) 0 to 8 typ x45 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143
0.009 - 0.013 (0.229 - 0.330)
0.016 - 0.050 (0.406 - 1.270)
0.050 (1.270) 0.014 - 0.019 (0.356 - 0.482)
20pn SOIC ILL.1
0.004 - 0.012 (0.102 - 0.305)
ORDERING INFORMATION
S9418
S
Base Part Number
Package S = 20 Lead SOIC
2023 ILL8 1.1
2023 1.5 4/24/99
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S9418
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
(c) Copyright 1999 SUMMIT Microelectronics, Inc.
2023 1.5 4/24/99
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