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M52957AFP
Distance Detection Signal Processing for 3V Supply Voltage
REJ03F0069-0100Z Rev.1.0 Sep.19.2003
Description
M52957AFP is a semiconductor integrated circuit containing distance detection signal processing circuit for 3V supply voltage. This device transforms each optical inflow current I1 and I2 from PSD SENSOR into the voltage, and integrates that output after doing calculation corresponds to I1/(I1+I2), and outputs it as the time data(pulse term).
Features
* Wide supply voltage range Vcc=2.2 to 5.5V * Includes clamp level switching circuit (Switch is 16 kinds by outside control) * Includes STANDBY function * Includes POWER ON RESET function
Application
Auto focus control for the CAMERA Sensor for short distance etc
Recommended Operating Condition
Rated supply voltage * * * * * * * * * * * * * * * 3.0V Supply voltage * * * * * * * * * * * * * * * 2.2 to 5.5V
Rev.1.0, Sep.19.2003, page 1 of 13
M52957AFP
Pin Configuration
PSDN CHN Vcc
(TESTN) NC
1 2
16 15
PSDF CHF GND1
(TESTF) NC
M52957AFP
3 4 5 6 7 8
14 13 12 11 10 9
STB CINT RESET SOUT
GND2 CLALV HOLD INT
Outline
Note: pin4,13 is connected only engineering sample
16P2E
Block Diagram
Vcc 3 TESTN CHN 2 PSDN 1
STATIONARY LIGHT REMOVE HOLD HOLD I2 STATIONARY LIGHT REMOVE I/V TRANSFORM AMP I1 I/V TRANSFORM AMP PULSE WIDTH TRANSFORM (DOUBLE INTEGRATION)
NC 4
CINT 6
BIAS
RECKON
I1 I1+I2 REFERENCE VOLTAGE
PSDF 16 CHF 15
CLAMP CIRCUIT
CLAMP LEVEL SWITCHING
13 NC
HOLD
TESTF
SEQUENTIAL CONTROL LOGIC
12 GND1 GND2
Note: pin4,13 is connected only engineering sample
14
11 CLALV
8 STB RESET INT HOLD SOUT
5
7
9
10
Rev.1.0, Sep.19.2003, page 2 of 13
M52957AFP
Absolute Maximum Ratings
(Ta = 25C, unless otherwise noted.)
Parameter Supply voltage Power dissipation Thermal derating Pin supply voltage Another pin supply voltage Output pin inflow current Operating temperature Storage temperature Symbol VCC Pd K VIF VI/O Isout Topr Tstg Ratings 7.0 320 -3.2 7.0 -0.3 to VCC + 0.3 0.5 -10 to 50 -40 to 125 Unit V mW mW/C V V mA C C Remark note 1 Ta=25C Ta25C Pin5, 7, 8, 9, 10, 11 note 2 NPN open collector
Notes : 1. As a principle, do not provide a supply voltage reversely. 2. As a principle, do not provide the terminals with the voltage over supply voltage or under ground voltage.
Rev.1.0, Sep.19.2003, page 3 of 13
M52957AFP
Electrical characteristics
(Ta = 25C, VCC = 5.0V, unless otherwise noted.)
Limits Classification Parameter Operating supply voltage range Usual consuming current While Rapid charge consuming current 1 While Rapid charge consuming current 2 While STAND BY consuming current HOLD "H" input voltage HOLD "L" input current HOLD "H" input current INT pin HOLD "L" input voltage INT "H" input voltage INT "L" input voltage INT "H" input current CLALV pin INT "L" input current CLALV "H" input voltage CLALV "L" input voltage CLALV "H" input current RESET pin CLALV "L" input current RESET "H" input voltage RESET "L" input voltage RESET "H" input current STB pin RESET "L" input current STB "H" input voltage STB "L" input voltage STB "H" input current HOLD C STB "L" input current CH rapid charge current CH stationary charge current CH stationary discharge current Symbol VCC ICC1 ICC2 Min. 2.2 Typ. 3.0 5.9 17.7 Max. 5.5 7.7 23.0 Unit V mA mA While CH rapid charge consuming current While CH and CINT rapid charge consuming current *1 Test conditions Note
Consuming current
ICC3
19.0
24.7
mA
*1
ICC4 VHOH VHOL IHOH IHOL VINH VINL IINH IINL VCLH VCLL ICLH ICLL VREH VREL IREH IREL VSTH VSTL ISTH ISTL ICHQC ICHC ICHD
1.1 0 -100 1.1 0 -100 1.1 0 -100 1.1 0 -100 VCC-0.3 0 -150 -2000 -30 10
-75 -75 -75 -75 -100 -1000 -20 20
1.0 7.0 0.3 1.0 -50 7.0 0.3 1.0 -50 7.0 0.3 1.0 -50 7.0 0.3 1.0 -50 7.0 0.3 3.0 -50 -500 -10 30
A V V A A V V A A V V A A V V A A V V A A A A A VIH=5.5V VIL=0V
*1
HOLD pin
VIH=5.5V VIL=0V
VIH=5.5V VIL=0V
VIH=5.5V VIL=0V
VIH=5.5V VIL=0V IPSD=5A , VCH=0V VCH=0V VCH=1.5V *1 *1 *1
Rev.1.0, Sep.19.2003, page 4 of 13
M52957AFP
Electrical characteristics (cont.)
(Ta = 25C, VCC = 3.0V, unless otherwise noted.)
Limits Classification Double integration Parameter CINT rapid charge current CINT reference voltage The first integration current The second integration current The first integration current stability percentage The second integration current stability percentage The first and second integration current ratio AF output time(9:1)-1 AF output time(6:4)-1 AF output time(3:7)-1 AF slope -1 AF linearity-1 AF input condition 2 AF output time(9:1)-2 AF output time(6:4)-2 AF output time(3:7)-2 AF slope -2 AF input condition 3 AF linearity-2 AF output time(9:1)-3 AF output time(6:4)-3 AF output time(3:7)-3 AF slope -3 AF linearity-3 AF input condition 1 minus 2 AF output time(9:1) AF output time(6:4) AF output time(3:7) Data SOUT leak current SOUT saturation voltage Signal light saturation current Stationary light remove current Clamp level Symbol ICINTC VCINT ICI1 ICI2 ICI1 Min. 84 1.6 4.06 -3.20 Typ. 120 1.8 5.80 -2.46 Max. 156 2.0 7.54 -1.27 10 Unit A V A A % Test conditions VCI=1V (CINT stable period) GND criterion VCINT=1.5V VCHF=2V , VCHN=0V Note *1 *1 *1 *1 *2
ICI2
10
%
*2
ICI12 D(9:1) - 1 D(6:4) - 1 D(3:7) - 1 AF - 1 LAF - 1 D(9:1) - 2 D(6:4) - 2 D(3:7) - 2 AF - 2 LAF - 2 D(9:1) - 3 D(6:4) - 3 D(3:7) - 3 AF - 3 LAF - 3 D(9:1) D(6:4) D(3:7) ISOUTL VSOUTS INF IPSD ICLAM
2.12 11.78 7.77 3.77 6.57 0.9 11.78 7.77 3.77 6.57 0.9 11.78 7.77 3.77 6.57 0.9 3.0 -30
2.36 13.40 8.95 4.51 8.89 1.0 13.40 8.95 4.51 8.89 1.0 13.40 8.95 4.51 8.89 1.0
2.60 15.02 10.13 5.25 11.21 1.1 15.02 10.13 5.25 11.21 1.1 15.02 10.13 5.25 11.21 1.1 280 280 280 1.0 0.3 30 30 msec msec msec msec msec msec msec msec msec msec msec msec sec sec sec A V A A %
| ICI1 | / | ICI2 | Near side9 : Far side1 Near side6 : Far side4 Near side3 : Far side7 *3 *3 *3 *3 *3 Near side9 : Far side1 Near side6 : Far side4 Near side3 : Far side7 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 Near side9 : Far side1 (Condition 1-2) Near side6 : Far side4 (Condition 1-2) Near side3 : Far side7 (Condition 1-2) VIN = 5.5V IOUT=500A *4 *4 Change quantity for Typ. current
AF input condition 1
Near side9 : Far side1 Near side6 : Far side4 Near side3 : Far side7
Sensor
Rev.1.0, Sep.19.2003, page 5 of 13
M52957AFP * *1 : Set up the logic control terminal, correspond to the parameter. * *2 : Change ratio between the first integration current and the second integration current at a voltage of CINT that is {CINT reference voltage(VCINT)-0.1V} and 1V.
I CI 1=( 1 I CI 2=( 1 -
The first integration current (CINT=1V) The first integration current (CINT=VCINT-0.1V) The second integration current (CINT=1V)
) X 100%
) X 100% The second integration current (CINT=VCINT-0.1V)
* *3 : Connect the resistance of 120 instead of PSD and establish current output from PHOTO COUPLER correspond to the parameter. And input the varied resistance ratio. And measure the pulse width of SOUT output at that time, obtain AFslope and AF linearity from the equations below. Input condition1: IPSD (Stationary light current)=0 I1+I2=100nA Input condition2: IPSD (Stationary light current)=0 I1+I2=50nA Input condition3: IPSD (Stationary light current)=10A I1+I2=100nA D(9 : 1) * * * The pulse width of SOUT output at input with I1:I2=9:1 D(6 : 4) * * * The pulse width of SOUT output at input with I1:I2=6:4 D(3 : 7) * * * The pulse width of SOUT output at input with I1:I2=3:7 AF slope : DAF = D(9 : 1) - D(7 : 3) AF linearity : L(AF) = (D(9 : 1) - D(6 : 4)) / (D(6 : 4) - D(7 : 3)) PSD quite resistance : 120K * *4 : The input current of one side channel when stationary light remove circuit and I/V transform AMP is not saturated.
Rev.1.0, Sep.19.2003, page 6 of 13
M52957AFP
Description of Pin
Limits
Pin name
Circuit diagram
Parameter Min. Typ. Max. "H"input voltage "L"input voltage "H"input current "L"input current "H"input voltage "L"input voltage 1.1 7.0
Unit
Test conditions and note
HOLD INT CLALV RESET
V 0 0.3
1.0 A -100 -75 -50
VIH=5.5V
VIL=0V
VCC -0.3 0
7.0 V 0.3
STB
"H"input current "L"input current 3.0 A -150 -100 -50 VIL=0V VIH=5.5V
"L"output voltage
0.3
V
IOL=500A
SOUT
"H"leak current 1.0 A VIN=5.5V
Rev.1.0, Sep.19.2003, page 7 of 13
M52957AFP
Application Example
0.068F Vcc 3 CHN
1.0F
NC 4 TESTN
CINT 6
PULSE WIDTH TRANSFORM (DOUBLE INTEGRATION)
2 1 PSDN STATIONARY LIGHT REMOVE HOLD HOLD I2 16 CHF 15 14 12 STATIONARY LIGHT REMOVE
I/V TRANSFORM AMP
I1
I/V TRANSFORM AMP
BIAS RECKON
I1 I1+I2
REFERENCE VOLTAGE
PSD PSDF
CLAMP CIRCUIT
13 NC HOLD TESTF
1.0F
CLAMP LEVEL SWITCHING
SEQUENTIAL CONTROL LOGIC
11 GND2 CLALV
GND1
5
7
9
10
8
PVcc
STB RESET
INT HOLD SOUT IRED
MICROCOMPUTER
Controls
(1) STB This terminal enables IC to operate. IC is Standby at HIGH in this terminal. IC can operate at LOW in this terminal. (2) RESET This terminal resets the whole IC including a logic. This terminal resets IC at HIGH. This terminal cancel resetting IC at the edge from HIGH to LOW. IC includes power on reset function. The control from external is also possible. The reset term in IC takes OR between power on reset and control signal from external.
H L Indefiniteness Reset Reset canceled
While this terminal is HIGH,dielectric divide pole countermeasures circuit of integration condenser is active.
Rev.1.0, Sep.19.2003, page 8 of 13
M52957AFP (3)CLALV This terminal sets up clamp level. As including D/A of 4bit, 16way clamp level setting is possible by inputting clock after reset is canceled(include none clamp).
Set up current value of each bit is on the right table. The number of input clock and set up clamp level is as follows.
bit 1 2 3 4
Set up current (Typ.) 0.125 nA 0.25 nA 0.5 nA 1.0 nA Clamp level(Typ.) 1.500 nA 1.625 nA 1.750 nA 1.875 nA None clamp 0.125 nA 0.250 nA 0.375 nA 0.500 nA
Clock value 0 1 2 3 4 5 6 7 8 9 10 11
Clamp level(Typ.) None clamp 0.125 nA 0.250 nA 0.375 nA 0.500 nA 0.625 nA 0.750 nA 0.875 nA 1.000 nA 1.125 nA 1.250 nA 1.375 nA
Clock value 12 13 14 15 16 17 18 19 20
Clamp level is established with fall edge of input clock. It repeats the same value after 16 clock.
(4) HOLD INT These terminals implement the following controls by inputting HIGH/LOW. a. CINT rapid charge ON , OFF b. CHrapid charge ON , OFF c. Stationary light hold ON , OFF d. The first integration ON , OFF e. The second integration ON , OFF
Stationary light hold
HOLD The first integration CINT rapid charge INT CH rapid charge The second integration
Reset canceled
Rev.1.0, Sep.19.2003, page 9 of 13
M52957AFP a. CINT rapid charge After reset is canceled, the capacity of CINT is charged rapidly until INT terminal first falls. b. CH rapid charge After reset is canceled, the capacity of CH is charged rapidly until INT terminal first rises and falls. c. Stationary light hold After reset is canceled, holds the stationary light while HOLD terminal is HIGH. d. The first integration After reset is canceled, as HOLD terminal is HIGH and INT terminal is HIGH, the first integration is implemented while INT terminal is HIGH. Therefore, the first integration must be finished(INT terminal from HIGH to LOW) until stationary light hold will be completed (HOLD terminal from HIGH to LOW) e. The second integration After reset is canceled, the second integration is implemented as HOLD terminal is LOW and INT terminal is HIGH. And, the second integration is completed by exceeding judgment level of CINT terminal although INT terminal is HIGH. (5)SOUT When the second integration starts, This terminal becomes from HIGH to LOW. If CINT terminal exceeds judge level or INT terminal becomes from HIGH to LOW, this terminal becomes from LOW to HIGH. (notice)As the signal from microcomputer, the signal that controls IRED ON/OFF is required except for above mentioned control signals. But applying the timing of HOLD is available.
Rev.1.0, Sep.19.2003, page 10 of 13
M52957AFP
Sequential Time Chart Example
Rev.1.0, Sep.19.2003, page 11 of 13
M52957AFP
Mask Option
(1) The second integration current value can be doubled.( 2.5 (2) Control terminal variation 5.0A)
1
Full spec (typical)
C L A L V 11 R E S E T 7 H O L D 10 S O U T 8
S T B 5
I N T 9
This type uses CLALV,STB,RESET,INT,HOLD,SOUT terminal as I/F terminal to the microcomputer. This is the typical type at M52957AFP.
MICROCOMPUTER
2
Most simplified type
H O L D 10 S O U T 8
I N T 9
This type does not connect CLALV,STB,RESET terminals to the microcomputer. When above mentioned terminals are not connected to the microcomputer without changing mask,connect each terminal to the ground. In this case,clamp level becomes 0 and standby function is lost. Power on reset in IC is used as reset.
MICROCOMPUTER
3
Explanation of the terminal that can be simplified. (a)CLALV In the typical type,16way clamp levels can be set by the external control,but also the terminal can be simplified by mask option as follows. Selects 1 point from 16 steps of clamp level and fixes it. Selects 2 points from clamp level and switches it by changing CLALV terminal HIGH/LOW. However,as selecting 2 points,there is a following constraint.
(I) Clamp level fixation
(II) Clamp level 2 step changeover
0.125nA
0.25nA
0.5nA
1.0nA
Fixes 3 parts of 4 switches correspond to each bit in figure to ON or OFF,controls another part by CLALV terminal .
(b)STB
When no standby function required such as VCC is suitched ON/OFF, STB terminal can be eliminated. Since IC include power on reset circuit, RESET terminal can be eliminated, As merit of controlling RESET terminal from outside, distance detection time can be shortened because there is no need to switch VCC to STB terminal ON/OFF at consecutive distance detection.
(c)RESET
Rev.1.0, Sep.19.2003, page 12 of 13
M52957AFP
16P2E-A
JEDEC Code -- e b2
16 9
Plastic 16pin 225mil SSOP
Weight(g) 0.06 Lead Material Alloy 42
Package Dimensions
EIAJ Package Code SSOP16-P-225-0.65
HE
E
L1
L
Rev.1.0, Sep.19.2003, page 13 of 13
F
e1
Recommended Mount Pad Symbol
1
8
A
G
D
A2
b
A1
e y
x
M
c z Z1 Detail G Detail F
A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2
Dimension in Millimeters Min Nom Max -- -- 1.45 0 0.1 0.2 -- 1.15 -- 0.17 0.22 0.32 0.13 0.15 0.2 4.9 5.0 5.1 4.3 4.4 4.5 -- 0.65 -- 6.2 6.4 6.6 0.3 0.5 0.7 -- 1.0 -- -- 0.225 -- -- 0.375 -- -- 0.13 -- -- -- 0.1 0 -- 10 -- 0.35 -- -- 5.8 -- -- 1.0 --
I2
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