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SI9123
New Product
Vishay Siliconix
500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Control
FEATURES
D 12-V to 72-V Input Voltage Range D Compatible with ETSI 300 132-2 100 V, 100-ms Transients D Integrated Half-Bridge 1-A Primary Drivers D Secondary Synchronous Rectifier Control D Voltage Mode Control D Voltage Feedforward Compensation D High Voltage Pre-Regulator Operates During Start-Up D Current Sensing On Low-Side Primary Device D D D D D Hiccup Current Control During Shorted Load Low Input Voltage Detection Programmable Soft-Start Function Programmable Oscillator Frequency Over Temperature Protection
APPLICATIONS
D Network Cards D Power Supply Modules
DESCRIPTION
SI9123 is a dedicated half-bridge controller IC ideally suited to fixed telecom dc-dc converter applications where high efficiency is required at low output voltages (e.g. <3.3 V). Designed to operate within the voltage range of 12-72 V and withstand 100 V, 100 ms transients, the IC is capable of controlling and directly driving both primary side MOSFET switches of a half-bridge circuit. High conversion efficiency is achieved by use of synchronous rectifying MOSFET transistors in the secondary. Due to the very low on-resistance of the secondary MOSFETs, a significant increase in the efficiency can be achieved as compared with conventional Schottky diodes for today's low output voltages. On-chip control of the dead time delays between the primary and secondary signals keep efficiencies high and prevents accidental destruction of the power transformer or wasted energy from self timed approaches. Such a system can achieve conversion efficiencies well in excess of 90%.
FUNCTIONAL BLOCK DIAGRAM
VINEXT REXT VIN D1 BST VCC CVCC EP Voltage Information SS CSS CS2 CS1 Current Control Secondary Drivers SEC_SYNC Voltage Control SoftStart PWM Primary Drivers DL (Low) RS CLOAD RLOAD Pre-Reg CBOOST LX DH (High) VOUT
+ CVIN1 Power Transformer To VCC
Pulse Transformer Driver Logic
SI9123
Half-Bridge Synchronous Controller Opto Error Amp
1.215 V
Figure 1.
Document Number: 72098 S-03639--Rev. B, 20-Mar-03 www.vishay.com
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SI9123
Vishay Siliconix
New Product
DESCRIPTION (CONTINUED)
SI9123 has advanced current monitoring circuitry to permit the user to set the maximum current in the primary circuit. Such a feature acts as protection against output shorts. Upon sensing an overload condition, the converter is shut off for a period of time and then soft-start cycle is re-initiated, achieving hiccup mode operation. Current sensing is by means of a sense resistor on the low-side primary device. An integrated over -temperature shutdown circuit also protects the system. The 100-V depletion mode MOSFET integrated pre-regulator circuit permits direct operation from input voltage with only one series resistor during startup. The pre-regulator automatically disconnects from the input supply when the output voltage is established by means of a feedback winding from the filter inductor. SI9123 is available in TSSOP-16 pin package. In order to satisfy the stringent ambient temperature requirements, SI9123 is rated to handle the industrial temperature range of -40 to 85_C.
DETAILED BLOCK DIAGRAM
VIN
VCC VREF
ROSC
Pre-Regulator
+ -
VUVLO 8.8 V Level Shift High-Side Driver OSC
Ramp
BST DH LX
VINDET VREF Error Amplifier 2.2 R R EP + VCC 1.65 V SS Gain CS2 CS1 + Peak DET Hiccup Mode Start I 4I + VSD 550 mV + PWM Comparator + VUV
VFF
VCC DL
Low-Side Driver
Driver Control and Timing
VCC SEC_SYNC SEC_SYNC Driver
OTP
Over Current Protection GND
SI9123
PGND
Figure 2.
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Document Number: 72098 S-03639--Rev. B, 20-Mar-03
SI9123
New Product
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
VIN (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V VIN (100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V VBST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V VBST - VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VREF, ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V SEC_SYNC Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa TSSOP-16 (TA = 25_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 W Thermal Impedance (QJA) TSSOP-16b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100_C/W Notes a. Device mounted on JEDEC compliant 1S2P (4-layer) test board.. b. Derate - 10 mW/_C above 25_C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 to 72 V CVIN1 o CVIN2 . . . . . . . . . . . . . . . . . . . . . . . 100 mF/ESR v 100 mW and 0.1 mF VCC Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 to 13.2 V CVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 mF fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 600 kHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 to 72 kW REXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 kW CSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 nF CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 mF CBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF CLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mF Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 0. 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA
SPECIFICATIONSa
Test Conditions Unless Specified Parameter Reference (3.3 V)
Output Voltage Short Circuit Current Load Regulation Power Supply Rejection VREF ISREF dVr/dlr PSRR VCC = 12 V, 25_C Load = 0 mA VREF = 0 V IREF = 0 to - 2.5 mA @ 100Hz - 30 60 3.2 3.3 3.4 - 50 - 75 V mA mV dB
Limits
- 40 to 85_C
Symbol
CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V v VCC v 13.2 V
Minb
Typc
Maxb
Unit
Oscillator
Accuracy (1% ROSC) Max Frequency FMAX ROSC = 30 kW, fNOM = 500 kHz ROSC = 24 kW - 20 600 20 % kHz
Error Amplifier
Input Bias Current Gain Bandwidth Power Supply Rejection Slew Rate IBIAS AV BW PSRR SR @ 100Hz VEP = 0 V - 40 - 2.2 5 60 0.5 MHz dB V/ms - 15 mA
Current Sense Amplifier
Input Voltage CM Range Input Amplifier Gain Input Amplifier Bandwidth Input Amplifier Offset Voltage VCC Hiccup Threshold Hysteresis Document Number: 72098 S-03639--Rev. B, 20-Mar-03 VCM AVOL BW VOS VTHCUP Increase CS2 Until SS Hiccups Decrease CS2 Until SS Clamps VCS1 - GND, VCS2 - GND "150 17.5 5 "5 150 - 50 www.vishay.com mV mV dB MHz
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SI9123
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Specified Parameter PWM Operation
Duty Cyclee DMAX DMIN fOSC = 500 kHz VEP = 0 V VEP = 1.85 V 90 92 t15 95 %
New Product
Limits
- 40 to 85_C
Symbol
CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V v VCC v 13.2 V
Minb
Typc
Maxb
Unit
Pre-Regulator
Input Voltage (Continuous) Input Leakage Current Regulator Bias Current Pre-Regulator Drive Capacility VCC P R Pre-Regulator T l t Turn Off Threshold Voltage Undervoltage Lockoutd VUVLO Hysteresis VIN ILKG IREG1 IREG2 ISTART VREG1 VREG2 VUVLO VUVLOHYS IIN = 10 mA VIN = 72 V, VCC u VREG VIN = 72 V, VINDET t VSD VIN = 72 V, VINDET u VREF VCC t VREG VINDET u VREF VINDET = 0 V 7.15 VCC Rising TA = 25_C 8.1 TA = 25_C 20 7.4 8.5 9.1 9.1 9.2 8.6 8.6 0.5 9.8 9.3 V 10.4 9.7 86 4 72 10 200 6.5 mA V mA
Soft-Start
Soft-Start Current Output Soft-Start Completion Voltage ISS1 ISS2 VSS_COMP 0 t VSS t 2 Vbe 2 Vbe t VSS t 4.8 V Normal Operation 12 60 7.35 20 100 8.1 28 200 8.85 mA V
Shutdown
VINDET Shutdown FN VINDET Hysteresis VSD VINDET Rising VINDET 350 550 200 720 mV
VINDET Input Threshold Voltages
VINDET - VIN Under Voltage VINDET Hysteresis VUV VINDET Rising VINDET 3.13 3.3 0.3 3.46 V
Over Temperature Protection
Activating Temperature De-Activating Temperature TJ Increasing TJ Decreasing 160 130 _C
Converter Supply Current (VCC)
Shutdown Switching Disabled Switching w/o Load Switching with CLOAD VCC Hiccup Current ICC1 ICC2 ICC3 ICC4 IHCUP Shutdown, VINDET = 0 V VINDET t VREF VINDET u VREF, fNOM = 500 kHz VCC = 12 V, CDH = CDL = 3 nF, CSEC_SYNC = 0.3 nF CS2 - CS1 = 200 mV, CDL = CDH = 3 nF CSEC_SYNC = 0.3 nF 50 1.8 3.0 140 2.8 4.4 15.2 4.3 350 3.8 6.8 mA mA
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Document Number: 72098 S-03639--Rev. B, 20-Mar-03
SI9123
New Product
SPECIFICATIONSa
Test Conditions Unless Specified Parameter Symbol
CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V v VCC v 13.2 V
Vishay Siliconix
Limits
- 40 to 85_C
Minb
VBST 0.3
Typc
Maxb
Unit
Output MOSFET DH Driver (High-Side)
Output High Voltage Output Low Voltage Boost Current LX Current Peak Output Source Peak Output Sink Rise Time Fall Time VOH VOL IBST ILX ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA 0.8 VLX = 48 V, VBST = VLX + VCC V VLX = 48 V, VBST = VLX + VCC V TA = 25_C CDH = 3 nF, VCC = 12 V, 20 - 80% 25_C, nF V - 0.8 0.75 1.55 - 0.4 - 1.0 1.0 18 22 28 28 ns V
VLX + 0.3 2.4 - 0.1 - 0.75
mA A
Output MOSFET DL Driver (Low-Side)
Output High Voltage Output Low Voltage Peak Output Source Peak Output Sink Rise Time Fall Time VOH VOL ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA - 1.0 VCC = 12 V TA = 25_C CDL = 3 nF, VCC = 12 V, 20 - 80% 25_C, nF V 0.75 1.0 19 24 28 28 ns VCC 0.3 0.3 - 0.75 A V
Secondary_Synchronous Driver
Output High Voltage Output Low Voltage Leading Edge Delays Trailing Edge Delays Peak Output Source Peak Output Sink Rise Time Fall Time VOH VOL td1 td3 td2 td4 ISOURCE ISINK tr tf VCC = 12 V TA = 25_C CSEC SYNC = 3 nF, VCC = 12 V 20 - 80% 25_C, SEC_SYNC nF V, TA = 25_C, VCC = 12 V, LX = 48 V, See Figure 3 25 C, CDH = CDL = 3 nF, CSGC_SYNC = 0.3 nF Sourcing 10 mA Sinking 10 mA 90 75 90 65 - 100 100 16 17 28 28 ns mA VCC 0.4 0.4 110 95 110 95 ns V
Voltage Mode
Error Amplifier td1DH td2DL Input to high-side switch off Input to low-side switch off t200 t200 ns
Current Mode
Current Amplifier td3DH td4DL Input to high-side switch off Input to low-side switch off t200 t200 ns
Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40_ to 85_C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 12 V unless otherwise noted. d. VUVLO tracks VREG1 by a diode drop e. Measured on DL or DH outputs.
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
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SI9123
Vishay Siliconix
New Product
TIMING DIAGRAMS FOR MOS DRIVERS
VCC
SEC_SYNC
GND VCC DL GND
VBST DH VMID GND Time
DH 50% LX
BST
VLX
DH, LX
DH, LX
VMID
SEC_SYNC 50% DH, LX SEC_SYNC
SEC_SYNC 50%
VCC GND Trailing
Leading td3 td4
DL
50% GND
Leading td1 td2
Trailing
Figure 3.
Hiccup Time Out VOLTS
Soft Start
Over Current Detected
2 Vbe GND t1 t2 Time
SS
Figure 4.
Soft-Start, Hiccup Mode Operation
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Document Number: 72098 S-03639--Rev. B, 20-Mar-03
SI9123
New Product
PIN CONFIGURATION
Vishay Siliconix
SI9123DQ (TSSOP-16)
VIN VCC VREF GND ROSC EP VINDET CS1 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 BST DH LX DL PGND SEC_SYNC SS CS2
ORDERING INFORMATION
Part Number
SI9123DQ-T1 SI9123DQ - 40 to 85_C
Temperature Range
Package
Tape and Reel Bulk
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
VIN VCC VREF GND ROSC EP VINDET CS1 CS2 SS SEC_SYNC PGND DL LX DH BST Input supply voltage for the start-up circuit. Supply voltage for internal circuitry 3.3-V reference, decoupled with 1-mF capacitor Ground External resistor connection to oscillator Voltage control input
Function
VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. Current limit amplifier negative input Current limit amplifier positive input Soft-Start control - external capacitor connection Secondary side timing signal Power ground. Low-side gate drive signal - primary High-side source and transformer connection node High-side gate drive signal - primary Bootstrap voltage to drive the high-side n-channel MOSFET switch
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
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SI9123
Vishay Siliconix
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DETAILED FUNCTIONAL BLOCK DIAGRAM
VCC
VIN Pre-Regulator
VREF
Reference Voltage 3.3 V
VREG VREF + 9.1 V
+ VUVLO
9.1 V
VUV
+ 8.6 V High-Side Primary Driver BST
VINDET
VREF + VSD 160_C Temp Protection VSD Clock Clock 132 kW 60 kW Logic VUV VUVLO OTP High Voltage Interface
Voltage Feedforward
550 mV OSC
DH LX
ROSC Oscillator
VCC
Low-Side Primary Driver DL
EP
+ VREF/2
+ PWM Generator
Logic PGND
Current Control CS2 CS1 + 100 mV
Gain VCC
Secondary Synchronous Driver SEC_SYNC
Blanking VCC 20 mA SS GND SS Enable 80 mA SS Control
Figure 5.
DETAILED OPERATION
Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins charging the external capacitor on VCC. The charging current is limited to typically 40 mA by the internal 100 V DMOS device. When VCC exceeds the UVLO voltage of 8.8 V, a soft-start cycle of the controller is initiated to provide power to the secondary. Once switching commences, the internal gate drivers for the primary side switching transistors and the drive current into the secondary synchronization driver draw additional current from the VCC capacitor and pre-regulator.
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
A detailed Functional Block Diagram is shown in Figure 5 with additional detail of the pre-regulator shown in Figure 6. The pre-regulator circuit acts as a linear regulator to provide VCC directly from the VINEXT supply until the VCC supply voltage between 10 V to 13.2 V can be sustained from an auxiliary winding from the secondary of the power inductor.
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SI9123
New Product
Vishay Siliconix
The pre-regulator will remain on until VCC equals VREG but between VUVLO and VREG, excessive current may result in VCC falling below VUVLO and stopping soft-start operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing of the VCC capacitor, bootstrap capacitor, the soft-start capacitor, the primary MOSFET gate driving charge, and load on the SEC_SYNC output. The value of the VCC capacitor should be chosen to be capable of maintaining soft-start operation with VCC above VUVLO until the VCC current can be supplied from the external circuit (e.g., via an auxiliary winding on the secondary inductor).
VINEXT REXT = 1.4 kW VIN HVDMOS VCC Auxillary VCC
clamp turns on at 14.5 V to shunt excessive current to GND. In systems where operation is directly from a 12 V supply, VINEXT and VCC can be connected to the 12 V bus. The soft-start circuit is designed for the dc-dc converter to start up in an orderly manner and reduce component stress. Soft-start is achieved by ramping the maximum attainable duty cycle during the soft-start time. The duty cycle is increased from zero to the final value at the rate set by an external capacitor, CSS as shown in Figure 7. The hiccup time is set by an internal 20 A current source charging CSS from 0 V to 2 Vbe, at which point switching begins. Then a 100 A charging current is applied to CSS to charge from 2 Vbe to the final value controlling the duty cycle as it rises. In the event of UVLO, shutdown or over current, the SS pin will be held low (<1 V) disabling driver switching. A longer soft-start time may be needed for highly capacitive loads and high peak-output current applications. In the event of an over current condition being detected, the soft-start pin will be pulled low and the cycle will start again performing a hiccup as shown in Figure 4. The hiccup off-time, t1, is given by:
t1 [ CSS 1.2 V 20 mA
14.5 V VREF
CVCC 4.7 mF
GND
The soft-start time t2 is can be estimated as:
t2 [ CSS (K VOUT 100 mA) n
Figure 6.
High-Voltage Pre-Regulator Circuit
The feedback voltage from the output of the auxiliary winding must sustain VCC above VREG to fully disconnect the pre-regulator, isolating VCC from VINEXT. VCC is then maintained above VREG for the duration of operation. In the event of an over voltage condition on VCC, an internal voltage
where VOUT is the output of the converter, and n is the turns ratio of the primary to each secondary winding, and K is the ratio of the resistive divider from VINEXT to VINDET (typically 10/1).
VCC + Peak Detect GM I SS Control CS1 CS2 Blank + SS Enable AV AV 150 mV SS 4I
CSS AV 100 mV
Figure 7.
Current-Sense and Soft-Start Circuit Block Diagram
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
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SI9123
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Voltage feed-forward is implemented by taking the attenuated VINEXT signal at VINDET to directly modulate the duty cycle. This relationship is shown in the Typical Characteristic section, Duty Cycle vs. VINDET, page 12. The response time to line transients is very short since the PWM duty cycle is changed directly without having to go through the error amplifier feedback loop. At start-up, i.e., once VCC is greater than VUVLO, switching is initiated under soft-start control which increases the maximum attainable switch on-time linearly over the soft-start period. Start-up from a VINDET power down, over-temperature, or over current is also initiated under soft-start control. Half-Bridge and Synchronous Rectification Timing Sequence The PWM signal generated within the IC controls the low and high-side bridge drivers on alternate cycles. A period of inactivity always results after initiation of the soft-start cycle until the soft-start voltage reaches approximately 2 Vbe and PWM generated switching begins. The first bridge driver to switch is always the low-side, DL as this allows charging of the high-side boost capacitor. The timing and coordination of the drives to the primary and secondary stages is very important and the relationships are shown in Figure 3. It is essential to avoid the situation where both of the secondary MOSFETs are on when either the high or the low-side switch are active. In this situation the transformer would effectively be presented with a short across the output. The SEC_SYNC timing signal is set to be ahead of the primary drive outputs by 50 - 80 ns. Primary High- and Low-Side MOSFET Drivers The drive voltage for the low-side MOSFET switch is provided directly from the VCC supply. The high-side MOSFET however requires the gate voltage to be enhanced above VIN. This is achieved by bootstrapping the VCC voltage onto the LX voltage (the high-side MOSFET source). In order to provide the bootstrapping an external diode and capacitor are required as shown on the application schematic. The capacitor will charge up after the low-side driver has turned on. The driver signals DH and DL are shown in Figure 3. The drive currents for the primary side MOSFETs is supplied from the VCC supply and can influence start up conditions. Secondary Synchronization Driver The secondary side MOSFETs are driven by the SEC_SYNC output via a pulse transformer and gate driver circuits. The time relationships are shown in Figure 3. Logic circuitry on the secondary side is required to align the synchronous rectifier gate drive with the primary drive. The current supplied to the pulse transformer is drawn from VCC. Oscillator The oscillator is designed to operate at a frequencies up to 500 kHz. The 500-kHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator and therefore the switching frequency is programmable by a resistor on the ROSC pin. The relationship is shown in the Typical Characteristics, FOSC vs. ROSC.
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
Care should be taken to control the operating time using the internal pre-regulator to prevent excessive power dissipation in the IC. The use of an external dropping resistor connected in series with the VIN pin to drop the voltage during start up is recommended. The value of R EXT is selected to drop the input voltage to the IC under worst case conditions thereby dissipating power in the resistor, instead of the IC. If the supply output is shorted and the auxiliary winding does not provide the VCC current, then continuous soft-start cycles will occur. The average power in the IC during start-up where the hiccup operation would be performed continuously is given by:
t1 ICC2 ) t2 ICC4 ) I SEC_SYNC t1 ) t2 t1 ICC2 ) t 2 ICC4 ) ISEC_SYNC t1 ) t2
Power (IC) + V IN
Power REXT + VINEXT * VIN
where ICC2 is the non-switching supply current, ICC4 is the supply current while switching, ISEC_SYNC is the average current out of the SEC_SYNC pin, and t1 and t2 are defined in Figure 4. After the feedback voltage from the secondary overrides the internal pre -regulator, no current flows through REXT. An example of the feedback circuitry is shown in Figure 15. The SS pin has a predictable +1.25-mV/_C temperature coefficient and can be used to continuously monitor the junction temperature of the IC for a given power dissipation. Reference The reference voltage of SI9123 is set at 3.3 V. The reference voltage should be de-coupled externally with a 0.1 mF capacitor and has 50-mA source capability. The REF pin voltage is 0 V in shutdown mode. Voltage Mode PWM Operation Under normal load conditions, the IC operates in voltage mode and generates a fixed frequency pulse-width modulated signal to the drivers. Duty cycle is controlled over a wide range to maintain the output voltage under line and load variation. Voltage feed-forward is also included to improve line regulation and transient response. In the half-bridge topology requiring isolation between output and input, the reference voltage and error amplifier are supplied externally, usually on the secondary side. The output error signal is usually passed to the power converter through an opto-coupling device for isolation. The error information enters the IC via pin EP and where 0 V results in the maximum duty cycle, whilst 2 V represents minimum duty cycle. The EP error signal is gained up by -2.2X via an inverting amplifier and compared against the internal ramp generator. The relationship between Duty Cycle and VEP is shown in the Typical Characteristic section, Duty Cycle vs. VEP 25_C, page 12.
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SI9123
New Product
Hiccup Operation Current limiting is achieved by monitoring the differential voltage between CS1 and CS2 pins which are connected across a primary low-side sense resistor. Once the differential voltage exceeds the 150-mV trigger point, Hiccup operation is started. The SS pin is pulled to ground and switching stops until the SS pin charges up to 2 Vbe whereupon a duty cycle limited soft-start is initiated. The upper and lower switching points of the current limit have 50 mV of hysteresis. VINEXT Voltage Monitor - VINDET The SI9123 provides a means of sensing the voltage on VINEXT to control the operating mode and provides the feed-forward control voltage to the PWM controller. This is achieved by choosing an appropriate resistive tap between VINEXT and ground. When the VINDET voltage is greater than 720 mV but less than VREF and VCC is greater than VUVLO, all internal circuitry is enabled, but switching is stopped.
Vishay Siliconix
When the applied voltage is greater than VREF and VCC is greater than VUVLO, the output drivers are activated as normal. If the voltage applied to the VINDET pin is greater than VCC -0.3 V, the high-side driver, DH , will stop switching until the voltage drops below VCC -0.3 V. If continuous switching is desired under maximum VINEXT conditions, the resistive tap on the VINEXT divider must be set to accommodate the normal VCC operating voltage. Alternatively, a zener clamp diode from VINDET to GND may also be used. VINDET also provides the input to the voltage feed-forward function by adjusting the amplitude of the PWM ramp to the PWM comparator. Shutdown Mode If VINDET pin is forced below 470 mV the device will enter SHUTDOWN mode. This powers down all unnecessary functions of the controller, ensures that the primary switches are off and results in a low level current demand of 140 mA from the VINEXT or VCC supplies.
TYPICAL CHARACTERISTICS
VSS vs. Temperature, VCC = 12 V
8.20 10.0
VREG vs. Temperature, VIN = 48 V
8.15 TC = +1.25 mV/C 8.10 V SS (V) VINDET u VREF V REG(V)
9.5
9.0 VINDET u VREF 8.5 TC = - 11 mV/C
8.05
8.00 8.0
7.95
7.90 - 50
- 25
0
25
50
75
100
125
150
7.5 - 50
- 25
0
25
50
75
100
125
150
Temperature (_C)
Temperature (_C)
ISS1 vs. VCC vs. Temperature
25 VCC = 13 V 23 VCC = 12 V 21 140
ISS2 vs. VCC vs. Temperature
130 VCC = 13 V VCC = 12 V
I SS1 (uA)
I SS1 (uA)
120
110
19 100 VCC = 10 V 17 90 VCC = 10 V
15 - 50
- 25
0
25
50
75
100
125
80 - 50
- 25
0
25
50
75
100
125
Temperature (_C) Document Number: 72098 S-03639--Rev. B, 20-Mar-03
Temperature (_C) www.vishay.com
11
SI9123
Vishay Siliconix
TYPICAL CHARACTERISTICS
FOSC vs. ROSC @ VCC = 12 V
600 3.300
New Product
VREF vs. Temperature, VCC = 12 V
3.295 500 3.290 FOSC (kHz) V REF (V)
400
3.285
3.280 300 3.275
200 20 30 40 50 ROSC (kW) 60 70 80
3.270 - 50
- 25
0
25
50
75
100
Temperature (_C)
IHCUP vs. SS Duty Cycle, CSS = 22 nF
10 100 90 9 Duty Cycle (%)
DL, DH Duty Cycle vs. VEP
3.6 V = VINDET 80 70 60 50 40 VCC = 12 V 7.2 V 4.8 V
8 IHCUP (mA)
7
6 VCC = 12 V ViINDET = 4.8 V CDH = CDL = 3 nF CSEC_SYNC = 0.3 nF 10 20 30 40 50
30 20 10 0 0.0
5
4 SS Duty Cycle (%) = t2 / (t1 + t2)
0.5
1.0 VEP (V)
1.5
2.0
DL, DH Delay vs. Temperture
120 VBST = 60 V VLX = 48 V VCC = 12 V 100 Delay (ns) 100 90 td2 Duty Cycle % 80 70 60
Duty Cycle vs. VINDET @ 25_C VEP = 1.2 V, VCC = 9.5 V
td1
80
td3 td4
DL, DH 60 50 40 40 - 50 30 2.5
- 25
0
25
50
75
100
125
3.5
4.5
5.5
6.5
7.5
Temperature (_C)
VINDET (V)
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12
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
SI9123
New Product
TYPICAL CHARACTERISTICS
IREG2 vs. Temperature
4.2 Drivers w/o CLOAD VIN = 48 V 4.75 Drivers w/o CLOAD VCC = 12 V
Vishay Siliconix
ICC3 vs. Temperature
4.0
4.55
IREG2 (mA)
3.6
ICC3 (mA)
3.8
4.35
4.15
3.4
3.95
3.2 - 50
- 25
0
25
50
75
100
3.75 - 50
- 25
0
25
50
75
100
Temperature (_C)
Temperature (_C)
DH, DL ISOURCE vs. VOH
250 250
DH, DL ISINK vs. VOL
200
VCC = 12 V
200
VCC = 12 V
ISOURCE (mA)
ISINK (mA)
150
150
100
100
50
50
0 0 200 400 VOH (mV) 600 800
0 0 200 400 VOL (mV) 600 800
SEC_SYNC ISOURCE vs. VOH
35 30 VCC = 12 V 25 ISOURCE (mA) 20 15 10 5 0 0 200 400 VOH (mV) Document Number: 72098 S-03639--Rev. B, 20-Mar-03 600 800 ISINK (mA) 25 20 15 10 5 0 0 35 30
SEC_SYNC ISINK vs. VOL
VCC = 12 V
200
400 VOL (mV)
600
800
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SI9123
Vishay Siliconix
TYPICAL WAVEFORMS
New Product
Figure 8.
Over Current Hiccup (CS2 = 200 mV)
DH 20 V/div VCC = 12 V
Figure 9.
Over Current Hiccup Cycle
DH 20 V/div
VCC = 12 V DL 20 V/div
DL 20 V/div
CS2 100 mV/div
CS2 100 mV/div
GND
SS 1 V/div
CSS = 22 nF
SS 1 V/div
CSS = 22 nF
200 ms/div
200 ms/div
Figure 10. Pre-Regulator Start-Up
Figure 11. Operating Driver Waveforms
VCC = 12 V DH 5 V/div
VINEXT 10 V/div SEC_SYNC 5 V/div VCC DL 5 V/div
2 ms/div
500 ns/div
Figure 12. SEC_SYNC Set-Up Time (td3, td4)
VBST = 60 V SEC_SYNC 5 V/div VLX = 48 V DH 5 V/div VCC = 12 V DL 5 V/div GND
Figure 13.
SEC_SYNC Set-Up Time (td1, td2)
VCC = 12 V
GND
VCC = 12 V
SEC_SYNC 5 V/div
GND
100 ns/div
100 ns/div
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Document Number: 72098 S-03639--Rev. B, 20-Mar-03
SI9123
New Product
LOGIC REPRESENTATIVE APPLICATION SCHEMATIC
1N4001 5 V Reg +5 V 5V GND
Vishay Siliconix
D3 U1 VAUX VAUX
1 VIN VOUT 3 Tab
4
0.1 mF +5 V D1B BAT54S D1A BAT54S GND TXOUT C35 R31 D1B BAT54S D1A BAT54S R32 1 kW +5 V 4 3 C36 10 mF L2A PRE Q Q GND
1
C36
C37 0.1 mF
OUTP
R33 470 W +5 V
0.1 mF 10 W
CLX 2D 1 CLR 74HC74 +5 V 10 L2A PRE CLX D CLR 74HC74
5 6
L3A 3 2 74AC32 L3B 9 8 5 74AC32 +5 V R37 1 kW 3 6
L4A 1 2 74AC00 GATEA
4 5
L4B GATEB
OUTN
+5 V R34 GND 470 W D1A BAT54S D1B BAT54S
11 12 13
Q Q
74AC00
R35 5 kW R36 5 kW
1 2
Q5 2N3904
VOUT
Figure 14.
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
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15
REPRESENTATIVE APPLICATION SCHEMATIC DIAGRAM
SI9123
16
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Vishay Siliconix
VINEXT + C1 1 mF 100 V C10 4.7 mF 16 V R27 1.4 kW C2 1 mF 50 V 16 VIN 2 3 C29 470 pF C9 1 mF 4 5 R1 90 kW R6 35 kW C30 200 - 800 pF 6 7 8 C11 1 nF ROSC EP PGND BST Q1 5, 6, Si4486EY 7, 8 C8 0.1 mF 4 14 Q2 13 12 4 1, 2, 3 R10 VINDET CS1 SS CS2 C14 22 nF 10 9 2 kW R12 0.02 W C12 15 pF R11 2 kW C5 1 mF 50 V D3 10MQ100N C20 680 pF 100 V 7, 8 3, 4 8:2:2 EPC19 9, 10 1, 2, 3 5, 6 5, 6, 7, 8 D2 10MQ100N T1 1, 2 + C3 15 mF 50 V + C4 15 mF 50 V +
C15 1 nF 5, 6, 7, 8 Q3
R14 3.3 W 4 1, 2, 3
D11 SMAJ12CA
1
D1
R16 10 W D8 DAS19
3
BAS19 1
Si4886DY
4 5, 6, 7, 8 1, 2, 3 Q4 T3 LEP-9080 4 7, 8, 9 Q5 1, 2, 3 D6 MBR0520 D7 30BQ040 5 1:3 1, 2, 3
SI9123
VCC VREF GND DH LX DL
15
Si4486EY
R13 15 W 1W
11, 12
D4 D5
Si4886DY
30BQ040
SEC_SYNC 11
30BQ040 5, 6, 7, 8
Si4886DY
R5 10 kW
3.3 V 4 5, 6, 7, 8 1, 2, 3 + C22 47 mF 10 V C23 + 47 mF 10 V C24 + 47 mF 10 V C32 + 10 mF 6.3 V VOUT
New Product
OUT_GND + C6 + C7 15 mF 15 mF 50 V 50 V + Q6
R7 GND 2 kW
Si4886DY
C16 1 nF
4 R15 3.3 W
Figure 15
U2 MOC207 6 5 R24 1 MW C34 0.1 mF VIN 7 7 6 U3 LM7301 VIN + 1 2 R19 2.2 kW
LOGIC C21 1 mF T2 OUTP OUTN 2:1 EP7 R26 5.6 kW C28 1 nF C25 33 nF R18 300 kW VOUT TX_OUT 5V GATEA GATEB VAUX GND 1 Q7A Q7B 3
2 Q8B 3
2
4
4
6 1 Q8A
6
Si3552DV
5
Si3552DV
5
R22 33 kW
Document Number: 72098 S-03639--Rev. B, 20-Mar-03
+ 4
3 2 R25 2 kW C26 0.1 mF C27 0.1 mF 1 2 U4 LM4041C1M3 - 1.2 3 OUT_GND + C19 4.7 mF 16 V C33 0.1 mF
R23 18.6 kW

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