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| MPE603EEC/D (Motorola Order Number) 5/1999 Rev. 1 TM Advance Information EC603e TM Embedded RISC Microprocessor (PID6) Hardware Specifications The EC603e microprocessor from Motorola is an implementation of the PowerPCTM family of reduced instruction set computing (RISC) microprocessors. The EC603e microprocessor for embedded systems is functionally equivalent to the MPC603e with the exception of the floating-point unit which is not supported on the EC603e microprocessor. The EC603e microprocessor is implemented in both a 2.5-volt version (PID 0007t EC603e microprocessor, abbreviated as PID7t) and a 3.3-volt version (PID 0006 EC603e microprocessor, abbreviated as PID6). This document describes the pertinent physical characteristics of the PID6. For functional characteristics of the processor, refer to the MPC603e & EC603e RISC Microprocessors User's Manual. This document contains the following topics: Topic Page Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Document Revision History" Section 1.10, "Ordering Information" 2 3 4 4 14 16 20 24 30 30 The PowerPC name, the PowerPC logotype, PowerPC 603, and PowerPC 603e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. (c) Motorola Inc., 1999. All rights reserved. Portions hereof (c) International Business Machines Corporation, 1991-1999. All rights reserved. To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/. 1.1 Overview The PID6 implementation of the EC603e microprocessor is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. The PID6 implements the 32-bit portion of the PowerPC architecture specification, which provides 32-bit effective addresses, and integer data types of 8, 16, and 32 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The PID6 provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power consumed by the processor. The fourth is a dynamic power management mode that causes the functional units in the PID6 to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. The PID6 is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the PID6 makes completion appear sequential. The PID6 integrates four execution units--an integer unit (IU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for PID6-based systems. Most integer instructions execute in one clock cycle. The PID6 provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The PID6 also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority. The PID6 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The PID6 interface protocol allows multiple masters to compete for system resources through a central external arbiter. The PID6 provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. The PID6 supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O. The PID6 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. 2 EC603e Microprocessor Hardware Specifications (PID6) 1.2 Features This section summarizes features of the PID6's implementation of the PowerPC architecture. Major features of the PID6 are as follows: * High-performance, superscalar microprocessor -- As many as three instructions issued and retired per clock -- As many as five instructions in execution per clock -- Single-cycle execution for most instructions Four independent execution units and one register file -- BPU featuring static branch prediction -- A 32-bit IU -- LSU for data transfer between data cache and GPRs -- SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions -- Thirty-two GPRs for integer operands High instruction and data throughput -- Zero-cycle branch capability (branch folding) -- Programmable static branch prediction on unresolved conditional branches -- Instruction fetch unit capable of fetching two instructions per clock from the instruction cache -- A six-entry instruction queue that provides lookahead capability -- Independent pipelines with feed-forwarding that reduces data dependencies in hardware -- 16-Kbyte data cache--four-way set-associative, physically addressed; LRU replacement algorithm -- 16-Kbyte instruction cache--four-way set-associative, physically addressed; LRU replacement algorithm -- Cache write-back or write-through operation programmable on a per page or per block basis -- BPU that performs CR lookahead operations -- Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size -- A 64-entry, two-way set-associative ITLB -- A 64-entry, two-way set-associative DTLB -- Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks -- Software table search operations and updates supported through fast-trap mechanism -- 52-bit virtual address; 32-bit physical address Facilities for enhanced system performance -- A 32- or 64-bit split-transaction external data bus with burst transfers -- Support for one-level address pipelining and out-of-order bus transactions Integrated power management -- Low-power 3.3-volt design -- Internal processor/bus clock multiplier that provides 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1 ratios -- Three power saving modes: doze, nap, and sleep -- Automatic dynamic power reduction when internal functional units are idle In-system testability and debugging features through JTAG boundary-scan capability * * * * * EC603e Microprocessor Hardware Specifications (PID6) 3 1.3 General Parameters The following list provides a summary of the general parameters of the PID6. Technology Die size Transistor count Logic design Package Power supply 0.5 CMOS, four-layer metal 11.67 mm x 8.4 mm (98 mm2) 2.6 million Fully-static Surface mount 240-pin ceramic quad flat pack (CQFP) or 255-pin ceramic ball grid array (CBGA) 3.3 5% V dc 1.4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PID6. 1.4.1 DC Electrical Characteristics The tables in this section describe the PID6 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Storage temperature range Notes: 1. Functional operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd by more than 2.5 V at any time including during power-on reset. 3. Caution: OVdd must not exceed Vdd/AVdd by more than 2.5 V at any time including during power-on reset. 4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time including during power-on reset. Vdd AVdd OVdd Vin Tstg Symbol Value -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 5.5 -55 to 150 Unit V V V V C 4 EC603e Microprocessor Hardware Specifications (PID6) Table 2 provides the recommended operating conditions for the PID6. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Die-junction temperature Note: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Vdd AVdd OVdd Vin Tj Symbol Value 3.3 165mv 3.3 165mv 3.3 165mv -0.3 to 5.5 0 to 105 Unit V V V V C Table 3 provides the packages thermal characteristics for the PID6. Table 3. Package Thermal Characteristics Characteristic Wire-bond CQFP package die junction-to-case thermal resistance (typical) Wire-bond CQFP package die junction-to-lead thermal resistance (typical) CBGA package die junction-to-case thermal resistance (typical) CBGA package die junction-to-ball thermal resistance (typical) Symbol JC JB JC JB Value 2.2 18.0 0.08 2.8 Rating C/W C/W C/W C/W Note: Refer to Section 1.8, "System Design Information," for more details about thermal management. Table 4 provides the DC electrical characteristics for the PID6. Table 4. DC Electrical Specifications At recommended operating conditions. See Table 2 Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = 3.465 V Vin = 5.5 V Hi-Z (off-state) leakage current, Vin = 3.465 V Vin = 5.5 V Output high voltage, IOH = -9 mA Symbol VIH VIL CVIH CVIL Iin Iin ITSI ITSI VOH Min 2.0 -0.3 2.4 -0.3 -- -- -- -- 2.4 Max 5.5 0.8 5.5 0.4 10 245 10 245 -- Unit V V V V A A A A V Notes 1 1 1 1 1 EC603e Microprocessor Hardware Specifications (PID6) 5 Table 4. DC Electrical Specifications (Continued) At recommended operating conditions. See Table 2 Characteristic Output low voltage, IOL = 14 mA Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY) Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) Notes: Symbol VOL Cin Cin Min -- -- -- Max 0.4 10.0 15.0 Unit V pF pF Notes 2 2 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals. 2. Capacitance is periodically sampled rather than 100% tested. Table 5 provides the power consumption for the PID6. Table 5. Power Consumption At recommended operating conditions. See Table 2 CPU Clock: SYSCLK Full-On Mode (DPM Enabled) Typical Max. Doze Mode Typical Nap Mode Typical Sleep Mode Typical Sleep Mode--PLL Disabled Typical 5 40 70 1.0 3.2 4.0 Processor (CPU) Frequency Unit 100 MHz 133.33 MHz Notes 4.2 5.3 W W 1, 3 1, 2 1.3 W 1, 2 85 mW 1, 2 50 mW 1, 2 6 mW 1, 2 Sleep Mode--PLL and SYSCLK Disabled Typical Notes: 1. These values apply for all valid bus ratios (PLL_CFG[0-3] settings). The values do not include I/O supply power (OVdd) or PLL supply power (AVdd). OVdd power is system dependent, but is typically <10% of Vdd power. Worst-case power consumption for AVdd = 15 mw. 2. Maximum power is measured at Vdd = 3.465 V using a worst-case instruction mix. 3. Typical power is an average value measured at Vdd = AVdd = OVdd = 3.3 V in a system executing typical applications and benchmark sequences. 3 3 mW 1, 2 6 EC603e Microprocessor Hardware Specifications (PID6) 1.4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the PID6. After fabrication, parts are sorted by maximum processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. These specifications are for 100 and 133.33 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency; see Section 1.10, "Ordering Information." 1.4.2.1 Clock AC Specifications Table 6 provides the clock AC timing specifications as defined in Figure 1. Table 6. Clock AC Timing Specifications At recommended operating conditions. See Table 2 100 MHz Num Characteristic Min Processor frequency VCO frequency SYSCLK (bus) frequency 1 2,3 4 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at 1.4 V SYSCLK jitter Internal PLL relock time Notes: 50 100 16.67 15.0 -- 40.0 -- -- Max 100 266.66 66.67 60.0 2.0 60.0 150 100 133.33 MHz Unit Min 50 100 16.67 15.0 -- 40.0 -- -- Max 133.33 266.66 66.67 60.0 2.0 60.0 150 100 MHz MHz MHz ns ns % ps s 2 3 4 3, 5 1 1 Notes 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8, "System Design Information," for valid PLL_CFG[0-3] settings. 2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. Cycle-to-cycle jitter, and is guaranteed by design. 5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. EC603e Microprocessor Hardware Specifications (PID6) 7 Figure 1 provides the SYSCLK input timing diagram. 1 4 4 2 3 CVih VM VM VM CVil SYSCLK VM = Midpoint Voltage (1.4 V) Figure 1. SYSCLK Input Timing Diagram 1.4.2.2 Input AC Specifications Table 7 provides the input AC timing specifications for the PID6 as defined in Figure 2 and Figure 3. Table 7. Input AC Timing Specifications At recommended operating conditions. See Table 2 100 MHz Num 10a 10b 10c 11a 11b 11c Notes: Characteristic Min Address/data/transfer attribute inputs valid to SYSCLK (input setup) All other inputs valid to SYSCLK (input setup) Mode select inputs valid to HRESET (input setup) (for DRTRY, QACK and TLBISYNC) SYSCLK to address/data/transfer attribute inputs invalid (input hold) SYSCLK to all other inputs invalid (input hold) HRESET to mode select inputs invalid (input hold) (for DRTRY, QACK, and TLBISYNC) 3.0 5.0 8*tsysclk 1.0 1.0 0 Max -- -- -- -- -- -- 133.33 MHz Unit Min 3.0 5.0 8*tsysclk 1.0 1.0 0 Max -- -- -- -- -- -- ns ns ns ns ns ns 2 3 4,5, 6,7 2 3 4,6,7 Notes 1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK (see Figure 2). Both input and output timings are measured at the pin. 2. Address/data/transfer attribute input signals are composed of the following--A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other input signals are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds. 6. These values are guaranteed by design, and are not tested. 7. This specification is for configuration mode select only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. 8 EC603e Microprocessor Hardware Specifications (PID6) Figure 2 provides the input timing diagram for the PID6. SYSCLK 10a 10b VM 11a 11b ALL INPUTS VM = Midpoint Voltage (1.4 V) Figure 2. Input Timing Diagram Figure 3 provides the mode select input timing diagram for the PID6. HRESET VM 10c 11c MODE PINS VM = Midpoint Voltage (1.4 V) Figure 3. Mode Select Input Timing Diagram EC603e Microprocessor Hardware Specifications (PID6) 9 1.4.2.3 Output AC Specifications Table 8 provides the output AC timing specifications for the PID6 as defined in Figure 4. Table 8. Output AC Timing Specifications1 At recommended operating conditions. See Table 2. CL = 50 pF2 100 MHz Num 12 13a 13b 14a 14b 15 16 17 18 19 20 21 Notes: Characteristic Min SYSCLK to output driven (output enable time) SYSCLK to output valid (5.5 V to 0.8 V--TS, ABB, ARTRY, DBB) SYSCLK to output valid (TS, ABB, ARTRY, DBB) SYSCLK to output valid (5.5 V to 0.8 V--all except TS, ABB, ARTRY, DBB) SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all except ARTRY, ABB, DBB) SYSCLK to ABB, DBB, high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable Maximum delay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge 1.0 -- -- -- -- 1.5 -- -- -- 0.2 * tsysclk+1.0 -- -- Max -- 11.0 10.0 13.0 11.0 -- 9.5 1.2 9.0 -- 1.2 2.25 133.33 MHz Unit Min 1.0 -- -- -- -- 1.5 -- -- -- 0.2 * tsysclk+1.0 -- -- Max -- 11.0 10.0 13.0 11.0 -- 9.5 1.2 9.0 -- 1.2 2.25 ns ns ns ns ns ns ns tsysclk ns ns tsysclk tsysclk 3,5,8 5,8 5,8 5,7 4 6 4 6 3 Notes 1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4). 2. All maximum timing specifications assume CL = 50 pF. 3. This minimum parameter assumes CL = 0 pF. 4. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5 V CMOS levels instead of 3.3 V CMOS levels). 5. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V. 7. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 8. Nominal precharge width for ARTRY is 1.0 tsysclk. 10 EC603e Microprocessor Hardware Specifications (PID6) Figure 4 provides the output timing diagram for the PID6. SYSCLK VM 14 15 12 16 VM VM ALL OUTPUTS (Except TS, ABB, DBB, ARTRY) 13 13 15 16 TS 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4 V) Figure 4. Output Timing Diagram 1.4.3 JTAG AC Timing Specifications Table 9 provides the JTAG AC timing specifications as defined in Figure 5 through Figure 8. Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) At recommended operating conditions. See Table 2., CL = 50 pF Num Characteristic TCK frequency of operation 0 Min 16 -- -- 3 -- -- -- -- 25 24 Max Unit MHz ns ns ns ns ns ns ns ns ns Notes 1 2 3 4 5 6 7 8 9 TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time TCK to output data valid TCK to output high impedance 62.5 25 0 13 40 6 27 4 3 1 2 2 3 3 EC603e Microprocessor Hardware Specifications (PID6) 11 Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) At recommended operating conditions. See Table 2., CL = 50 pF Num 10 11 12 13 Notes: Characteristic TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance 0 25 4 3 Min -- -- 24 15 Max ns ns ns ns Unit Notes 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test signal input timing with respect to TCK. 3. Non-test signal output timing with respect to TCK. Figure 5 provides the JTAG clock input timing diagram. 1 2 2 VM VM TCK 3 3 VM VM = Midpoint Voltage (1.4 V) Figure 5. JTAG Clock Input Timing Diagram Figure 6 provides the TRST timing diagram. TCK 4 VM TRST 5 Figure 6. TRST Timing Diagram 12 EC603e Microprocessor Hardware Specifications (PID6) Figure 7 provides the boundary-scan timing diagram. TCK VM VM 6 7 Data Inputs 8 Input Data Valid Data Outputs 9 Output Data Valid Data Outputs 8 Data Outputs Output Data Valid Figure 7. Boundary-Scan Timing Diagram Figure 8 provides the test access port timing diagram. TCK VM VM 10 11 TDI, TMS 12 Input Data Valid TDO 13 Output Data Valid TDO 12 TDO Output Data Valid Figure 8. Test Access Port Timing Diagram EC603e Microprocessor Hardware Specifications (PID6) 13 1.5 Pin Assignments The following sections contain the pinout diagrams for the PID6. Note that the PID6 is offered in both ceramic quad flat pack (CQFP) and ceramic ball grid array (CBGA) packages. 1.5.1 Pinout Diagram for the CQFP Package Figure 9 contains the pinout diagram of the CQFP package for the PID6. OVDD GND OGND CI WT QACK TBEN TLBISYNC RSRV AP0 AP1 OVDD OGND AP2 AP3 CSE0 TC0 TC1 OVDD CLK_OUT OGND BR APE DPE CKSTP_OUT CKSTP_IN HRESET PLL_CFG0 SYSCLK PLL_CFG1 PLL_CFG2 AVDD PLL_CFG3 VDD GND LSSD_MODE L1_TSTCLK L2 _TSTCLK TRST TCK TMS TDI TDO TSIZ0 TSIZ1 TSIZ2 OVDD OGND TBST TT0 TT1 SRESET INT SMI MCP TT2 TT3 OVDD GND OGND 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 GBL A1 A3 VDD A5 A7 A9 OGND GND OVDD A11 A13 A15 VDD A17 A19 A21 OGND GND OVDD A23 A25 A27 VDD DBWO DBG BG AACK GND A29 QREQ ARTRY OGND VDD OVDD ABB A31 DP0 GND DP1 DP2 DP3 OGND VDD OVDD DP4 DP5 DP6 GND DP7 DL23 DL24 OGND OVDD DL25 DL26 DL27 DL28 VDD OGND 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 14 OVDD DL29 DL30 DL31 GND DH31 DH30 DH29 OGND OVDD DH28 DH27 DH26 DH25 DH24 DH23 OGND DH22 OVDD DH21 DH20 DH19 DH18 DH17 DH16 OGND DH15 OVDD DH14 DH13 DH12 DH11 DH10 DH9 OGND OVDD DH8 DH7 DH6 DL22 DL21 DL20 OGND OVDD DL19 DL18 DL17 DH5 DH4 DH3 OGND OVDD DH2 DH1 DH0 GND DL16 DL15 DL14 OGND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 TOP VIEW TT4 A0 A2 VDD A4 A6 A8 OVDD GND OGND A10 A12 A14 VDD A16 A18 A20 OVDD GND OGND A22 A24 A26 VDD DRTRY TA TEA DBDIS GND A28 CSE1 TS OVDD VDD OGND DBB A30 DL0 GND DL1 DL2 DL3 OVDD VDD OGND DL4 DL5 DL6 GND DL7 DL8 DL9 OVDD OGND DL10 DL11 DL12 DL13 VDD OVDD Figure 9. Pinout Diagram for the CQFP Package EC603e Microprocessor Hardware Specifications (PID6) 1.5.2 Pinout Diagram for the CBGA Package Figure 10 (in part A) shows the pinout of the CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. Part A 01 02 03 04 A B C D E F G H J K L M N P R T Not to Scale 05 06 07 08 09 10 11 12 13 14 15 16 Part B Substrate Assembly Encapsulant View Die Figure 10. Pinout of the CBGA Package as Viewed from the Top Surface EC603e Microprocessor Hardware Specifications (PID6) 15 1.6 Pinout Listings The following sections contain the pinout listings for the PID6 CQFP and CBGA packages. 1.6.1 Pinout Listing for the CQFP Package Table 10 provides the pinout listing for the PID6 CQFP package. Table 10. Pinout Listing for the 240-pin CQFP Package Signal Name A[0-31] Pin Number 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 28 36 231, 230, 227, 226 218 32 209 27 219 237 221 215 216 225, 150 145 153 26 25 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 38, 40, 41, 42, 46, 47, 48, 50 217 156 1 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 214 188 Active High I/O I/O AACK ABB AP[0-3] APE ARTRY AVDD BG BR CI CLK_OUT CKSTP_IN CKSTP_OUT CSE[0-1]1 DBB DBDIS DBG DBWO DH[0-31] Low Low High Low Low High Low Low Low -- Low Low High Low Low Low Low High Input I/O I/O Output I/O Input Input Output Output Output Input Output Output I/O Input Input Input I/O DL[0-31] High I/O DP[0-7] DPE DRTRY GBL GND HRESET INT High Low Low Low Low Low Low I/O Output Input I/O Input Input Input 16 EC603e Microprocessor Hardware Specifications (PID6) Table 10. Pinout Listing for the 240-pin CQFP Package (Continued) Signal Name LSSD_MODE2 L1_TSTCLK2 L2_TSTCLK2 MCP OGND OVDD3 PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC[0-1] TCK TDI TDO TEA TLBISYNC TMS TRST TSIZ[0-2] TS TT[0-4] VDD3 WT Notes: 1. There are two CSE signals in the EC603e microprocessor--CSE0 and CSE1. The XATS signal in the PowerPC 603TM microprocessor is replaced by the CSE1 signal in the PID6. 2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 205 204 203 186 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 213, 211, 210, 208 235 31 232 187 189 212 155 234 192 224, 223 201 199 198 154 233 200 202 197, 196, 195 149 191, 190, 185, 184, 180 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 236 Pin Number Active Low -- -- Low Low High High Low Low Low Low Low -- Low High Low High -- High High Low Low High Low High Low High High Low I/O Input Input Input Input Input Input Input Input Output Output Input Input Input Input Input I/O Output Input Input Output Input Input Input Input I/O I/O I/O Input Output EC603e Microprocessor Hardware Specifications (PID6) 17 1.6.2 Pinout Listing for the CBGA Package Table 11 provides the pinout listing for the PID6 CBGA package. Table 11. Pinout Listing for the 255-pin CBGA Package Signal Name A[0-31] Pin Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04 J04 A10 L01 B06 E01 D08 A06 D07 B01, B05 J14 N01 H15 G04 P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 F01 C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 A07 B15 1 Active High I/O I/O AACK ABB AP[0-3] APE ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBB DBG DBDIS DBWO DH[0-31] Low Low High Low Low -- Low Low Low Low Low -- High Low Low Low Low High Input I/O I/O Output I/O -- Input Output Output Input Output Output Output I/O Input Input Input I/O DL[0-31] High I/O DP[0-7] DPE DRTRY GBL GND High Low Low Low -- I/O Output Input I/O -- HRESET INT L1_TSTCLK Low Low -- Input Input Input D11 18 EC603e Microprocessor Hardware Specifications (PID6) Table 11. Pinout Listing for the 255-pin CBGA Package (Continued) Signal Name L2_TSTCLK 1 LSSD_MODE 1 MCP NC OVDD PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC[0-1] TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD2 Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. Future members of the 603 family may use different OVdd and Vdd input levels. D12 B10 C13 B07, B08, C03, C06, C08, D05, D06, F03, H04, J16 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 A08, B09, A09, D09 D03 J03 D01 A16 B14 C09 H14 C02 A14 A02, A03 C11 A11 A12 H13 C04 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 Pin Number Active -- Low Low Low -- High Low Low Low Low Low -- Low High Low High -- High High Low Low High Low Low High High Low -- I/O Input Input Input Input -- Input Input Output Output Input Input Input Input Input I/O Output Input Input Output Input Input Input Input I/O I/O I/O Output -- EC603e Microprocessor Hardware Specifications (PID6) 19 1.7 Package Description The following sections provide the package parameters and the mechanical dimensions for the PID6. 1.7.1 CQFP Package Description The following sections provide the package parameters and mechanical dimensions for the Motorola CQFP package. 1.7.1.1 Package Parameters The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack. Package outline Interconnects Pitch 32 mm x 32 mm 240 0.5 mm 20 EC603e Microprocessor Hardware Specifications (PID6) 1.7.1.2 Mechanical Dimensions of the CQFP Package Figure 11 shows the mechanical dimensions of the Motorola CQFP package. AB I R -H- 2 R G AA H F C A J B *Reduced pin count shown for clarity. 60 pins per side A B C D E F G H J AA AB 1 2 R Pin 240 Pin 1 Min. Max. 30.86 31.75 34.6 BSC 3.75 4.15 0.5 BSC 0.18 0.30 3.10 3.90 0.13 0.175 0.45 0.55 0.25 - 1.80 REF 0.95 REF 2 6 1 7 0.15 REF Notes: 1. BSC--Between Standard Centers. 2. All measurements in mm. D E Die Wire Bonds Ceramic Body Alloy 42 Leads *Not to scale Figure 11. Mechanical Dimensions of the Wire-Bond CQFP Package EC603e Microprocessor Hardware Specifications (PID6) 21 1.7.2 CBGA Package Description The following sections provide the package parameters and mechanical dimensions for the CBGA package. 1.7.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-pin ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 21 mm 255 1.27 mm 2.45 mm 3.00 mm 0.89 mm (35 mil) 22 EC603e Microprocessor Hardware Specifications (PID6) 1.7.2.2 Mechanical Dimensions of the CBGA Package Figure 12 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package. 2X 0.200 A1 CORNER A -E- -T- 0.150 T B P 2X 0.200 -F- N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS DIM MIN MAX MIN MAX A T R P N M L K J H G F E D C B A INCHES 1 2 3 4 5 6 7 8 9 10111213141516 21.000 BSC 21.000 BSC 2.450 0.820 3.000 0.930 0.827 BSC 0.827 BSC 0.096 0.032 0.118 0.036 B C D G K 1.270 BSC 0.790 0.990 0.050 BSC 0.031 0.039 H C H K N P 0.635 BSC 5.000 5.000 16.000 16.000 0.025 BSC 0.197 0.197 0.630 0.630 G 255X K D S 0.300 S T E 0.150 S T F S Figure 12. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package EC603e Microprocessor Hardware Specifications (PID6) 23 1.8 System Design Information This section provides electrical and thermal design recommendations for successful application of the PID6. 1.8.1 PLL Configuration The PID6 PLL, shown in Table 12 for nominal frequencies, is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. Table 12. PLL Configuration CPU Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0-3] Bus-toCore Multiplier 1x 1x 1.5x 2x 2x 2.5x 3x 3.5x 4x Core-toVCO Multiplier 2x 4x 2x 2x 4x 2x 2x 2x 2x Bus 16.67 MHz -- -- -- -- -- -- 50 (100) 58.4 (117) 66.67 (133) Bus 20 MHz -- -- -- -- -- 50 (100) 60 (120) 70 (140) 80 (160) Bus 25 MHz -- -- -- -- 50 (200) 62.5 (125) 75 (150) 87.5 (175) 100 (200) Bus 33.33 MHz -- -- 50 (100) 66.67 (133) 66.67 (266) 83.33 (166) 100 (200) 116.67 (233) 133.33 (266) Bus 40 MHz -- -- 60 (120) 80 (160) -- 100 (200) 120 (240) -- -- Bus 50 MHz 50 (100) 50 (200) 75 (150) 100 (200) -- 125 (250) -- -- -- Bus 60 MHz 60 (120) 60 (240) 90 (180) 120 (240) -- -- -- -- -- Bus 66.67 MHz 66.67 (133) 66.67 (266) 100 (200) 133.33 (266) -- -- -- -- -- 0000 0001 1100 0100 0101 0110 1000 1110 1010 0011 1111 Notes: PLL bypass Clock off 1. PLL_CFG[0-3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PID6; see Section 1.4.2.1, "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the PID6 regardless of the SYSCLK input. 24 EC603e Microprocessor Hardware Specifications (PID6) 1.8.2 PLL Power Supply Filtering The AVdd power signal is provided on the PID6 to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. 10 Vdd 10 F 0.1 F AVdd GND Figure 13. PLL Power Supply Filter Circuit 1.8.3 Decoupling Recommendations Due to the PID6's dynamic power management feature, large address and data buses, and high operating frequencies, the PID6 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PID6 system, and the PID6 itself requires a clean, tightly regulated source of power. Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin of the PID6. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should vary in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values for the Vdd pins--220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OVdd pins--0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). 1.8.4 Connection Recommendations To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. 1.8.5 Pull-up Resistor Requirements The PID6 requires high-resistive (weak: 10 K) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PID6 or other bus master. These signals are--TS, ABB, DBB, ARTRY. In addition, the PID6 has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 K-10 K) if they are used by the system. These signals are--APE, DPE, and CKSTP_OUT. EC603e Microprocessor Hardware Specifications (PID6) 25 During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the PID6 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PID6. It is recommended that these signals be pulled up through weak (10 K) pullup resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are--A[0-31], AP[0-3], TT[0-4], TBST, TSIZ[0-2], and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 Thermal Management Information This section provides thermal management information for the ceramic quad-flat package (CQFP) and the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design--the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods-- adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (CBGA package); see Figure 14. This spring force should not exceed 5.5 pounds of force. WB/C4-CQFP Package Heat Sink CBGA Package Heat Sink Clip Adhesive or Thermal Interface Material Printed-Circuit Board Option Figure 14. Package Exploded Cross-Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the PID6. There are several commercially-available heat sinks for the PID6 provided by the following vendors: Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 Thermalloy 2021 W. Valley View Lane P.O. Box 810839 800-227-0254 (USA/Canada) 401-739-7600 818-842-7277 214-243-4321 26 EC603e Microprocessor Hardware Specifications (PID6) Dallas, TX 75731 Wakefield Engineering 60 Audubon Rd. Wakefield, MA 01880 Aavid Engineering One Kool Path Laconia, NH 03247-0440 617-245-5900 603-528-3400 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.6.1 Internal Package Conduction Resistance For this packaging technology the intrinsic thermal conduction resistance (shown in Table 3) versus the external thermal resistance paths are shown in Figure 15 for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board Radiation External Resistance Convection (Note the internal versus external package resistance) Figure 15. Package with Heat Sink Mounted to a Printed-Circuit Board 1.8.6.2 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 16 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/ oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 14). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. EC603e Microprocessor Hardware Specifications (PID6) 27 2 Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (Kin2/W) 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 16. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: Dow-Corning Corporation Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4850 Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067 AI Technology (e.g. EG7655) 1425 Lower Ferry Rd Trent, NJ 08618 517-496-4000 617-935-4850 216-741-7659 860-571-5100 609-882-2332 28 EC603e Microprocessor Hardware Specifications (PID6) 1.8.6.3 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (jc + int + sa) * Pd Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance Pd is the power consumed by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 2. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. The thermal resistance of the thermal interface material (int) is typically about 1 C/ W. Assuming a Ta of 30 C, a Tr of 5 C, a CQFP package jc = 2.2, and a power consumption (Pd) of 4.5 watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30 C + 5 C + (2.2 C/W + 1.0 C/W + Rsa) * 4.5 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (Rsa) versus airflow velocity is shown in Figure 17. 8 7 Heat Sink Thermal Resistance (C/W) Thermalloy #2328B Pin-fin Heat Sink (25 x28 x 15 mm) 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Figure 17. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity EC603e Microprocessor Hardware Specifications (PID6) 29 Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 C/W, thus Tj = 30C + 5C + (2.2 C/W +1.0 C/W + 7 C/W) * 4.5 W, resulting in a die-junction temperature of approximately 81 C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figureof-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. 1.9 Document Revision History Table 13. Document Revision History Document Revision Rev 1 Substantive Change(s) In Table 6, the minimun processor frequency for the 100 mhz and the 133 mhz parts was changed to 50 mhz. The maximum VCO frequency was changed to 266.66 mhz on and the minimum VCO frequency on the 133 mhz part was changed to 100 mhz. In Table 12 the CPU and VCO frequencies were changed to correspond to the the valid clock specifications as shown in Table 6. 1.10 Ordering Information This section provides the part numbering nomenclature for the PID6. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. Figure 18 provides the Motorola part numbering nomenclature for the PID6. In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original production design. The bus divider may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. 30 EC603e Microprocessor Hardware Specifications (PID6) MPE 603 E XX XXX X X Revision Level (Contact Motorola Sales Office) Product Code Part Identifier Part Modifier (E = Enhanced) Application Modifier (L = Full Spec all modes) Max. Internal Processor Speed Package (FE = Wire-Bond CQFP, RX = Ceramic Ball Grid Array) Figure 18. Motorola Part Number Key EC603e Microprocessor Hardware Specifications (PID6) 31 EC603e and Mfax are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or 1-303-675-2140; World Wide Web Address: http://ldc.nmd.com/ JAPAN: Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd Silicon Harbour Centre 2, Dai King Street Tai Po Industrial Estate Tai Po, New Territories, Hong Kong MfaxTM: RMFAX0@email.sps.mot.com; TOUCHTONE 1-602-244-6609; US & Canada ONLY (800) 774-1848; World Wide Web Address: http://sps.motorola.com/mfax INTERNET: http://motorola.com/sps Technical Information: Motorola Inc. SPS Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. Document Comments: FAX (512) 895-2638, Attn: RISC Applications Engineering. World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/netcomm http://www.motorola.com/HPESD MPE603EEC/D |
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