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ISL95711
Digitally Controlled Potentiometer (XDCPTM)
Data Sheet August 15, 2005 FN8241.2
Terminal Voltage 3V or 5V, 128 Taps I2C Serial Interface
The Intersil ISL95711 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a I2C interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. The wiper terminal can be connected to either end of the resistor array or at any one of the Tap Positions in between, providing 128 steps of resolution between RL and RH. The "position" of the wiper is determined by the value assigned to the volatile Wiper Register (WR). This register has an associated non-volatile Initial Value Register (IVR). The value stored in the IVR will be written into the WR at power-up, allowing wiper position recall after power interruption. The WR and the IVR can be directly written to and read from using standard I2C interface protocol. The device is available in either a 10k or 50k version. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: * Industrial and automotive control * Parameter and bias adjustments * Amplifier bias and control
Features
* Non-Volatile Solid-State Potentiometer * I2C Serial Interface with Hardwire Slave Address Allows Up to Four Devices * DCP Terminal Voltage, from V- to VCC * 128 Wiper Tap Points - Wiper position can be stored in nonvolatile memory and recalled on power-up * 127 Resistive Elements - Typical tempco 50ppm/C - Ratiometric Tempco 4ppm/C - End to end resistance range 20% * Low Power CMOS - Standby current, 1A - Active current, 200A max - VCC = 3V to 5.5V - V- = -3V to -5.5V * High Reliability - Endurance, 200,000 data changes per bit - Register data retention, 50 years * RTOTAL Values = 10k, 50k * Package - 10-lead MSOP - Pb-Free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER ISL95711WIU10Z (Notes 1& 2) ISL95711UIU10Z (Notes 1& 2) NOTES: 1. Add "-T" suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. RESISTANCE OPTION () 10K 50K TEMP RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10-Ld MSOP 10-Ld MSOP
Pinout
ISL95711 (10-LD MSOP)
TOP VIEW
SDA VGND A1 A0
1 2 3 4 5
10 9 8 7 6
SCL VCC RL RW RH
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL95711 Block Diagram
SDA VCC GND SCL 7-BIT WIPER REGISTER (VOLATILE) 127 126 SDA SCL CONTROL AND MEMORY RW RH 7-BIT NONVOLATILE MEMORY 125 124 ONE OF 128 DECODER 2 VSIMPLE BLOCK DIAGRAM A1 A0 STORE AND RECALL CONTROL CIRCUITRY SLAVE ADDRESS DECODE DETAILED BLOCK DIAGRAM 1 0 RL RW RH
A1 A0
TRANSFER GATES
RESISTOR ARRAY
RL
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL SDA VGND A1 A0 RH RW RL VCC SCL active low outputs. Negative supply voltage for the potentiometer wiper control. Ground. A1 and A0 are address select pins used to set the slave address for the I2C serial interface. A1 and A0 are address select pins used to set the slave address for the I2C serial interface. A fixed terminal for one end of the potentiometer resistor. The wiper terminal which is equivalent to the movable terminal of a potentiometer. A fixed terminal for one end of the potentiometer resistor. Positive logic supply voltage Clock input for the I2C serial interface. DESCRIPTION Data I/O for I2C serial interface. It has an open drain output and may be wire or'd with other open drain
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ISL95711
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SDA, SCL, A0, and A1 with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VCC+0.3V Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.03V to 6V RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3V to -5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (Note 1) 10 50 -20 VV- = -5.5V; VCC = +5.5V, wiper current = (VCC-V-)/RTOTAL 70 10/10/ 25 Voltage at pins; V- to VCC 0.1 1 +20 VCC 200 MAX UNIT k k % V pF A
PARAMETER RH to RL resistance
RH to RL resistance tolerance RH,RL RW CH/CL/CW ILkgDCP RH,RL terminal voltage Wiper resistance Potentiometer Capacitance (Note 13) Leakage on RH, RL, RW pins
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded) INL (Note 6) DNL (Note 5) ZSerror (Note 3) FSerror (Note 4) Integral non-linearity Differential non-linearity W, U options -1 -0.5 1 0.5 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/C
Zero-scale error
W option U option
0 0 -4 -2
1 0.5 -1 -1 4
4 2 0 0
Full-scale error
W option U option DCP Register set between 16 to 120d, T = -40C to +85C
TCV Ratiometric Temperature Coefficient (Notes 7, 13)
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) RDNL (Note 10) Roffset (Note 9) TCR (Notes 12, 13) Integral non-linearity Differential non-linearity DCP register set between 20 hex and 7F hex. Monotonic over all tap positions W and U options -1 -0.5 1 0.5 MI (Note 8) MI (Note 8) MI (Note 8) ppm/C
Offset
DCP Register set to 00 hex, W option DCP Register set to 00 hex, U option
0 0
2 0.5 50
5 2
Resistance Temperature Coefficient
DCP register set between 16 and 127d, T = -40C to +85C
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ISL95711
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 IV-1 ICC2 IV-2 ICCSB PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX 200 -100 200 -3 1 1 -5 -2 -10 1 -2.5 2.5 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 3 10 UNITS A A A mA A A A A A s V V V/ms ms
VCC supply current, volatile write/read fSCL = 400kHz;SDA = Open; (for I2C, Active, Read and Volatile Write States only) V- supply current, volatile write/read VCC supply current, non volatile write V- supply current, nonvolatile write VCC current (standby) fSCL = 400kHz;SDA = Open; (for I2C, Active, Read and Volatile Write States only) fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) VCC = +5.5V, I2C Interface in Standby State VCC = +3.6V, I2C Interface in Standby State V- = -5.5V, I2C Interface in Standby State V- = -3.6V, I2C Interface in Standby State
IV-SB
V- current (standby)
ILkgDig tDCP (Note 13) Vpor
Leakage current, at pins SDA, SCL, A0, and A1 DCP wiper response time Power-on recall for both V- and VCC
Voltage at pin from GND to VCC SCL falling edge of last bit of DCP Data Byte to wiper change VVCC
V-Ramp tD (Note 13)
V- ramp rate Power-up delay
EEPROM SPECS EEPROM Endurance EEPROM Retention SERIAL INTERFACE SPECS VIL VIH Hysteresis VOL Cpin (Note 15) fSCL tIN tAA tBUF A0, A1, SDA, and SCL input buffer LOW voltage A0, A1, SDA, and SCL input buffer HIGH voltage SDA and SCL input buffer hysteresis SDA output buffer LOW voltage, sinking 4mA A0, A1, SDA, and SCL pin capacitance SCL frequency Pulse width suppression time at SDA and SCL inputs SCL falling edge to SDA output data valid Time the bus must be free before the start of a new transmission Clock LOW time Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. Measured at the 30% of VCC crossing. 1300 -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 50 900 0.3*VCC VCC+ 0.3 V V V V pF kHz ns ns ns Temperature 75C 200,000 50 Cycles Years
tLOW
1300
ns
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ISL95711
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHD:STO tDH tR (Note 15) tF (Note 15) Cb (Note 15) Rpu (Note 15) tWC (Notes 14) tSU:A tHD:A PARAMETER Clock HIGH time START condition setup time START condition hold time Input data setup time Input data hold time STOP condition setup time STOP condition setup time Output data hold time SDA and SCL rise time SDA and SCL fall time Capacitive loading of SDA or SCL SDA and SCL bus pull-up resistor offchip Non-volatile Write cycle time A0, A1 setup time A0, A1 hold time Before START condition After STOP condition 600 600 TEST CONDITIONS Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k. MIN 600 600 600 100 0 600 600 0 20 + 0.1 * Cb 20 + 0.1 * Cb 10 1 250 250 400 TYP (Note 1) MAX UNITS ns ns ns ns ns ns ns ns ns ns pF k
12
20
ms ns ns
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
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ISL95711 A0, A1 Pin Timing
START STOP
SCL
Clk 1
SDA IN tSU:A A0, A1
tHD:A
NOTES: 1. Typical values are for TA = 25C and 5V supply voltage. 2. LSB: [V(RW)127 - V(RW)0] / 127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = (V(RW)0 - V-) / LSB. 4. FS error = [V(RW)127 - VCC] / LSB. 5. DNL = [V(RW)i - V(RW)i-1] / LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i - (i * LSB - V(RW)0) for i = 1 to 127. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 7. TC V = --------------------------------------------------------------------------------------------- x ---------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C for i = 16 to 120 decimal. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 - R0| / 127. R127 and R0 are the measured resistances for the DCP register set to 127d and 0 respectively. 9. Roffset = R0 / MI, when measuring between RW and RL. Roffset = R127 / MI, when measuring between RW and RH. 10. RDNL = (Ri - Ri-1) / MI, for i = 16 to 127. 11. RINL = [Ri - (MI * i) - R0] / MI, for i = 16 to 127. [ Max ( Ri ) - Min ( Ri ) ] 10 12. TC R = --------------------------------------------------------------- x ---------------[ Max ( Ri ) + Min ( Ri ) ] 2 125C for i = 16 to 127d. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. 14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
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ISL95711 Test Circuit
TEST POINT
address serial data stream must be made with the Address input pins in order to initiate communication with the ISL95711. A maximum of 4 ISL95711 devices may occupy the I2C serial bus.
RW FORCE CURRENT
Principles of Operation
The ISL95711 is an integrated circuit incorporating one DCP with it's associated register, non-volatile memory, and the I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered-down, the last value stored in the IVR will be maintained in the nonvolatile memory. When power is restored, the contents of the IVR are recalled and the wiper is set to that value. The ISL95711 has dual supplies, VCC and V-. For proper operation of the chip, it is recommended both power supplies ramp up simultaneously to their final values within 20ms. The chip design gives priority to the V- supply stabilization and then looks at VCC stabilization. As the Vsupply goes below -2.5V, the RW pin goes to the default code of 64. As VCC also exceeds 2.5V (after V- < -2.5V), the RW pin goes to the code stored in the EEPROM memory value (this is referred as power on recall).
Equivalent Circuit
RTOTAL RH CH CW CL RL
RW
Pin Descriptions
Potentiometer Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL95711 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RH are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127, the wiper will be closest to RH, and with the WR set to 00, the wiper is closest to RL RW Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for the I2C interface. It receives device address, operation code, wiper register address and data from a I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. SDA requires an external pull-up resistor, since it's an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since it's an open drain input. DEVICE ADDRESS (A1-A0) The Address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal is controlled by a 7-bit volatile Wiper Register (WR). When the WR contains all zeroes (00h), the wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR contains all ones (7Fh), the wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (7Fh), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95711 is being powered up, the WR is reset to 40h (64 decimal), which locates the RW at the center
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ISL95711
between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading (~ 2.5V), the ISL95711 reads the value stored on a non-volatile Initial Value Register (IVR) and loads it into the WR. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections. device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL95711 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 1). On power-up of the ISL95711 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95711 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 1). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 1). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 2). The ISL95711 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95711 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1, and A0. The LSB is in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation. (See Table 2.)
TABLE 2. IDENTIFICATION BYTE FORMAT Logic values at pins A1, and A0 respectively 0 (MSB) 1 0 1 0 A1 A0 R/W (LSB)
Memory Description
The ISL95711 contains 1 non-volatile byte know as the Initial Value Register (IVR). It is accessed by the I2C interface operations with Address 00h. The IVR contains the value which is loaded into the Volatile Wiper Register (WR) at power-up. The volatile WR, and the non-volatile IVR of a DCP are accessed with the same address. The Access Control Register (ACR) determines which byte at address 00h is accessed (IVR or WR). The volatile ACR must be set as follows: When the ACR is all zeroes, which is the default at powerup: * A read operation to address 0 outputs the value of the non-volatile IVR. * A write operation to address 0 writes the same value to the WR and IVR of the corresponding DCP. When the ACR is 80h: * A read operation to address 0 outputs the value of the volatile WR. * A write operation to address 0 only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. 00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2.
TABLE 1. MEMORY MAP ADDRESS 2 1 0 IVR NON-VOLATILE Reserved WR VOLATILE ACR
WR: Wiper Register, IVR: Initial value Register.
The ISL95711 is pre-programmed with 40h in the IVR.
I2C Serial Interface
The ISL95711 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the 8
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ISL95711 Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95711 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95711 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95711 enters its standby state (See Figure 3). The byte at address 02h determines if the Data Byte is to be written to volatile or both volatile and non-volatile. (See "Memory Description" on page 8.) received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 4). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL95711 responds with an ACK; then the ISL95711 transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 4). The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory. (See "Memory Description".)
Data Protection
A STOP condition acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
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ISL95711
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL95711
0 1 0 1 0 A1 A0 0 A C K
000000
0 A C K A C K
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W=1
A C K
A C K
S T O P
SIGNAL AT SDA
0 1 0 1 0 A1 A0 0 A C K
000000
0 A C K
0 1 0 1 0 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 4. READ SEQUENCE
Communicating with the ISL95711
There are 3 register addresses in the ISL95711, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the non-volatile Initial Value Register (IVR), and the volatile Wiper Register (WR). Address 02h contains only a volatile word and is used as a pointer to either the IVR or WR. See Table 1.
The non-volatile IVR stores the power-up value of the wiper. On power-up, the contents of the IVR are transferred to the WR. To write to the IVR, first address 02h is set to data 00h, then the data is written. Writing a new value to the IVR register will set a new power-up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. So, if a new value is loaded into the IVR, not only will the non-volatile IVR change, but the WR will also contain the same value after the write, and the wiper position will change. Reading from the IVR will not change the WR, if its contents are different.
Register Descriptions: Access Control
The Access Control Register (ACR) is volatile and is at address 02h. It is 8-bits, and only the MSB is significant, all other bits should be zero (0). The ACR controls which word is accessed at register 00h as follows: 00h = Nonvolatile IVR 80h = Volatile WR All other bits of the ACR should be written to as zeros. Only the MSB can be either 0 or 1. Power-up default for this address is 00h.
Register Description: IVR and WR
The ISL95711 has a single potentiometer. The wiper of the potentiometer is controlled directly by the WR. Writes and reads can be made directly to this register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting address 02h to data 80h, then writing the data.
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Example 1 Writing a new value (77h) to the IVR:
Write to ACR first 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 A A 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 A A Then, write to IVR
NOTE: The WR will also reflect this new value since both registers get written to at the same time)
Example 2 Reading from the WR:
Write to the ACR first (to index the WR) 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 A A A 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 1 0 x 0 0 x A A 1 0 0 0 0 0 0 0 A Then, Set the WR address Read from the WR
NOTE: A = acknowledge, x = data bit read
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ISL95711 MSOP Packaging Information
10 Lead MSOP, Package Code
0.0106 [0.27] 0.0067 [0.17] 10 9 8 7 6
4
0.0106 [0.27] 0.0067 [0.17] WITH PLATING (S) 0.0091 [0.23] 0.0051 [0.13] WITH PLATING 0.0080 [0.203] REF
4
0.1970 [5.00] 0.1890 [4.80]
0.0050 [0.127]
1
2
3
4
5
BASE METAL
0.0197 [0.50] BSC
SECTION A-A 0.1220 [3.10] 0.1142 [2.90] 0.0433 [1.10] MAX. 2 0.0374 [0.95] 0.0295 [0.75] 0.0098 [0.25] GAUGE PLANE 0.1220 [3.10] 0.1142 [2.90]
3 A
0.1220 [3.10] 0.0059 [0.15] 0.0020 [0.05] 0.0039 [0.10] MAX. (S) 0.1142 [2.90] (S) 0.0276 [0.70] 0.0157 [0.40]
3
0-6 A
NOTES: 1. Package dimensions conform to JEDEC specification MO-187BA. 2.
2 Does not include mold flash, protrusion or gate burrs, mold flash protrusions or gate burrs shall not exceed 0.15 mm per side. 3 4
3. 4.
Does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.8 mm.
5. Lead span/stand-off height/coplanarity are considered as special characteristics. 6. Controlling dimensions in inches [mm].
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN8241.2 August 15, 2005

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