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GS71116ATP/J/U
SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features
* Fast access time: 7, 8, 10, 12 ns * CMOS low power operation: 145/125/100/85 mA at minimum cycle time * Single 3.3 V power supply * All inputs and outputs are TTL-compatible * Byte control * Fully static operation * Industrial Temperature Option: -40 to 85C * Package line up J: 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package GP: Pb-Free 400 mil, 3244-pin TSOP Type II package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package GU: Pb-Free 6 mm x 8 mm Fine Pitch Ball Grid Array package * Pb-Free TSOP-II and FP-BGA packages available
64K x 16 1Mb Asynchronous SRAM
7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS
SOJ 64K x 16-Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
Top view
44-pin SOJ
Description
The GS71116A is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71116A is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions Symbol
A0-A15 DQ1-DQ16 CE LB UB WE OE VDD VSS NC
Package J
Description
Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect
Rev: 1.07 12/2004
1/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Fine Pitch BGA 64K x 16-Bump Configuration
1 2 3 4 5 6
A B C D E F G H
LB DQ16
OE UB
A0 A3 A5 NC NC A8 A10 A13
A1 A4 A6 A7 NC A9 A11 A14
A2 CE DQ2 DQ4 DQ5 DQ7 WE A15
NC DQ1 DQ3
DQ14 DQ15
VSS DQ13 VDD DQ12
DQ11 DQ10 DQ9 NC NC A12
VDD VSS
DQ6 DQ8 NC
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U) Top View
TSOP-II 64K x 16-Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
Top view
44-pin TSOP II
Package TP
Rev: 1.07 12/2004
2/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A15 CE WE Control OE UB _____
Column Decoder
I/O Buffer
DQ1
DQ16
Truth Table CE
H
OE
X
WE
X
LB
X L
UB
X L H L L H L X H
DQ1 to DQ8
Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z
DQ9 to DQ16
Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z
VDD Current
ISB1, ISB2
L
L
H
L H L
L
X
L
L H
IDD
L L Note: X: "H" or "L"
H X
H X
X H
Rev: 1.07 12/2004
3/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Absolute Maximum Ratings Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) 0.7 -55 to 150
Unit
V V V W
oC
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions Parameter
Supply Voltage for -7/-8/-10/-12 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VIH VIL TAc TAI
Min
3.0 2.0 -0.3 0 -40
Typ
3.3 -- -- -- --
Max
3.6 VDD +0.3 0.8 70 85
Unit
V V V
o
C C
o
Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than -2 V and not exceed 20 ns.
Capacitance Parameter
Input Capacitance Output Capacitance
Symbol
CIN COUT
Test Condition
VIN = 0 V VOUT = 0 V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA = 25C, f = 1 MHz 2. These parameters are sampled and are not 100% tested.
Rev: 1.07 12/2004
4/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
DC I/O Pin Characteristics Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL ILO VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = -4 mA ILO = +4 mA
Min
-1 uA -1 uA 2.4
Max
1uA 1uA
0.4V
Power Supply Currents
Parameter Symbol Test Conditions
CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2 V All other inputs VDD - 0.2 V or 0.2 V
0 to 70C 7 ns 8 ns 10 ns 12 ns 7 ns
-40 to 85C 8 ns 10 ns 12 ns
Operating Supply Current
IDD
145 mA 125 mA 100 mA
85 mA
150 mA
130 mA 105 mA
90 mA
Standby Current
ISB1
25 mA
20 mA
20 mA
15 mA
30 mA
25 mA
25 mA
20 mA
Standby Current
ISB2
2 mA
5 mA
Rev: 1.07 12/2004
5/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
AC Test Conditions Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH = 2.4 V VI L= 0.4 V tr = 1V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2
Output Load 1
DQ 50 VT = 1.4 V 30pF1
Output Load 2
3.3 V DQ 5pF1 589 434
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.07 12/2004
6/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
AC Characteristics Read Cycle
Parameter Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Byte disable to output in High Z (UB, LB) Symbol tRC tAA tAC tAB tOE tOH tLZ* tOLZ* tBLZ* tHZ* tOHZ* tBHZ* -7 Min 7 -- -- -- -- 3 3 0 0 -- -- -- Max -- 7 7 3 3 -- -- -- -- 3.5 3 3 Min 8 -- -- -- -- 3 3 0 0 -- -- -- -8 Max -- 8 8 3.5 3.5 -- -- -- -- 4 3.5 3.5 Min 10 -- -- -- -- 3 3 0 0 -- -- -- -10 Max -- 10 10 4 4 -- -- -- -- 5 4 3.5 Min 12 -- -- -- -- 3 3 0 0 -- -- -- -12 Max -- 12 12 5 5 -- -- -- -- 6 5 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns --
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC Address tAA tOH Data Out Previous Data Data valid
Rev: 1.07 12/2004
7/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ UB, LB OE tBLZ tOE Data Out tOLZ High impedance tAB tBHZ tOHZ Data valid tHZ
Write Cycle
Parameter Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z Symbol tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -7 Min 7 5 5 5 3.5 0 5 0 0 0 3 -- Max -- -- -- -- -- -- -- -- -- -- -- 3 Min 8 5.5 5.5 5.5 4 0 5.5 0 0 0 3 -- -8 Max -- -- -- -- -- -- -- -- -- -- -- 3.5 Min 10 7 7 7 5 0 7 0 0 0 3 -- -10 Max -- -- -- -- -- -- -- -- -- -- -- 4 Min 12 8 8 8 6 0 8 0 0 0 3 -- -12 Max -- -- -- -- -- -- -- -- -- -- -- 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested.
Rev: 1.07 12/2004
8/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Write Cycle 1: WE control
tWC Address tAW OE tCW CE tBW UB, LB tAS WE tDW Data In tWHZ Data Out tDH Data valid tWLZ High impedance tWP tWR
Write Cycle 2: CE control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 1.07 12/2004
9/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Write Cycle 3: UB, LB control
tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1
High impedance
Rev: 1.07 12/2004
10/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
44-Pin, 400 mil SOJ
Symbol A A1 A2 HE B B1 c 1 e 22
A
Dimension in inch min -- 0.025 0.105 -- 0.026 -- 1.120 0.395 -- 0.435 0.360 0.082 -- 0o nom -- -- 0.110 0.018 0.028 0.008 1.125 0.400 0.05 0.440 0.370 0.087 -- -- max 0.148 -- 0.115 -- 0.032 -- 1.130 0.405 -- 0.445 0.380 0.106 0.004 7o
Dimension in mm min -- 0.635 2.667 -- 0.660 -- 28.44 10.033 -- 11.049 9.144 2.083 -- 0o nom -- -- 2.794 0.457 0.711 0.203 28.58 10.160 1.27 11.176 9.398 2.210 -- -- max 3.759 -- 2.921 -- 0.813 -- 28.70 10.287 -- 11.303 9.652 2.70 0.102 7o
D 44 23
L c
GE
E
D E e HE
A
A2
A1
y
B B1 Detail A
GE Q L y Q
Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: inches
Rev: 1.07 12/2004
11/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
44 Pin, 400 mil TSOP-II
Symbol 23 c A A1 A2 HE
A
Dimension in inch min -- 0.002 0.037 0.01 -- 0.721 0.396 -- 0.455 0.016 -- -- 0
o
Dimension in mm min -- 0.05 0.95 0.25 -- 18.31 10.06 -- 11.56 0.40 -- -- 0
o
44
D
nom -- -- 0.039 0.014 0.006 0.725 0.400 0.031 0.463 0.020 0.031 -- --
max 0.047 -- 0.041 0.018 -- 0.729 0.404 -- 0.471 0.024 -- 0.004 5
o
nom -- -- 1.00 0.35 0.15 18.41 10.16 0.80 11.76 0.50 0.80 -- --
max 1.20 -- 1.05 0.45 -- 18.51 10.26 -- 11.96 0.60 -- 0.10 5o
E
B c D E e HE L
1 A2
e
22 B
A
A1
y L1 L
L1 y Q Q
Detail A
Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm
Rev: 1.07 12/2004
12/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
6 mm x 8 mm Fine Pitch BGA 8.00 0.10 6.00 0.10 0.22 0.05 3 2 1 6 0.75(typ).
13/16
Top View
1.20(max)
pin A1 index
Bottom View
pin A1 index
5
4
Rev: 1.07 12/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Ball Dia. 0.35 Pitch 0.75
(c) 2001, GSI Technology
3.75 5.25
0.36(typ)
0.10
G
D
C
H
A
B
E
F
D
units: mm
GS71116ATP/J/U
Ordering Information Part Number*
GS71116ATP-7 GS71116ATP-8 GS71116ATP-10 GS71116ATP-12 GS71116ATP-7I GS71116ATP-8I GS71116ATP-10I GS71116ATP-12I GS71116AGP-7 GS71116AGP-8 GS71116AGP-10 GS71116AGP-12 GS71116AGP-7I GS71116AGP-8I GS71116AGP-10I GS71116AGP-12I GS71116AJ-7 GS71116AJ-8 GS71116AJ-10 GS71116AJ-12 GS71116AJ-7I GS71116AJ-8I GS71116AJ-10I GS71116AJ-12I GS71116AU-7 GS71116AU-8 GS71116AU-10 GS71116AU-12 GS71116AU-7I GS71116AU-8I Rev: 1.07 12/2004
Package
400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II Pb-free 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 14/16
Access Time
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns
Temp. Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial
Status
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Ordering Information Part Number*
GS71116AU-10I GS71116AU-12I GS71116AGU-7 GS71116AGU-8 GS71116AGU-10 GS71116AGU-12 GS71116AGU-7I GS71116AGU-8I GS71116AGU-10I GS71116AGU-12I
*
Package
6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA Pb-free 6 mm x 8 mm Fine Pitch BGA
Access Time
10 ns 12 ns 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Temp. Range
Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Status
Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example: GS71116ATP-10T
Rev: 1.07 12/2004
15/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
1Mb Asynchronous Datasheet Revision History Rev. Code: Old; New
71116A_r1 71116A_r1; 71116_r1_01 71116A_r1_01; 71116A _r1_02 71116A_r1_02; 71116A _r1_03 71116A_r1_03; 71116A _r1_04 71116A_r1_04; 71116A _r1_05 71116A_r1_05; 71116A_r1_06 71116A_r1_06; 71116A_r1_07 Content Content Content Content Content Content/Format Content/Format
Types of Changes Format or Content
Page #/Revisions/Reason
* Creation of new datasheet * Added 6 ns speed bin to entire document * Updated all power numbers * Changed 6 mm x 10 mm FPBGA package designator from U to X * Updated Recommended Operating Conditions table on page 4 * Changed FPBGA package from 6 x 10 to 6 x 8 (package U) * Updated Read Cycle AC Characteristics table * Removed 6 ns speed bin from entire document * Added 7 ns speed bin to entire document * Updated timings for tBHZ (Read Cycle) for 10 ns and 12 ns * Updated format * Added Pb-free information for TSOP-II package * Added Pb-free information for FP-BGA package
Rev: 1.07 12/2004
16/16
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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