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Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
74F8960/74F8961
FEATURES
* Octal latched transceiver * Drives heavily loaded backplanes with
equivalent load impedances down to 10
DESCRIPTION
The 74F8960 and 74F8961 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired-OR bus. The B port inverting drivers are low-capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter. The B port interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident switching is employed, therefore BTL propagation delays are short. Although the
voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8960 and 74F8961 A ports have TTL 3-state drivers and TTL receivers with a latch function. A separate High-level control input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F8961 is the non-inverting version of 74F8960.
* High drive (100mA) open collector drivers
on B port
* Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
* High speed operation enhances
performance of backplane buses and facilitates incident wave switching
* Compatible with IEEE futurebus standards * Built-in precision band-gap reference
provides accurate receiver thresholds and improved noise immunity
* Controlled output ramp and multiple GND
pins minimize ground bounce
* Glitch-free power up/down operation
TYPE 74F8960 74F8961 TYPICAL PROPAGATION DELAY 6.5ns 6.5ns TYPICAL SUPPLY CURRENT( TOTAL) 80mA 80mA
ORDERING INFORMATION
DESCRIPTION 28-pin plastic DIP (300 mil)1 28-pin PLCC1 NOTE: Thermal mounting techiques are recommended. ORDER CODE COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F8960N, N748961N N74F8960A, N74F8961A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A8 B0 - B8 OEA OEB0, OEB1 LE A0 - A7 PNP latched inputs Data inputs with threshold circuitry A output enable input (active high) B output enable inputs (active low) Latch enable input (active low) 3-state outputs DESCRIPTION 74F (U.L.) HIGH/LOW 3.5/0.117 5.0/0.167 1.0/0.033 1.0/0.033 1.0/0.033 150/40 OC/166.7 LOAD VALUE HIGH/LOW 70A/70A 100A/100A 20A/20A 20A/20A 20A/20A 3mA/24mA OC/100mA
B0 - B7 Open collector outputs NOTES: 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. 2. OC = Open collector.
December 19, 1990
1
853-1120 01322
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
PIN CONFIGURATION
74F8960
VCC 1 OEA 2 A0 3 GND 4 A1 5 A2 6 A3 7 GND 8 A4 9 A5 10 GND 11 A6 12 A7 13 VX 14 28 LE 27 B0 26 B1 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 18 GND 17 B7 16 OEB1 15 OEB0 A1 A2 5 6 7 8 9 PLCC GND A0 OEA VCC LE 4 3 2 1 28 B0 B1 27 26 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 12 A6 13 14 15 16 17 18 27 15 2 28 16
74F8960/74F8961
PIN CONFIGURATION PLCC
74F8960
LOGIC SYMBOL
74F8960
3 5 6 7 9 10 12 13
A0 A1 A2 OEB0 OEA LE OEB1
A3 A4 A5
A6 A7
A3
GND A4
A5 10 GND 11
B0 B1 B2 B3 B4 B5
B6 B7
A7 VX OEB2 OEB1 B7 GND
26 24
23
21 20
19 17
VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25
PIN CONFIGURATION
74F8961
VCC 1 OEA 2 A0 3 GND 4 A1 5 A2 6 A3 7 GND 8 A4 9 A5 10 GND 11 A6 12 A7 13 VX 14 28 LE
PIN CONFIGURATION PLCC
74F8961
LOGIC SYMBOL
74F8961
3 5 6 7 9 10 12 13
27 B0 26 B1 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 18 GND 17 B7 16 OEB1 15 OEB0 A1 A2 5 6
GND A0 OEA VCC LE 4 3 2 1 28
B0 B1 27 26 25 GND 24 B2 23 B3 15 2 28 16 A0 A1 A2 A3 A4 A5 OEB0 OEA LE OEB1 B0 B1 B2 B3 B4 B5 B6 B7 A6 A7
A3 7
GND A4 8 9 PLCC
22 GND 21 B4 20 B5 19 B6
A5 10 GND 11 12 A6 13 14 15 16 17 18
27
26 24
23
21 20
19 17
A7 VX OEB2 OEB1 B7 GND
VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25
December 19, 1990
2
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
IEC/IEEE SYMBOL FOR 74F8960
74F8960
15 16 28 2 C1 EN3 27 & EN2 15 16 28 2 C1 EN3 &
74F8960/74F8961
IEC/IEEE SYMBOL FOR 74F8961
74F8961
EN2
3
1D 3
2
3
1D 3
2
27
5 6 7 9 10 11 13
26 24 23 21 20 19 17
5 6 7 9 10 11 13
26 24 23 21 20 19 17
PIN DESCRIPTION
SYMBOL A0 - A7 B0 - B7 OEB0 OEB1 LE VX PINS 3, 5, 6, 7, 9, 10, 12, 13 27, 26, 24, 23, 21, 20, 19, 17 15 16 28 14 TYPE I/O I/O Input Input Input Input NAME AND FUNCTION PNP latched input/3-state output (with VX control option) Data input with special threshold circuitry to reject noise/ open collector output, high current drive Enables the B outputs when both pins are low Enables the A outputs when high Latched when high (a special feature is buillt in for proper enabling times) Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
December 19, 1990
3
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
LOGIC DIAGRAM
74F9860 OEB0 15 OEB0 15 74F9861
74F8960/74F8961
OEB1
16
OEB1
16
OEA 2
OEA 2
LE 28 3
LE 28 3
A0
Data LE
Q
27 B0
A0
Data LE
Q
27 B0
A1
5
Data LE
Q
26 B1
A1
5
Data LE
Q
26 B1
A2
6
Data LE
Q
24 B2
A2
6
Data LE
Q
24 B2
A3
7
Data LE
Q
23 B3
A3
7
Data LE
Q
23 B3
A4
9
Data LE
Q
21 B4
A4
9
Data LE
Q
21 B4
A5 10
Data LE
Q
20 B5
A5 10
Data LE
Q
20 B5
A6 12
Data LE
Q
19 B6
A6 12
Data LE
Q
19 B6
A7 13
Data LE
Q
17 B7
A7 13
Data LE
Q
17 B7
VCC = Pin 1, VX = Pin 14, GND = Pin 4, 8, 11, 18, 22, 25
December 19, 1990
4
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
FUNCTION TABLE FOR 74F8960
INPUTS An H L X - - - - H l X - - - - H l X - - - - NOTES: 1. H = 2. L = 3. X = 4. - = 5. Z = 6. Qn = 7. (1) = 8. (2) = 9. H**= 10. B* = Bn* X X X - H L - X X X H L H L X X X H L H L LE L L H L H H H L L H L L H H L L H L L H H OEA L L L H H H H L L L H H H H L L L H H H H OEB 0 L L L L L L L H H H H H H H X X X X X X X OEB 1 L L L L L L L X X X X H H H H H H H H H H LATCH STATE H L Qn (1) H (2) H (2) Qn H l Qn H L Qn Qn H l Qn H L Qn Qn OUTPUTS An Z Z Z (1) H L Qn Z Z Z H L H L Z Z Z H L H L Bn L H** Qn (1) Z(2) Z(2) Qn Z Z Z Z Z Z Z Z Z Z Z Z Z Z B 3-state, data from B to A B and A 3-state B 3-state, data from B to A B and A 3-state Latch state to A and B A 3-state, latched data to B Feedback: A to B, B to A A 3-state, data from A to B
74F8960/74F8961
OPERATING MODE
Preconditioned latch enabling data transfer from B to A
High-voltage level Low-voltage level Don't care Input not externally driven High impedance (off) state High or low voltage level one setup time prior to the low-to-high LE transition. Condition will cause a feedback loop path: A to B and B to A. The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high. Goes to level of pullup voltage. Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
5
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
FUNCTION TABLE FOR 74F8961
INPUTS An H L X - - - - H l X - - - - H l X - - - - NOTES: 1. H = 2. L = 3. X = 4. - = 5. Z = 6. Qn = 7. (1) = 8. (2) = 9. H**= 10. B* = Bn* X X X - H L - X X X H L H L X X X H L H L LE L L H L H H H L L H L L H H L L H L L H H OEA L L L H H H H L L L H H H H L L L H H H H OEB 0 L L L L L L L H H H H H H H X X X X X X X OEB 1 L L L L L L L X X X X H H H H H H H H H H LATCH STATE H L Qn (1) H (2) H (2) Qn H l Qn H L Qn Qn H l Qn H L Qn Qn OUTPUTS An Z Z Z (1) H L Qn Z Z Z H L H L Z Z Z H L H L Bn H** L Qn (1) Z(2) Z(2) Qn Z Z Z Z Z Z Z Z Z Z Z Z Z Z B 3-state, data from B to A B and A 3-state B 3-state, data from B to A B and A 3-state Latch state to A and B A 3-state, latched data to B Feedback: A to B, B to A A 3-state, data from A to B
74F8960/74F8961
OPERATING MODE
Preconditioned latch enabling data transfer from B to A
High-voltage level Low-voltage level Don't care Input not externally driven High impedance (off) state High or low-voltage level one setup time prior to the low-to-high LE transition. Condition will cause a feedback loop path: A to B and B to A. The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high. Goes to level of pullup voltage. Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
6
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
ABSOLUTE MAXIMUM RATINGS
74F8960/74F8961
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VX VIN Supply voltage Threshold control Input voltage OEB, OEA, LE A0 - A7, B0 - B7 IIN VOUT IOUT Input current Voltage applied to output in high output state Current applied to output in low output state A0 - A7 B0 - B7 Tamb Tstg Operating free air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +5.5 -40 to +5 -0.5 to VCC 48 200 0 to +70 -65 to +150 UNIT V V V V mA V mA mA
C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH Supply voltage High-level input voltage Except B0 - B7 B0 - B7 VIL Low-level input voltage Except B0 - B7 B0 - B7 IIk Input clamp current Except A0 - A7 A0 - A7 IOH IOL High-level output current Low-level output current A0 - A7 A0 - A7 B0 - B7 Tamb Operating free air temperature range 0 PARAMETER MIN 4.5 2.0 1.6 0.8 1.475 -18 -40 -3 24 100 +70 NOM 5.0 MAX 5.5 UNIT V V V V V mA mA mA mA mA
C
December 19, 1990
7
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 IOH IOFF VOH High-level output current Power-off output current B0 - B7 B0 - B7 A74
74F8960/74F8961
LIMITS TYP. MIN.
2
UNIT MAX. 100 100 A A V V 0.50 1.15 V V V -0.5 -1.2 100 1 20 100 -20 -100 70 -70 V V
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MIN, IOH = -3mA, VX =VCC IOH = -4mA, VX =3.13V and 3.47V IOL = 20mA, VX = VCC IOL = 100mA IOL = 4mA 0.40 2.5 2.5
VCC
High-level output voltage
A0 -
VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX VIH = MIN VCC = MIN, II = IIK VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 5.5V VCC = MAX, VI = 2.7V
A0 - A74 VOL VIK II IIH IIL Low-level output voltage B0 - B78
Input clamp voltage
A0 - A7 Except A0 - A7
Input current at maximum input voltage High-level input current Low-level input current
OEBn, OEA, LE A0-A7, B0 - B7 OEBn, OEA, LE B0-B7 OEBn, OEA, LE B0 - B7
A
mA
VCC = MAX, VI = 2.1V, Bn - An = 0V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.3V VCC = MAX, VO = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VX = VCC, LE = OEA = OEBn = 2.7V, A0 - A7 = 2.7V, B0 - B7 = 2.0V, VCC = MAX, VX = 3.13 & 3.47V, LE = OEA = OEBn = A0 - A7 = 2.7V, B0 - B7 = 2.0V, -100 -10
A A A A A A A A
mA
IOZH + IIH IOZL + IIL IX
Off-state output current, high-level current applied Off-state output current, low-level voltage applied High-level control current
A0 - A7 A0 - A7
100 10
IOS
Short circuit output current3
V = MAX, Bn = 1.3V, OEA = 2.0V, OEBn = 74F8960 CC 2.7V A0-A7 'F8960 only V = MAX, Bn = 1.8V, OEA = 2.0V, OEBn = only 74F8961 CC 2.7V ICCH VCC = MAX VCC = MAX, VIL = 0.5V
-60
-150
65 100 75
100 145 100
mA mA mA
ICC
Supply current (total)
ICCL ICCZ
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type and function table for operating mode. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH =1.8v and VIL = 1.3V.
December 19, 1990
8
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
AC ELECTRICAL CHARACTERISTICS FOR 74F8960
74F8960/74F8961
A PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Bn to An Output enable time to high or low, OEA to An Output enable time from high or low, OEA to An Waveform 1, 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 4.5 6.0 8.0 8.5 2.0 2.0 TYP 6.0 10.0 10.5 11.0 3.5 4.5 Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CD = 50pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Propagation delay An to Bn Propagation delay LE to Bn Output enable/disable time OEBn to Bn Transition time, Bn port 1.3V to 1.7V, 1.7V to 1.3V Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test circuit and waveforms 3.5 3.5 3.5 4.0 2.5 3.5 0.5 0.5 TYP 5.5 5.0 5.5 6.5 4.5 5.5 2.0 2.0 MAX 8.0 8.0 8.5 9.0 7.5 8.5 4.5 4.5 MAX 8.5 13.5 13.5 13.5 6.5 7.0 Tamb = 0C to +70C VCC = +5.0V 10% MIN 3.5 7.5 7.5 8.5 2.0 2.0 UNIT CL = 50p, RL = 500 MAX 9.5 14.5 15.0 16.0 7.0 7.5 ns ns ns
B PORT LIMITS Tamb = 0C to +70C VCC = +5.0V 10% MIN 2.0 3.0 2.5 3.0 1.5 3.5 0.5 0.5 UNIT CD = 50pF, RL = 9 MAX 9.5 9.0 9.5 10.5 8.0 9.0 5.0 6.0 ns ns ns ns
AC SETUP REQUIREMENTS FOR 74F8960
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tw(L) Setup time, high or low An to LE Hold time, high or low An to LE LE pulse width, low Waveform 3 Waveform 3 Waveform 3 5.0 3.0 0.0 0.0 4.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% MIN 5.0 5.0 0.0 0.0 5.0 UNIT CL = 50pF, RL = 500 MAX ns ns ns
December 19, 1990
9
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
AC ELECTRICAL CHARACTERISTICS FOR 74F8961
74F8960/74F8961
A PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Bn to An Output enable time to high or low, OEA to An Output enable time from high or low, OEA to An Waveform 1, 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 5.5 4.5 8.0 8.5 2.0 2.0 TYP 8.0 6.0 10.5 11.0 3.5 4.5 Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CD = 50pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Propagation delay An to Bn Propagation delay LE to Bn Output enable/disable time OEBn to Bn Transition time, Bn port 1.3V to 1.7V, 1.7V to 1.3V Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test circuit and waveforms 3.0 3.0 3.5 3.5 3.0 3.5 0.5 0.5 TYP 5.0 4.5 5.0 5.0 4.5 5.5 2.0 2.0 MAX 7.0 7.5 8.0 8.0 7.0 9.0 4.5 4.5 MAX 12.0 9.0 13.5 13.5 6.0 7.0 Tamb = 0C to +70C VCC = +5.0V 10% MIN 5.5 4.5 7.5 8.0 1.5 2.0 UNIT CL = 50p, RL = 500 MAX 12.0 9.0 15.0 15.5 6.5 7.5 ns ns ns
B PORT LIMITS Tamb = 0C to +70C VCC = +5.0V 10% MIN 2.5 2.5 3.0 2.5 2.5 3.5 0.5 0.5 UNIT CD = 50pF, RU = 9 MAX 8.0 8.5 9.0 9.0 8.0 10.0 5.0 4.5 ns ns ns ns
AC SETUP REQUIREMENTS FOR 74F8961
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tw(L) Setup time, high or low An to LE Hold time, high or low An to LE LE pulse width, low Waveform 3 Waveform 3 Waveform 3 3.5 4.5 0.0 0.0 4.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% MIN 4.5 5.0 0.0 0.0 5.0 UNIT CL = 50pF, RL = 500 MAX ns ns ns
December 19, 1990
10
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
AC WAVEFORMS
An, Bn, OEBn VM tPLH An, Bn VM An, Bn, OEBn VM tPHL VM VM tPHL VM
74F8960/74F8961
VM tPLH VM
An, Bn
Waveform 1. Propagation delay for data to output
An VM VM th(L) ts(L) LE VM VM
Waveform 2. Propagation delay for data to output
VM VM th(H) ts(H) tw(L) VM
Waveform 3. Data setup and hold times and LE pulse width
OEA VM tPZH An VM 0V VOL +0.3V VM tPHZ VOH -0.3V OEA VM tPZL An VM VM tPLZ
Waveform 4. 3-state output enable time to high level and output disable time from high level
Waveform 5. 3-state output enable time to low level and output disable time from low level
NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open
VIN PULSE GENERATOR RT D.U.T. tTLH (tr ) CL RL POSITIVE PULSE 90% VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% Low V 90% VCC 7.0V VOUT RL NEGATIVE PULSE VM 10% tTHL (tf ) tw VM 10% tTLH (tr ) Low V 90% AMP (V)
Test circuit for 3-state outputs on A port
VCC 7.0V
Input pulse definition
VIN PULSE GENERATOR RT D.U.T. VOUT RU
INPUT PULSE REQUIREMENTS family tTLH tw 74F amplitude Low V VM rep. rate A port B port 3.0V 3.0V 0.0V 1.0V 1.5V 1.5V 1MHz 1MHz 500ns 500ns 2.5ns 4.0ns
tTHL 2.5ns 4.0ns
CD
Test circuit for outputs on B port DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU = Pull up resistor; see AC electrical characteristics for value. CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
December 19, 1990
11

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