View MB15F72SP_412628.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21363-2E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F72SP
s DESCRIPTION
The Fujitsu MB15F72SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. MB15F72SP has the same configuration with MB15F02 or MB15F02L. The BiCMOS process is used , as a result a supply current is typically 2.7 mA typ. at 2.7 V.The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data. The new package(BCC20) decreases a area of MB15F72SP more than 30 % comparing with the former BCC16 (for dual PLL). MB15F72SP is ideally suited for wireless mobile communications, such as PDC
s FEATURES
* High frequency operation:RF synthesizer: 1300 MHz max :IF synthesizer: 350 MHz max * Low power supply voltage: VCC = 2.4 to 3.6 V * Ultra Low power supply current:ICC = 2.7 mA typ. (VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25C, in IF, RF locking state) * Direct power saving function:Power supply current in power saving mode Typ. 0.1 A (VCC = Vp = 2.7 V, Ta = +25C) Max. 10 A (VCC = Vp = 2.7 V)
(Continued)
s PACKAGES
20-pin plastic TSSOP 20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M04)
MB15F72SP
(Continued) * Software selectable charge pump current: 1.5 mA/6.0 mA (typ.) * Dual modulus prescaler: 1300 MHz prescaler (64/65 or 128/129 )/350 MHz prescaler (8/9 or 16/17) * 23 bit shift resister * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * On-chip phase control for phase comparator * Built-in digital locking detector circuit to detect PLL locking and unlocking. * Operating temperature: Ta = -40C to +85C * Sireal data format compatible with MB15F02SL * Small package BCC20 (3.4 mm x 3.6mm x 0.8mm)
s PIN ASSIGNMENTS
(TSSOP-20)
TOP VIEW
(BCC-20) TOP VIEW
OSCIN Data GND Clock finIF XfinIF GNDIF VCCIF PSIF VpIF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LE finRF XfinRF GNDRF VCCRF PSRF
OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DoIF LD/fout
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Clock Data LE finRF XfinRF GNDRF VCCRF PSRF VpRF DoRF
DoIF DoRF LD/fout VpRF
(FPT-20P-M06)
(LCC-20P-M04)
2
MB15F72SP
s PIN DESCRIPTION
Pin no. TSSOP BCC 1 2 3 4 5 6 19 20 1 2 3 4 Pin name I/O OSCIN GND finIF XfinIF GNDIF VCCIF I Descriptions The programmable reference divider input. TCXO should be connected with a AC coupling capacitor.
Ground for OSC input buffer and the shift register circuit. I I Prescaler input pin for the IF-PLL. Connection to an external VCO should be via AC coupling. Prescaler complimentary input pin for the IF-PLL section. This pin should be grounded via a capacitor.
Ground for the IF-PLL section. Power supply voltage input pin for the IF-PLL section(except for the charge pump circuit), the OSC input buffer and the shift register circuit. When power is OFF, latched data of IF-PLL is lost. I Power saving mode control for the IF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSIF = "H" ; Normal mode / PSIF = "L" ; Power saving mode
7 8 9
5 6 7
PSIF VpIF DOIF
Power supply voltage input pin for the IF-PLL charge pump. O Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FCbit. Lock detect signal output (LD)/phase comparator monitoring output (fout).The output signal is selected by LDS bit in the serial data. LDS bit = "H" ; outputs fout signal / LDS bit = "L" ; outputs LD signal Charge pump output for the RF-PLL section. Phase characterstics of the phase detector can be reversed by FCbitt.
10
8
LD/fout
O
11 12 13
9 10 11
DORF VpRF PSRF
O
Power supply voltage input pin for the RF-PLL charge pump. I Power saving mode control for the RF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSRF = "H" ; Normal mode / PSRF = "L" ; Power saving mode Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit).
14 15 16 17
12 13 14 15
VCCRF GNDRF XfinRF finRF
Ground for the RF-PLL section. I I Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. Load enable signal input(with the schmitt trigger circuit). When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input(with the schmitt trigger circuit). A data is transferred to the corresponding latch(IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit). One bit of data is shifted into the shift register on a rising edge of the clock. 3
18
16
LE
I
19
17
Data
I
20
18
Clock
I
MB15F72SP
s BLOCK DIAGRAM
VCCIF (4) 6 GNDIF 5 (3) VpIF 8 (6)
PSIF 7 (5)
Intermittent mode control (IF-PLL)
3 bit latch
LDS SWIF FCIF
7 bit latch
11 bit latch
fpIF
Phase comp. (IF-PLL)
Binary 7-bit Binary 11-bit proswallow counter grammable (IF-PLL) counter(IF-PLL)
Charge Current pump Switch (IF-PLL)
9 DoIF (7)
finIF 3 (1) XfinIF 4 (2)
Prescaler (IF-PLL) (8/9, 16/17
Lock Det. (IF-PLL)
2 bit latch
14 bit latch
Binary 14-bit programmable ref. counter(IF-PLL)
1 bit latch C/P setting counter
LDIF
T1
T2
frIF OSCIN 1 (19) frRF T1 OR
2 bit latch
AND
C/P setting counter
1 bit latch
Selector
T2
Binary 14-bit programmable ref. counter(RF-PLL)) 14 bit latch
LD frIF frRF fpIF fpRF
10 LD/ ( 8 ) fout
( 15 ) finRF 17 XfinRF 16 ( 14 )
Prescaler (RF-PLL) (64/65, 128/129)
Lock Det. (RF-PLL)
PSRF 13 (11)
Intermittent mode control (RF-PLL)
LDS SWRF FCRF
Binary 11-bit proBinary 7-bit swallow counter grammable counter (RF-PLL) (RF-PLL)
Phase comp. (RF-PLL)
Charge Current pump Switch (RF-PLL)
11 DoRF (9)
fpRF
3 bit latch
7 bit latch
11 bit latch
LE 18 ( 16 ) ( 17 ) Data 19 Clock 20 ( 18 )
Schmitt circuit
Latch selector
Schmitt circuit Schmitt circuit
CC NN 12
23-bit shift register
2 ( 20 ) GND
( 12 ) 14 VCCRF
15 ( 13 ) GNDRF
12 ( 10 ) VpRF
O : TSSOP ( ) : BCC
4
MB15F72SP
s ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VCC Vp VI LD/fout DoIF, DoRF VO VDO Tstg Rating Min. -0.5 VCC -0.5 GND GND -55 Max. 4.0 4.0 VCC + 0.5 VCC Vp +125 Unit V V V V V C
Power supply voltage Input voltage Output voltage Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCC Vp VI Ta Value Min. 2.4 VCC GND -40 Typ. 2.7 2.7 Max. 3.6 3.6 VCC +85 Unit V V V C Remark VCCRF = VCCIF
Power supply voltage Input voltage Operating temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F72SP
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Parameter Symbol ICCIF *1 IF PLL ICCRF *2 RF PLL IPSIF IPSRF finIF Operating frequency
*3
Condition
Value Min. 50 100 Typ. 1.1 1.6 0.1
*8
Max. 10 10 350 1300 40 +2 +2 VCC 0.3 VCC - 0.4 0.3 VCC +1.0 +1.0 +100 0 0.4 0.4 2.5 -1.0
Unit mA mA A A MHz MHz MHz dBm dBm VP - P V V V V A A A A V V V V nA mA mA
Power supply current
Power saving current
PSIF = PSRF = "L" PSIF = PSRF = "L" IF PLL RF PLL
0.1 *8
finIF finRF fOSC
finRF *3 OSCIN finIF
3 -15 -15 0.5 0.7 VCC + 0.4 0.7 VCC -1.0 -1.0 0 -100 VCC - 0.4 Vp - 0.4 1.0
PfinIF IF PLL, 50 system PfinRF RF PLL, 50 system VOSC VIH VIL VIH VIL IIH *4 IIL *4 IIH IIL *4 VOH VOL
Input sensitivity
finRF OSCIN
"H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H" level output current "L" level output current
Data, LE, Clock PSIF, PSRF Data, LE, Clock, PSIF, PSRF OSCIN
Schmitt trigger input Schmitt trigger input
VCC = Vp = 2.7 V, IOH = -1 mA VCC = Vp = 2.7 V, IOL = 1 mA VCC = Vp = 2.7 V, IDOH = -0.5 mA VCC = Vp = 2.7 V, IDOL = 0.5 mA VCC = Vp = 2.7 V VOFF = 0.5 V to Vp - 0.5 V VCC = Vp = 2.7 V VCC = Vp = 2.7 V
LD/fout
DoIF, DoRF DoIF, DoRF LD/fout
VDOH VDOL IOFF IOH *4 IOL
(Continued)
6
MB15F72SP
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Parameter Symbol Condition VCC = Vp = 2.7 V, CS bit = "H" VDOH = Vp/2, CS bit = "L" Ta = +25 C VCC = Vp = 2.7 V, CS bit = "H" VDOL = Vp/2, CS bit = "L" Ta = +25 C VDO = Vp / 2 0.5 V VDO Vp - 0.5 V -40 C Ta +85 C, VDO = Vp / 2 Value Min. Typ. -6.0 -1.5 6.0 1.5 3 10 10 Max. Unit mA mA mA mA % % %
"H" level output current "L" level output current
DoIF DoRF DoIF DoRF
IDOH *4
IDOL
IDOL/IDOH IDOMT *5 Charge pump current rate vs. VDO vs.Ta IDOVD *6 IDOTA *7
*1 : finIF = 270 MHz, fosc = 12.8 MHz, VCCIF = VpIF = 2.7 V, SWIF = 0, Ta = +25C, in locking state. *2 : finRF = 910 MHz, fosc = 12.8 MHz, VCCRF = VpRF = 2.7 V, SWRF = 0, Ta = +25C, in locking state. *3 : AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency. *4 : The symbol "-" (minus) means direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = +25C (||I3| - |I4||)/[(|I3| + |I4|)/2] x 100(%) *6 : VCC = Vp = 2.7 V, Ta = +25C (Applied to each IDOL, IDOH) [(||I2| - |I1||)/2]/[(|I1| + |I2|)/2] x 100(%) *7 : VCC = Vp = 2.7 V, Ta = +25C (Applied to each IDOL, IDOH) [||IDO(+85C)| -|IDO(-40C)||/2]/[|IDO(+85C)| + |IDO(-40C)|/2] x 100(%) *8 : fosc = 12.8 MHz, VCCRF = VpRF = VCCIF = 2.7 V, Ta = +25C
I1 IDOL
I3 I2
IDOH
I4 I1 0.5 Vp/2 Vp - 0.5 Vp
Charge pump output voltage (V)
7
MB15F72SP
s FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
fVCO = [(P x N) + A] x fOSC / R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On a rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. The programmable reference counter for the IF-PLL CN1 CN2 0 0 The programmable reference counter for the RF-PLL 1 0 The programmable counter and the swallow counter for the IF-PLL 0 1 The programmable counter and the swallow counter for the RF-PLL 1 1
(1) Shift Register Configuration * Programmable Reference Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
16
17
18 19 20 21 22 23
X X X
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
CS R1 to R14 T1, T2 CN1, CN2 X
: Charge pump currnet select bit : Divide ratio setting bits for the programmable reference counter (3 to 16,383) : Test purpose bit : Control bit : Dummy bits (Set "0" or "1")
Note : Data input with MSB first.
8
MB15F72SP
* Programmable Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
CN1 CN2 LDS
SWIF/ FCIF/ A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 SWRF FCRF
A1 to A7 N1 to N11 LDS SWIF/SWRF FCIF/FCRF CN1, CN2
: Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (IF : SWIF,RF : SWRF) : Phase control bit for the phase detector (IF: FCIF, RF: FCRF) : Control bit
Note: Data input with MSB first. (2) Data setting * Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14) Divide ratio 3
4 * * * 16383
R14 0
0 * * * 1
R13 0
0 * * * 1
R12 0
0 * * * 1
R11 0
0 * * * 1
R10 0
0 * * * 1
R9 0
0 * * * 1
R8 0
0 * * * 1
R7 0
0 * * * 1
R6 0
0 * * * 1
R5 0
0 * * * 1
R4 0
0 * * * 1
R3 0
1 * * * 1
R2 1
0 * * * 1
R1 1
0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 11-bit Programmable Counter Data Setting (N1 to N11) Divide ratio
3 4 * * * 2047
N11
0 0 * * * 1
N10
0 0 * * * 1
N9
0 0 * * * 1
N8
0 0 * * * 1
N7
0 0 * * * 1
N6
0 0 * * * 1
N5
0 0 * * * 1
N4
0 0 * * * 1
N3
0 1 * * * 1
N2
1 0 * * * 1
N1
1 0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 7-bit Swallow Counter Data Setting (A1 to A7) Divide ratio
0 1 * * * 127
A7
0 0 * * * 1
A6
0 0 * * * 1
A5
0 0 * * * 1
A4
0 0 * * * 1
A3
0 0 * * * 1
A2
0 0 * * * 1
A1
0 1 * * * 1
9
MB15F72SP
* Prescaler Data Setting (SW) Divide ratio Prescaler divide ratio IF-PLL Prescaler divide ratio RF-PLL * Charge Pump Current Setting (CS) Current value 6.0 mA 1.5 mA CS 1 0 SW = "1"
8/9 64/65
SW = "0"
16/17 128/129
* LD/fout Output Select Data Setting (LDS) LD/fout output signal fout signal LD signal LDS 1 0
* Test Purpose Bit Setting (T1, T2) LD/fout pin state Outputs frIF. Outputs frRF. Outputs fpIF. Outputs fpRF. T1 0 1 0 1 T2 0 0 1 1
* Phase Comparator Phase Switching Data Setting (FCIF, FCRF) Phase comparator input fr > fp fr < fp fr = fp FCIF = "1" DoIF H L Z FCRF = "1" DoRF FCIF = "0" DoIF L H Z FCRF = "0" DoRF
Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High
(1)
(1) VCO polarity FC = "1" (2) VCO polarity FC = "0"
VCO Output Frequency
(2)
LPF Output voltage
Max.
Note : Give attention to the polarity for using active type LPF.
10
MB15F72SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status Normal mode Power saving mode PSIF/PSRF pins
H L
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pins high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes *When power (VCC) is first applied, the device must be in standby mode, PSIF = PSRF = Low, for at least 1 s. *PS pins must be set at "L" for Power-ON.
OFF VCC Clock Data LE PSIF PSRF (1)
ON
tV 1 s
tPS 100 ns
(2)
(3)
(1) PS IF = PSRF = "L" (power saving mode) at Power-ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS IF, PSRF : "L" "H") 100 ns later after setting serial data.
11
MB15F72SP
4. SERIAL DATA INPUT TIMING
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 1st data Control bit
Invalid data
2nd data
Data
MSB
LSB
Clock t1 t7 LE t4 t5 t2 t3 t6
Parameter t1 t2 t3 t4
Min. 20 20 30 30
Typ.
Max. Unit ns ns ns ns
Parameter t5 t6 t7
Min. 100 20 100
Typ.
Max. Unit ns ns ns
Note : LE should be "L" when the data is transferred into the shift register.
12
MB15F72SP
s PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = "1")
DoIF/DoRF
H Z L
(FC bit = "0")
DoIF/DoRF
H Z L
* LD Output Logic IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state LD output H L L L
Notes:*Phase error detection range = -2 to +2 *Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state. *LD output becomes low when phase error is tWU or more. *LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. *tWU and tWL depend on OSCIN input frequency as follows. tWU > 2/fosc : e.g. tWU > 156.3 ns when fosc = 12.8 MHz tWU < 4/fosc : e.g. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F72SP
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF VpIF 0.1 F VCCIF 0.1 F 1000 pF 50 S.G.
1000 pF LD/ fout 10 S.G.
DoIF 9
VpIF 8
PSIF 7
VCCIF 6
GNDIF 5
XfinIF 4
finIF 3
GND 2
OSCIN 1
50
11 DoRF
12 VpRF
13 PSRF
14 VCCRF
15 GNDRF
16 XfinRF
17 finRF
18 LE
19 Data
20 Clock
1000 pF
Controller (divide ratio setting)
1000 pF VpRF 0.1 F 0.1 F VCCRF 50 S.G.
Note : Terminal number shows that of TSSOP-20.
14
MB15F72SP
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity - Input frequency
Ta = +25 C 10
Input sensitivity PfinRF (dBm)
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0
,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 200 400 600 800 1000 1200 1400 1600 1800 2000
Input frequency finRF (MHz) IF-PLL input sensitivity - Input frequency
10 5 Ta = +25 C
Input sensitivity PfinIF (dBm)
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0
,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 50 100 150 200 250 300 350 400 450 500 550 600 650 700
Input frequency finIF (MHz)
15
MB15F72SP
2. OSCIN input sensitivity
Input sensitivity vs Input frequency
Ta = +25 C
10
Input sensitivity VOSC (dBm)
0 -10 -20 -30 -40 -50 -60 0
,,,, ,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 20 40 60 80 100 120 140 160 180 200 220
Input frequency fOSC (MHz)
16
MB15F72SP
3. RF-PLL Do output current
* 1.5 mA mode IDO - VDO
Charge pump output current IDO (mA)
10.0
Ta = +25 C VCC = Vp = 2.7 V
IDOL 0.0 IDOH
-10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
* 6.0 mA mode IDO - VDO
Charge pump output current IDO (mA)
10.0
Ta = +25 C VCC = Vp = 2.7 V IDOL
0.0
IDOH -10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V) 17
MB15F72SP
4. IF-PLL Do output current
* 1.5 mA mode
IDO - VDO
10.0
Charge pump output current IDO (mA)
Ta = +25 C VCC = Vp = 2.7 V
IDOL 0.0 IDOH
-10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
* 6.0 mA mode
IDO - VDO
10.0
Charge pump output current IDO (mA)
Ta = +25 C VCC = Vp = 2.7 V IDOL
0.0
IDOH -10.0 0.0 1.0 2.0 2.7
Charge pump output voltage VDO (V)
18
MB15F72SP
5. fin input impedance
finRF input impedance
VCC = 2.7 V
1 : 266.06 -661.69 100 MHz 2 : 21.406 -146.27 500 MHz 3 : 11.1 -62.982 1 GHz 4 : 10.35 -38.861 1.3 GHz
1
4
2
3 START 100.000 000 MHz STOP 1 500.000 000 MHz
finIF input impedance
VCC = 2.7 V
1 : 712.91 -967.81 50 MHz 2 : 251.59 -650.97 100 MHz 3 : 40.648 -241.14 300 MHz 1 2 4 : 20.391 -141.98 500 MHz
4
3
START 50.000 000 MHz
STOP 500.000 000 MHz
19
MB15F72SP
6. OSCIN input impedance
OSCIN input impedance
VCC = 2.7 V
1 : 10.693 k -11.664 k 3 MHz 2 : 1.8725 k -6.3285 k 10 MHz 3 : 124.25 -1.6726 k 40 MHz
4 1 2 4 : 31.188 3 -664.28 100 MHz
START 3.000 000 MHz
STOP 100.000 000 MHz
20
MB15F72SP
s REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit S.G. OSCIN DO fin Spectrum Analyzer LPF
fVCO = 680 MHz KV = 50 MHz/V fr = 25 kHz fOSC = 14.4 MHz LPF
VCC = 3.0 V VVCO = 2.2 V Ta = + 25 C CP : 6 mA mode
1.0 k
VCO 2200 pF
2.2 k 0.047 pF
4700 pF
* PLL Reference Leakage
ATTEN 10 dB RL 0 dBm
VAVG 72 10 dB/
MKR -73.67 dB 25.0 kHz
MKR 25.0 kHz -73.67 dB
CENTER 680.0000 MHz RBW 1.0 kHz VBW 1.0 kHz
SPAN 200.0 kHz SWP 500 ms
* PLL Phase Noise
ATTEN 10 dB RL 0 dBm
VAVG 23 10 dB/
MKR -55.00 dB 5.37 kHz
MKR 5.37 kHz -55.00 dB
CENTER 680.0000 MHz RBW 100 Hz VBW 100 Hz
SPAN 20.00 kHz SWP 1.60 s
(Continued)
21
MB15F72SP
(Continued)
* PLL Lock Up time
680 MHz755 MHz within1 kHz LchHch 1.244 ms
755.004250 MHz
* PLL Lock Up time
755 MHz680 MHz within 1 kHz HchLch 1.133 ms
680.004000 MHz
755.000250 MHz
680.000000 MHz
754.996250 MHz -822 s 4.178 ms 1.000 ms/div 9.178 ms
679.996000 MHz -822 s
4.178 ms 1.000 ms/div
9.178 ms
855.00 MHz
780.00 MHz
755.00 MHz
680.00 MHz
655.00 MHz -822 s 4.178 ms 1.000 ms/div 9.178 ms
580.00 MHz -822 s 4.178 ms 1.000 ms/div 9.178 ms
22
MB15F72SP
s APPLICATION EXAMPLE
OUTPUT
VCO 1000 pF 2.7 V 1000 pF 0.1 F
LPF 2.7 V 0.1 F
from controller
Clock 20
Data 19
LE 18
finRF 17
XfinRF 16
GNDRF 15
VCCRF 14
PSRF 13
VpRF 12
DoRF 11
MB15F72SP 1 OSCIN 2 GND 3 finIF 4 XfinIF 5 GNDIF 6 VCCIF 7 PSIF 8 VpIF 9 DoIF 10 LD/fout
Lock Det. 1000 pF 1000 pF 1000 pF 2.7 V 2.7 V
0.1 F TCXO OUTPUT VCO
0.1 F
LPF
Notes : * Clock, Data, LE : Schmitt trigger circuit is provided(insert a pull-down or pull-up registor to prevent oscillation when open-circuit in the input). * Terminal number shows that of TSSOP-20.
23
MB15F72SP
s USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must equal equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device.
s ORDERING INFORMATION
Part number MB15F72SPPFT MB15F72SPPV Package 20-pin plastic TSSOP (FPT-20P-M06) 20-pad plastic BCC (LCC-20P-M04) Remarks
24
MB15F72SP
s PACKAGE DIMENSIONS
20-pin plastic TSSOP (FPT-20P-M06)
* 6.500.10(.256.004)
20 11
Note 1 ) * : These dimensions do not include resin protrusion.
Note 2 ) Pins width and pins thickness include plating thickness.
0.170.05 (.007.002)
* 4.400.10
INDEX
6.400.20 (.173.004) (.252.008)
Details of "A" part 1.050.05 (Mounting height) (.041.002) LEAD No.
1 10
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8
+0.03 +.001
(0.50(.020)) 0.45/0.75 (.018/.030)
0.07 -0.07 .003 -.003 (Stand off) 0.25(.010)
0.10(.004)
C
1999 FUJITSU LIMITED F20026S-2C-2
Dimensions in mm (inches)
(Continued)
25
MB15F72SP
(Continued)
20-pad plastic BCC (LCC-20P-M04)
3.00(.118)TYP 3.600.10(.142.004)
16 11
0.80(.031)MAX (Mounting height)
11
0.250.10 (.010.004)
16
0.250.10 (.010.004) INDEX AREA 3.400.10 (.134.004) 2.70(.106) TYP "D" "A" "B" "C"
0.50(.020) TYP
1
6
6
1
0.0850.04 (.003.002) (Stand off)
0.50(.020) TYP 2.80(.110)REF
0.05(.002)
Details of "A" part 0.500.10 (.020.004)
Details of "B" part 0.500.10 (.020.004)
Details of "C" part 0.500.10 (.020.004) C0.20(.008)
Details of "D" part 0.300.10 (.012.004)
0.600.10 (.024.004)
0.300.10 (.012.004)
0.600.10 (.024.004)
0.400.10 (.016.004)
C
1999 FUJITSU LIMITED C20055S-1C-1
Dimensions in mm (inches)
26
MB15F72SP
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0002 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB15F72SP

	To Download MB15F72SP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .