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| PSoCTM Mixed Signal Array CY8C24123, CY8C24223, and CY8C24423 Final Data Sheet Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0 to 5.25 V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 6 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 8-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART - Multiple SPI Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 4K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 10 Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Port 2 Port 1 Port 0 Analog Drivers PSoCTM Functional Overview The PSoCTM family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23 family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 4K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array (1 Rows, 4 Blocks) ANALOG SYSTEM Analog Block Array (2 Columns, 6 Blocks) Analog Ref Analog Input Muxing The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture micro- Digital Clocks Multiply Accum. POR and LVD Decimator I2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES June 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12011 Rev. *F 1 CY8C24x23 Final Data Sheet PSoCTM Overview processor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Digital peripheral configurations include those listed below. PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 1) SPI master and slave (up to 1) I2C slave and master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 1) Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3. The Analog System The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below. The Digital System The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Port 2 Port 1 Port 0 Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to 2, with selectable gain to 48x) Instrumentation amplifiers (1 with selectable gain to 93x) Comparators (up to 2, with 16 selectable thresholds) DACs (up to 2, with 6- to 9-bit resolution) Multiplying DACs (up to 2, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration 4 8 8 Row Output Configuration 8 8 Row 0 DBB00 DBB01 DCB02 DCB03 4 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital System Block Diagram June 4, 2004 Document No. 38-12011 Rev. *F 2 CY8C24x23 Final Data Sheet PSoCTM Overview Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The number of blocks is dependant on the device family which is detailed in the table titled "PSoC Device Characteristics" on page 3. P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. P0[6] P0[4] P0[2] P0[0] Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. P2[6] P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs PSoC Part Number CY8C29x66 M8C Interface (Address Bus, Data Bus, Etc.) up to 64 up to 44 up to 44 up to 24 up to 16 4 2 2 1 1 16 8 8 4 4 12 12 12 12 8 4 4 4 2 1 4 4 4 2 1 CY8C27x66 CY8C27x43 CY8C24x23 CY8C22x13 Analog System Block Diagram June 4, 2004 Document No. 38-12011 Rev. *F Analog Blocks Digital Blocks Digital IO Digital Rows 12 12 12 6 3 3 CY8C24x23 Final Data Sheet PSoCTM Overview Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows 98, Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items. Tele-Training Free PSoC "Tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see http://www.cypress.com/support/training.cfm. PSoCTM Designer Graphical Designer Interface Context Sensitive Help Commands Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: http://www.cypress.com/support/cypros.cfm. PSoCTM Designer Core Engine Manufacturing Information File Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Application Notes A long list of application notes will assist you in every aspect of your design effort. To locate the PSoC application notes, go to http://www.cypress.com/design/results.cfm. Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems June 4, 2004 Document No. 38-12011 Rev. *F 4 CY8C24x23 Final Data Sheet PSoCTM Overview PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. PSoC Development Tool Kit June 4, 2004 Document No. 38-12011 Rev. *F 5 CY8C24x23 Final Data Sheet PSoCTM Overview User Modules and the PSoC Development Process The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a pictorial environment (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with pointand-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a ROM file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the ROM image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. June 4, 2004 Document No. 38-12011 Rev. *F 6 CY8C24x23 Final Data Sheet PSoCTM Overview Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO IO IPOR LSb LVD MSb PC POR PPOR PSoCTM PWM RAM ROM SC SMP alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose IO input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump Description Table of Contents For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. 1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 8-Pin Part Pinout ....................................... 8 1.1.2 20-Pin Part Pinout ..................................... 9 1.1.3 28-Pin Part Pinout ................................... 10 1.1.4 32-Pin Part Pinout .................................... 11 Register Reference ..................................................... 12 2.1 Register Conventions ........................................... 12 2.1.1 Abbreviations Used .................................. 12 2.2 Register Mapping Tables ..................................... 12 Electrical Specifications ............................................ 15 3.1 Absolute Maximum Ratings ................................ 16 3.2 Operating Temperature ....................................... 16 3.3 DC Electrical Characteristics ................................ 17 3.3.1 DC Chip-Level Specifications ................... 17 3.3.2 DC General Purpose IO Specifications .... 17 3.3.3 DC Operational Amplifier Specifications ... 18 3.3.4 DC Analog Output Buffer Specifications ... 20 3.3.5 DC Switch Mode Pump Specifications ..... 21 3.3.6 DC Analog Reference Specifications ....... 22 3.3.7 DC Analog PSoC Block Specifications ..... 23 3.3.8 DC POR and LVD Specifications ............. 24 3.3.9 DC Programming Specifications ............... 25 3.4 AC Electrical Characteristics ................................ 26 3.4.1 AC Chip-Level Specifications ................... 26 3.4.2 AC General Purpose IO Specifications .... 28 3.4.3 AC Operational Amplifier Specifications ... 29 3.4.4 AC Digital Block Specifications ................. 31 3.4.5 AC Analog Output Buffer Specifications ... 32 3.4.6 AC External Clock Specifications ............. 33 3.4.7 AC Programming Specifications ............... 33 3.4.8 AC I2C Specifications ............................... 34 Packaging Information ............................................... 35 4.1 Packaging Dimensions ......................................... 35 4.2 Thermal Impedances .......................................... 40 4.3 Capacitance on Crystal Pins ............................... 40 Ordering Information .................................................. 41 5.1 Ordering Code Definitions ................................... 41 Sales and Company Information ............................... 42 6.1 Revision History .................................................. 42 6.2 Copyrights ............................................................ 42 2. 3. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations used to measure the PSoC devices. 4. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. 5. 6. June 4, 2004 Document No. 38-12011 Rev. *F 7 1. Pin Information This chapter describes, lists, and illustrates the CY8C24x23 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 8-Pin Part Pinout Type Table 1-1. 8-Pin Part Pinout (PDIP, SOIC) Pin No. 1 2 3 4 5 6 7 8 IO IO IO Power I I Digital IO IO IO Power Analog IO IO Pin Name P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Vdd Description Analog column mux input and column output. Analog column mux input and column output. Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Analog column mux input. Analog column mux input. Supply voltage. CY8C24123 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss 8 1 2 PDIP 7 3SOIC6 5 4 Vdd P0[4], AI P0[2], AI P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. June 2004 Document No. 38-12011 Rev. *F 8 CY8C24x23 Final Data Sheet 1. Pin Information 1.1.2 20-Pin Part Pinout Type Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO Power IO IO IO IO Input I I I I IO IO IO IO Power Digital IO IO IO IO Power Analog I IO IO I Pin Name P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. CY8C24223 20-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 PDIP SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. June 4, 2004 Document No. 38-12011 Rev. *F 9 CY8C24x23 Final Data Sheet 1. Pin Information 1.1.3 28-Pin Part Pinout Type Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO Power I I I I IO IO IO IO Input I I IO IO IO IO Power Digital IO IO IO IO IO IO IO IO Power I I Analog I IO IO I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. CY8C24423 28-Pin PSoC Device Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) External Voltage Reference (VRef) Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. June 4, 2004 Document No. 38-12011 Rev. *F 10 CY8C24x23 Final Data Sheet 1. Pin Information 1.1.4 32-Pin Part Pinout Type Table 1-4. 32-Pin Part Pinout (MLF*) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IO Power I IO IO I I I IO IO IO IO IO IO I I IO Input I I IO IO IO IO IO Power IO IO Digital IO IO IO IO Power Power I I Analog Pin Name P2[7] P2[5] P2[3] P2[1] Vss SMP P1[7] P1[5] NC P1[3] P1[1] Vss P1[0] P1[2] P1[4] NC P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] NC P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Description CY8C24423 PSoC Device P0[1], AI P0[3], AIO P0[5], AIO P0[7], AI Vdd P0[6], AI P0[4], AI NC 26 25 EXTCLK, P1[4] NC 16 Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) No connection. Do not use. Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) No connection. Do not use. Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) External Voltage Reference (VRef) Analog column mux input. Analog column mux input. No connection. Do not use. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. 32 31 P2[7] P2[5] AI, P2[3] AI, P2[1] Vss SMP I2C SCL, P1[7] I2C SDA, P1[5] 1 2 3 4 5 6 7 8 30 29 28 27 MLF (Top View) I2C SCL, XTALin, P1[1] Vss 9 10 11 12 LEGEND: A = Analog, I = Input, and O = Output. * The MLF package has a center pad that must be connected to the same ground as the Vss pin. June 4, 2004 Document No. 38-12011 Rev. *F I2C SDA, XTALout, P1[0] P1[2] NC P1[3] 13 14 15 24 23 22 21 20 19 18 17 P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] 11 2. Register Reference This chapter lists the registers of the CY8C27xxx PSoC device by way of mapping tables, in offset order. For detailed register information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. 2.1 2.1.1 Register Conventions Abbreviations Used 2.2 Register Mapping Tables The register conventions specific to this section are listed in the following table. Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific The PSoC device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is set, the user is said to be in the "extended" address space or the "configuration" registers. Note In the following register mapping tables, blank fields are Reserved and should not be accessed. May 2004 (c) Cypress MicroSystems, Inc. 2003 -- Document No. 38-12011 Rev. *F 12 CY8C24x23 Final Data Sheet 2. Register Reference Register Map Bank 0 Table: User Space Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 RW DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 RW DBB01DR0 24 # CMP_CR0 64 # DBB01DR1 25 W ASY_CR 65 # DBB01DR2 26 RW CMP_CR1 66 RW DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # 6C DCB03DR1 2D W 6D DCB03DR2 2E RW 6E DCB03CR0 2F # 6F 30 ACB00CR3 70 RW 31 ACB00CR0 71 RW 32 ACB00CR1 72 RW 33 ACB00CR2 73 RW 34 ACB01CR3 74 RW 35 ACB01CR0 75 RW 36 ACB01CR1 76 RW 37 ACB01CR2 77 RW 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDIOLT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # RW # RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # June 4, 2004 Document No. 38-12011 Rev. *F 13 CY8C24x23 Final Data Sheet 2. Register Reference Register Map Bank 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 RW DBB00IN 21 RW CLK_CR1 61 RW DBB00OU 22 RW ABF_CR0 62 RW 23 AMD_CR0 63 RW DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 RW 27 ALT_CR0 67 RW DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW 6C DCB03IN 2D RW 6D DCB03OU 2E RW 6E 2F 6F 30 ACB00CR3 70 RW 31 ACB00CR0 71 RW 32 ACB00CR1 72 RW 33 ACB00CR2 73 RW 34 ACB01CR3 74 RW 35 ACB01CR0 75 RW 36 ACB01CR1 76 RW 37 ACB01CR2 77 RW 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDIOLT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF RW RW RW RW RW RW RW RW RW RW RW R W W RW W RL # # June 4, 2004 Document No. 38-12011 Rev. *F 14 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C24x23 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. 5.25 4.75 Vdd Voltage O l i d ng Va rati n pe gi o Re 3.00 93 kHz CPU Frequency 12 MHz 24 MHz Figure 3-1. Voltage versus Operating Frequency The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol oC Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Symbol W Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms mA ms mV nA ns nV pA pF pp ppm ps sps V June 2004 Document No. 38-12011 Rev. *F 15 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.1 Symbol TSTG TA Vdd VIO - IMIO IMAIO - - Absolute Maximum Ratings Description Storage Temperature Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Static Discharge Voltage Latch-up Current Table 3-2. Absolute Maximum Ratings Min -55 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 - - - - - - - - - - Typ Max +100 +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 - 200 Units oC o Notes Higher storage temperatures will reduce data retention time. C V V V mA mA V mA 3.2 Symbol TA TJ Operating Temperature Description Ambient Temperature Junction Temperature Table 3-3. Operating Temperature Min -40 -40 - - Typ Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 40. The user must limit the power consumption to comply with this requirement. June 4, 2004 Document No. 38-12011 Rev. *F 16 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3 3.3.1 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-4. DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current Description - Min 3.00 - 5 Typ 8 Max 5.25 V Units mA Notes Conditions are Vdd = 5.0V, 25 oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC <= TA <= 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA <= 85 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC <= TA <= 55 oC. Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55 oC < TA <= 85 oC. Trimmed for appropriate Vdd. IDD3 Supply Current - 3.3 6.0 mA ISB ISBH ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.a Reference Voltage (Bandgap) - - - 3 4 4 6.5 25 7.5 A A A ISBXTLH - 5 26 A VREF 1.275 1.3 1.325 V a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. 3.3.2 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-5. DC GPIO Specifications Symbol RPU RPD VOH VOL VIL VIH VH IIL CIN COUT Pull up Resistor Pull down Resistor High Output Level Low Output Level Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output Description 4 4 Min Typ 5.6 5.6 - - - - 60 1 3.5 3.5 - - 10 10 8 8 - Max Units k k V V V V mV nA pF pF Notes Vdd - 1.0 - - 2.1 - - - - IOH = 10 mA, Vdd = 4.75 to 5.25V (80 mA maximum combined IOH budget) IOL = 25 mA, Vdd = 4.75 to 5.25V (150 mA maximum combined IOL budget) Vdd = 3.0 to 5.25 Vdd = 3.0 to 5.25 Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. 0.75 0.8 June 4, 2004 Document No. 38-12011 Rev. *F 17 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-6. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power Input Offset Voltage (absolute value) High Power - - - - - - Min Typ 1.6 1.3 1.2 7.0 20 4.5 - - 10 8 Max Units mV mV mV V/oC Notes 7.5 35.0 - 9.5 Vdd Vdd - 0.5 TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. 0.0 0.5 GOLOA Open Loop Gain Power = Low Power = Medium Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - - - - - - 60 - - dB VOHIGHOA High Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.5 200 400 800 1600 3200 6400 - V V V V V V A A A A A A VOLOWOA Low Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB June 4, 2004 Document No. 38-12011 Rev. *F 18 CY8C24x23 Final Data Sheet 3. Electrical Specifications Table 3-7. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power High Power is 5 Volt Only - - - - - 0.2 Min Typ 1.65 1.32 7.0 20 4.5 - 10 8 Max Units mV mV V/oC Notes TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range 35.0 - 9.5 Vdd - 0.2 pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA Open Loop Gain Power = Low Power = Medium Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 50 - - dB VOHIGHOA High Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High is 5V only - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.2 200 400 800 1600 3200 6400 - V V V V V V A A A A A A VOLOWOA Low Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB June 4, 2004 Document No. 38-12011 Rev. *F 19 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.4 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-8. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High - - - - 0.5 Min 3 +6 - 1 1 Typ 12 - Max Units mV V/C Notes Vdd - 1.0 - - - - V VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.1 - 0.5 x Vdd + 1.1 - V V VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High - - 60 1.1 2.6 - 5.1 8.8 - mA mA dB PSRROB Supply Voltage Rejection Ratio Table 3-9. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High - - - - 0.5 Min 3 +6 1 1 Typ 12 - Max Units mV V/C Notes Vdd - 1.0 - - - - V VOHIGHOB High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.0 - 0.5 x Vdd + 1.0 - V V VOLOWOB Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High - 50 0.8 2.0 - 2.0 4.3 - mA mA dB PSRROB Supply Voltage Rejection Ratio June 4, 2004 Document No. 38-12011 Rev. *F 20 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.5 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-10. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V IPUMP 5V Output voltage 3V Output voltage Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V VBAT5V VBAT3V VBATSTART VPUMP_Line VPUMP_Load VPUMP_Ripple Description Min 4.75 3.00 Typ 5.0 3.25 Max 5.25 3.60 V V Units Notes Average, neglecting ripple Average, neglecting ripple For implementation, which includes 2 uH inductor, 1 uF cap, and Schottky diode. 8 5 1.8 1.0 1.1 - - - 35 - - - - - - - 5 5 25 50 1.3 50 - - 5.0 3.3 - - - - - - - mA mA V V V %VOa %VOa mVpp % MHz % Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) Load Regulation Output Voltage Ripple (depends on cap/load) Efficiency Switching Frequency Switching Duty Cycle Configuration of note 2, load is 5mA. Configuration of note 2, load is 5mA, Vout is 3.25V. - FPUMP DCPUMP a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-14 on page 24. D1 Vdd C1 SMP Battery VBAT + PSoCTM Vss Figure 3-2. Basic Switch Mode Pump Circuit June 4, 2004 Document No. 38-12011 Rev. *F 21 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.6 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Table 3-11. 5V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - AGND = Vdd/2a CT Block Power = High AGND = 2 x BandGapa 2 x BG - 0.048 a Description Bandgap Voltage Reference 1.274 Min 1.30 Typ 1.326 Max V V V V V V V V V V V V V V V V V V Units Vdd/2 - 0.043 Vdd/2 - 0.025 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Vdd/2 + 0.003 2 x BG + 0.024 P2[4] + 0.014 BG + 0.016 1.6 x BG + 0.018 0.034 CT Block Power = High AGND = P2[4] (P2[4] = Vdd/2) CT Block Power = High AGND = BandGap a P2[4] - 0.013 BG - 0.009 1.6 x BG - 0.022 Vdd/2)a -0.034 CT Block Power = High AGND = 1.6 x BandGap a CT Block Power = High AGND Column to Column Variation (AGND = CT Block Power = High RefHi = Vdd/2 + BandGap Ref Control Power = High RefHi = 3 x BandGap Ref Control Power = High RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) Ref Control Power = High RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Ref Control Power = High RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Ref Control Power = High RefHi = 3.2 x BandGap Ref Control Power = High RefLo = Vdd/2 - BandGap Ref Control Power = High RefLo = BandGap Ref Control Power = High RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) Ref Control Power = High RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Ref Control Power = High RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Ref Control Power = High Vdd/2 + BG - 0.140 3 x BG - 0.112 2 x BG + P2[6] - 0.113 P2[4] + BG - 0.130 P2[4] + P2[6] - 0.133 3.2 x BG - 0.112 Vdd/2 + BG - 0.018 3 x BG - 0.018 2 x BG + P2[6] - 0.018 P2[4] + BG - 0.016 P2[4] + P2[6] - 0.016 3.2 x BG Vdd/2 + BG + 0.103 3 x BG + 0.076 2 x BG + P2[6] + 0.077 P2[4] + BG + 0.098 P2[4] + P2[6]+ 0.100 3.2 x BG + 0.076 Vdd/2 - BG - 0.051 BG - 0.082 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.057 Vdd/2 - BG + 0.024 BG + 0.023 2 x BG - P2[6] + 0.025 P2[4] - BG + 0.026 P2[4] - P2[6] + 0.026 Vdd/2 - BG + 0.098 BG + 0.129 2 x BG - P2[6] + 0.134 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.110 a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 2%. June 4, 2004 Document No. 38-12011 Rev. *F 22 CY8C24x23 Final Data Sheet 3. Electrical Specifications Table 3-12. 3.3V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - AGND = Vdd/2a CT Block Power = High AGND = 2 x BandGapa CT Block Power = High AGND = P2[4] (P2[4] = Vdd/2) CT Block Power = High AGND = BandGapa CT Block Power = High AGND = 1.6 x BandGapa 1.6 x BG - 0.027 Vdd/2)a -0.034 Not Allowed Not Allowed Not Allowed Not Allowed 0.000 0.034 mV 1.6 x BG - 0.010 1.6 x BG + 0.018 V CT Block Power = High AGND Column to Column Variation (AGND = CT Block Power = High RefHi = Vdd/2 + BandGap Ref Control Power = High RefHi = 3 x BandGap Ref Control Power = High RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Ref Control Power = High RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Ref Control Power = High RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Ref Control Power = High RefHi = 3.2 x BandGap Ref Control Power = High RefLo = Vdd/2 - BandGap Ref Control Power = High RefLo = BandGap Ref Control Power = High RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Ref Control Power = High RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Ref Control Power = High RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Ref Control Power = High P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V P2[4] + P2[6] - 0.075 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V BG - 0.009 BG + 0.005 BG + 0.015 V P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V Vdd/2 - 0.037 Not Allowed Vdd/2 - 0.020 Vdd/2 + 0.002 V Description Bandgap Voltage Reference 1.274 Min 1.30 Typ 1.326 Max V Units a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 2% 3.3.7 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-13. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) - - Min 80 Typ 12.24 - - Max fF Units k Notes June 4, 2004 Document No. 38-12011 Rev. *F 23 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.8 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 3-14. DC POR and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.963 3.033 3.185 4.110 4.550 4.632 4.719 4.900 3.023 3.095 3.250 4.194 4.643 4.727 4.815 5.000 3.083 3.157 3.315 4.278 4.736 4.822 4.911 5.100 V V V V V V V V V 2.863 2.963 3.070 3.920 4.393 4.550 4.632 4.718 2.921 3.023 3.133 4.00 4.483 4.643 4.727 4.814 2.979a 3.083 3.196 4.080 4.573 4.736b 4.822 4.910 V V V V V V V V V - - - 92 0 0 - - - mV mV mV - 2.816 4.394 4.548 - V V V - Description Vdd Value for PPOR Trip (positive ramp) Min Typ 2.908 4.394 4.548 - Max V V V Units Notes a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. June 4, 2004 Document No. 38-12011 Rev. *F 24 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.3.9 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-15. DC Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a - - 2.2 - - - Min 5 - - - - - - - - - Typ 25 0.8 - 0.2 1.5 Max V V Units mA Notes mA mA V V - - Years Driving internal pull-down resistor. Driving internal pull-down resistor. Vss + 0.75 Vdd - - - Vdd - 1.0 50,000 1,800,000 10 Erase/write cycles per block. Erase/write cycles. Flash Data Retention a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. June 4, 2004 Document No. 38-12011 Rev. *F 25 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4 3.4.1 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-16. AC Chip-Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW Description Internal Main Oscillator Frequency CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time Min 23.4 0.93 0.93 0 0 15 - - - 0.5 0.5 - - - 10 40 - 46.8 - - 0 24 24 12 48 24 32 Typ Max 24.6a 24.6a,b 12.3b,c 49.2a,b,d 24.6b,e,d 64 - - 600 10 50 2620 3800f - 60 - 49.2a,c 12.3 - Units MHz MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms ns s Notes Trimmed. Utilizing factory trim values. Refer to the AC Digital Block Specifications below. 32.768 23.986 - - - 1700 2800 100 - 50 50 48.0 600 - - Accuracy is capacitor and crystal dependent. 50% duty cycle. Is a multiple (x732) of crystal frequency. TOS TOSACC Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP % kHz MHz ps MHz s Trimmed. Utilizing factory trim values. a. b. c. d. e. f. 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. 3.0V < 5.25V. The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 3-3. PLL Lock Timing Diagram June 4, 2004 Document No. 38-12011 Rev. *F 26 CY8C24x23 Final Data Sheet 3. Electrical Specifications PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 3-5. External Crystal Oscillator Startup Timing Diagram Jitter24M1 F24M Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram Jitter32k F32K2 Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram June 4, 2004 Document No. 38-12011 Rev. *F 27 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.2 AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-17. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min - - - 27 22 Typ 12 18 18 - - Max Units MHz ns ns ns ns Notes Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% 90% GPIO Pin 10% TRiseF TRiseS TFallF TFallS Figure 3-8. GPIO Timing Diagram June 4, 2004 Document No. 38-12011 Rev. *F 28 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.3 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 3-18. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High - - - - - - Min Typ Max Units Notes Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. - 3.9 s s s - - 0.72 0.62 s s s TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High - - - - - - 0.15 - - 0.72 - 0.92 - 5.9 s s s s s s Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High 6.5 0.01 - - 1.7 - V/s V/s V/s V/s V/s V/s V/s V/s V/s 0.5 4.0 0.75 - - - V/s V/s V/s MHz MHz MHz 3.1 5.4 - - - 200 - MHz MHz MHz nV/rt-Hz Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. BWOA Gain Bandwidth Product Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) June 4, 2004 Document No. 38-12011 Rev. *F 29 CY8C24x23 Final Data Sheet 3. Electrical Specifications Table 3-19. 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) - - - - - - Min Typ Max Units Notes Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. - 3.92 s s s - - - 0.72 - - s s s TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) - - - - - - 0.31 - - - - 0.72 - - - 5.41 s s s s s s Specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) 2.7 - - 0.24 - - - - - - V/s V/s V/s V/s V/s V/s V/s V/s V/s 1.8 - - 0.67 - - - - - - V/s V/s V/s MHz MHz MHz 2.8 - - - - - - 200 - - - MHz MHz MHz nV/rt-Hz Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. BWOA Gain Bandwidth Product Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High (3.3 Volt High Bias Operation not supported) Power = High, Opamp Bias = High (3.3 Volt High Power, High Opamp Bias not supported) Specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) June 4, 2004 Document No. 38-12011 Rev. *F 30 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.4 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-20. AC Digital Block Specifications Function Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50a 50 - - - - - 50a - - a Description Min 50a - - 50a - - - - - - - - Typ - Max Units ns MHz MHz ns MHz MHz Notes 49.2 24.6 - 49.2 24.6 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. - - - - - - - - - - 16 - - - 49.2 49.2 24.6 8.2 4.1 - 16.4 49.2 ns ns ns MHz MHz MHz MHz ns ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). June 4, 2004 Document No. 38-12011 Rev. *F 31 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.5 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-21. 5V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.65 0.65 - - - - V/s V/s 0.65 0.65 - - - - V/s V/s - - - - 2.2 2.2 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - Min - - Typ Max 2.5 2.5 Units s s Notes Table 3-22. 3.3V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz 0.5 0.5 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 2.6 2.6 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - Min - - Typ Max 3.8 3.8 Units s s Notes June 4, 2004 Document No. 38-12011 Rev. *F 32 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.6 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-23. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description 0 Min - - - - Typ Max 24.24 - - - Units MHz ns ns s Notes 20.6 20.6 150 Table 3-24. 3.3V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1 a Min 0 0 41.7 41.7 150 - - - - - Typ Max 12.12 24.24 - - - Units MHz MHz ns ns s Notes Frequency with CPU Clock divide by 2 or greaterb High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 3.4.7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-25. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - Min - - - - - 15 30 - Typ 20 20 - - 8 - - 45 Max Units ns ns ns ns MHz ms ms ns Notes June 4, 2004 Document No. 38-12011 Rev. *F 33 CY8C24x23 Final Data Sheet 3. Electrical Specifications 3.4.8 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only or unless otherwise specified. Table 3-26. AC Characteristics of the I2C SDA and SCL Pins Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0 a Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition 0 Min 4.0 4.7 4.0 4.7 0 250 4.0 - - - - - - - - - Max 100 Max 400 - - - - - - - - 50 Units kHz s s s s s Notes ns s s Bus Free Time Between a STOP and START Condition 4.7 Pulse Width of spikes are suppressed by the input filter. - ns a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus June 4, 2004 Document No. 38-12011 Rev. *F 34 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C24x23 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. 4.1 Packaging Dimensions 51-85075 - *A Figure 4-1. 8-Lead (300-Mil) PDIP May 2004 (c) Cypress MicroSystems, Inc. 2003 -- Document No. 38-12011 Rev. *F 35 CY8C24x23 Final Data Sheet 4. Packaging Information 51-85066 *B 51-85066 - *C Figure 4-2. 8-Lead (150-Mil) SOIC 20-Lead (300-Mil) Molded DIP P5 51-85011-A 51-85011 - *A Figure 4-3. 20-Lead (300-Mil) Molded DIP June 4, 2004 Document No. 38-12011 Rev. *F 36 CY8C24x23 Final Data Sheet 4. Packaging Information 51-85077 - *C Figure 4-4. 20-Lead (210-Mil) SSOP 51-85024 - *B Figure 4-5. 20-Lead (300-Mil) Molded SOIC June 4, 2004 Document No. 38-12011 Rev. *F 37 CY8C24x23 Final Data Sheet 4. Packaging Information 51-85014 - *C Figure 4-6. 28-Lead (300-Mil) Molded DIP 51-85079 - *C Figure 4-7. 28-Lead (210-Mil) SSOP June 4, 2004 Document No. 38-12011 Rev. *F 38 CY8C24x23 Final Data Sheet 4. Packaging Information 51-85026 - *C Figure 4-8. 28-Lead (300-Mil) Molded SOIC X = 138 MIL Y = 138 MIL 32 51-85188 - ** Figure 4-9. 32-Lead (5x5 mm) MLF June 4, 2004 Document No. 38-12011 Rev. *F 39 CY8C24x23 Final Data Sheet 4. Packaging Information 4.2 Thermal Impedances Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF Table 4-1. Thermal Impedances per Package Typical JA * 123 oC/W 185 oC/W 109 oC/W 117 oC/W 81 oC/W 69 oC/W 101 oC/W 74 oC/W 22 oC/W * TJ = TA + POWER x JA 4.3 Capacitance on Crystal Pins Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF Table 4-2: Typical Package Capacitance on Crystal Pins Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.0 pF June 4, 2004 Document No. 38-12011 Rev. *F 40 5. Ordering Information The following table lists the CY8C24x23 PSoC Device family's key package features and ordering codes. Table 5-1. CY8C24x23 PSoC Device Family Key Features and Ordering Information Analog Outputs Analog Blocks (Columns of 3) Digital IO Pins Analog Inputs Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range 8 Pin (300 Mil) DIP 8 Pin (150 Mil) SOIC 8 Pin (150 Mil) SOIC (Tape and Reel) 20 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin (300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 32 Pin (5x5 mm) MLF CY8C24123-24PI CY8C24123-24SI CY8C24123-24SIT CY8C24223-24PI CY8C24223-24PVI CY8C24223-24PVIT CY8C24223-24SI CY8C24223-24SIT CY8C24423-24PI CY8C24423-24PVI CY8C24423-24PVIT CY8C24423-24SI CY8C24423-24SIT CY8C24423-24LFI 4 4 4 4 4 4 4 4 4 4 4 4 4 4 256 256 256 256 256 256 256 256 256 256 256 256 256 256 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 16 16 16 16 24 24 24 24 24 24 4 4 4 8 8 8 8 8 10 10 10 10 10 10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 5.1 Ordering Code Definitions Package Type: P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended CY 8 C 24 xxx-SPxx June 4, 2004 Document No. 38-12011 Rev. *F XRES Pin Ordering Code Package Flash (Kbytes) RAM (Bytes) 41 |
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