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XR-T7295
...the analog plus company TM
DS3/Sonet STS-1 Integrated Line Receiver
June 1997-3
FEATURES D Fully Integrated Receive Interface for DS3 and STS-1 Rate Signals D Integrated Equalization (Optional) and Timing Recovery D Loss-of-Signal and Loss-of-Lock Alarms D Variable Input Sensitivity Control D 5V Power Supply D Pin Compatible with XR-T7295E D Companion Device to T7296 Transmitter
APPLICATIONS D Interface to DS-3 Networks D Digital Cross-Connect Systems D CSU/DSU Equipment D PCM Test Equipment D Fiber Optic Terminals
GENERAL DESCRIPTION The XR-T7295 DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1 (51.84Mbps) signal transmitted over coaxial cable. (See Figure 13). The device also provides the functions of receive equalization (optional), automatic-gain control (AGC), clock-recovery and data retiming, loss-of-signal and loss-of-frequency-lock detection. The digital system interface is dual-rail, with received positive and negative 1s appearing as unipolar digital signals on separate output leads. The on-chip equalizer is designed for cable distances of 0 to 450ft. from the cross-connect frame to the device. The receive input has a variable input sensitivity control, providing three different sensitivity ORDERING INFORMATION
Operating Temperature Range -40C to + 85C -40C to + 85C
settings, to adapt longer cables. High input sensitivity allows for significant amounts of flat loss within the system. Figure 1 shows the block diagram of the device. The XR-T7295 device is manufactured using linear CMOS technology. The XR-T7295 is available in either a 20-pin plastic DIP or 20-pin plastic SOJ package for surface mounting. Two versions of the chip are available, one is for either DS3 or STS-1 operation (the XR-T7295, this data sheet), and the other is for E3 operation (the XR-T7295E, refer to the XR-T7295E data sheet). Both versions are pin compatible. For either DS3 or STS-1, an input reference clock at 44.736MHz or 51.84MHz provides the frequency reference for the device.
Part No. XR-T7295IP XR-T7295IW
Package 20 Lead 300 Mil PDIP 20 Lead 300 Mil JEDEC SOJ
Rev. 1.05
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-T7295
BLOCK DIAGRAM
III IIII III IIII IIIII IIIII I IIIIII IIIIIIIIIIII III IIIIII IIIIIII III IIIIII III III I III III I I III III IIIIIIII III IIIIIIII IIIIIIII III IIIIIIIII I I II IIIIIIII III IIIIIIII II II IIIIIIIIIII IIIIIIIIII I II
REQB 18 4 5 20 1 11 9 12 10 2 Attenuator Gain & Equalizer Slicers Phase Detector Loop Filter VCO RIN Retimer Peak Detector 19 AGC Frequency Phase Aquisition Circuit Digital LOS Detector LOSTHR Analog LOS Analog LOS 7 Equalizer Tuning Ckt. 17 3 6 13 8 ICT TMC1 TMC2 EXCLK RLOL
LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC
14 RCLK
16 RPDATA 15 RNDATA
RLOS
Figure 1. Block Diagram
Rev. 1.05 2
XR-T7295
PIN CONFIGURATION
GNDA RIN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VDDA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK VDDC VDDD
GNDA RIN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDDA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK VDDC VDDD
20 Lead PDIP (0.300")
20 Lead SOJ (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3,6 4,5 7 8 9 10 11 12 13 Symbol GNDA RIN TMC1-TMC2 LPF1-LPF2 RLOS RLOL GNDD GNDC VDDD VDDC EXCLK I Type I I I O O Description Analog Ground. Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series with 50 k. Test Mode Control 1 and 2. Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. PLL Filter 1 and 2. An external capacitor (0.1F $20%) is connected between these pins. Receive Loss-of-signal. This pin us set high on loss of the data signal at the receive input. (See Table 7) Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock. Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with PLL clock. Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with EXCLK. 5V Digital Supply ($10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 5V Digital Supply ($10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. External Reference Clock. A valid DS3 (44.736MHz $100ppm) or STS-1 (51.84MHz + 100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD /2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns. Receive Clock. Recovered clock signal to the terminal equipment. Receive Negative Data. Negative pulse data output to the terminal equipment. (See Figure 11.) Receive Positive Data. Positive pulse data output to the terminal equipment. (See Figure 11) In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-circuit testing. There is an internal pull-up on this pin. Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low places the equalizer in the data path. Loss-of-signal Threshold Control. The voltage forced on this pin controls the input lossof-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin must be set to the desired level upon power-up and should not be changed during operation. 5V Analog Supply ($10%).
14 15 16 17
RCLK RNDATA RPDATA ICT
O O O I
18 19
REQB LOSTHR
I I
20
VDDA
Rev. 1.05 3
XR-T7295
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = -40C to +85C, VDD = 5V$10% Typical Values are for VDD = 5.0 V, 25C, and Random Data. Maximum Values are for VDD = 5.5V all 1s Data.
Symbol IDD Parameter Power Supply Current DS3 REQB = 0 REQB = 1 STS-1 REQB = 0 REQB = 1 Logic Interface Characteristics Input Voltage VIL VIH Low High Output Voltage VOL VOH CI CL IL Low High Input Capacitance Load Capacitance Input Leakage -10 20 10 -50 GNDD VDDD0.5 0.4 VDDD 10 10 10 500 100 -5 V V pF pF A A A A -0.5 to VDD + 0.5V (all input pins except 2 and 17) 0 V (pin 17) VDD (pin 2) GNDD (pin 2) -5.0mA 5.0mA GNDD VDDD0.5 0.5 VDDD V V 87 83 111 108 mA mA 82 79 106 103 mA mA Min. Typ. Max. Unit Condition
Electrical Characteristics
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Storage Temperature . . . . . . . . . . . . -40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Rev. 1.05 4
XR-T7295
System A 0-450 ft. 0-450 ft. System B
XR-T7296 Transmitter
Frame
DSX-3 or STSX-1
Type 728A Coaxial Cable
Figure 2. Application Diagram
SYSTEM DESCRIPTION Receive Path Configurations In the receive signal path (see Figure 1), the internal equalizer can be included by setting REQB = 0 or bypassed by setting REQB = 1. The equalizer bypass option allows easy interfacing of the XR-T7295 device into systems already containing external equalizers. Figure 3 illustrates the receive path options. In Case 1 of Figure 3, the signal from the DSX-3 cross-connect feeds directly into RIN. In this mode, the user should set REQB = 0, engaging the equalizer in the data path. Table 1 and the following sections describe the receive signal requirements. In Case 2 of Figure 3, external line build-out (LBO) and equalizer networks precede the XR-T7295 device. In this mode, the signal at RIN is already equalized, and the on-chip filters should be bypassed by setting REQB=1. The signal at RIN must meet the amplitude limits described in Table 1 In applications where the XR-T7295 device is used to monitor DS3 transmitter outputs directly, the receive equalizer should be bypassed. Again, the signal at RIN must meet the amplitude limits described in Table 1. Minimum signals are for SOJ devices. Due to increased package parasitics, add 3dB to all table values for DIP devices. Maximum input amplitude under all conditions is 850mV pk.
Rev. 1.05 5
Although system designers typically use power in dBm to describe input levels, the XR-T7295 responds to peak input signal amplitude. Therefore, the XR-T7295 input signal limits are given in mV pk. Conversion factors are as follows: At DSX3: 390mV pk ' 0 dBm At DSX3 + 450 ft. of cable: 310 mV pk ' 0 dBm
Data Rate DS3 Minimum Signal 80 60 40 80 80 80 110 80 60 110 110 110
REQB 0
STS-1
Table 1. Receive Input Signal Amplitude Requirements
IIIII IIIII IIIII I
XR-T7295 Receiver
IIII IIII IIII IIIII IIII
Cross Connect
IIII IIII IIII
LOSTHR 0 VDD/2 VDD
Unit mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pK mV pk
1
0 VDD/2 VDD
0
0 VDD/2 VDD
1
0 VDD/2 VDD
XR-T7295
CASE 1:
0-450 ft.
0
D
0.01F
S
75
X
CASE 2:
0-450 ft.
Existing Off-chip Networks
Rev. 1.05 6
IIIIII III IIIIII III IIIIII IIIIII IIIIII I I IIIIII IIIIII IIIIIIIIII IIII I IIIIII IIIIII IIIIIIIIII IIII
D
S
225 ft. LBO
X
Closed For 225-450 ft. Of Cable
Figure 3. Receiver Configurations
IIIIII IIIIII IIIIII IIIIII IIIIII
REQB RIN LPF1 XR-T7295 LPF2 1 0.01F Fixed Equalizer RIN 75
III III I I IIIIIIIIII IIII IIII IIIIIII IIIIII IIII
0.1F
REQB
LPF1
0.1F
LPF2 XR-T7295
XR-T7295
DS3 SIGNAL REQUIREMENTS AT THE DSX Pulse characteristics are specified at the DSX-3, which is an interconnection and test point referred to as the cross-connect (see Figure 2.) The cross-connect exists at the point where the transmitted signal reaches the Table 2 lists the signal distribution frame jack. requirements. Currently, two isolated pulse template requirements exist: the ACCUNET T45 pulse template (see Table 3 and Figure 4) and the G.703 pulse template (see Table 4 and Figure 5). Table 3 and Table 5 give the associated boundary equations for the templates. The XR-T7295 correctly decodes any transmitted signal that meets one of these templates at the cross-connect.
Parameter Line Rate Line Code Test Load Pulse Shape
Specification 44.736 Mbps 20 ppm Bipolar with three-0 substitution (B3ZS) 75 5% An isolated pulse must fit the template in Figure 4 or Figure 5.1 The pulse amplitude may be scaled by a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk, measured at the center of the pulse. For and all 1s transmitted pattern, the power at 22.368 $ 0.002MHz must be -1.8 to +5.7dBm, and the power at 44.736 $0.002MHz must be -21.8dBm to -14.3dBm.2, 3
Power Levels
Notes 1 The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 4. The proposed G.703 standards further state that the voltage in a time slot containing a 0 must not exceed $ 5% of the peak pulse amplitude, except for the residue of preceding pulses. 2 The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands. 3 The all 1s pattern must be a pure all 1s signal, without framing or other control bits.
Table 2. DSX-3 Interconnection Specification
Lower Curve Time T -0.36 -0.36 T +0.28 0.28 T 0.5 Equation 0 1+sin /2 [1+T/0.18] Time T-0.68 -0.68 T +0.36 0.36 T 0.5 Upper Curve Equation 0 1+sin/2 [ 1+T/0.34]
0.11e-3.42(T-0.3)
0.05 + 0.407e-1.84(T-0.36)
Table 3. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See Figure 4.)
Rev. 1.05 7
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-0.5 0 0.5 1.0 1.5 Time Slots - Normalized To Peak Location 0.36 T 2.0
XR-T7295
1.0
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0 -1.0 Time Slots - Normalized To Peak Location -0.5 0 0.5 1.0 1.5
Rev. 1.05 -0.36 T+0.28 T -0.36 0.28 T Time
Table 4. DSX-3 Pulse Template Boundaries for G.703 Standards (See Figure 5)
Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards
Lower Curve
Figure 5. DSX-3 Isolated Pulse Template for G.703 Standards
Normalized Amplitude
0.2
0.4
0.6
0.8
0.2
Normalized Amplitude
0.4
0.6
0.8
1.0
0.5 1+sin /2 [1+T/0.18]
0 -1.0
0.11e-3.42(T-0.3)
Function
0
8 -0.65 T 0 0 T 0.36 T -0.65 Time 2.0 Upper Curve 0.5 1+sin/2 [ 1+T/0.34] 1.05 1-e-4.6(T+0.65) Function 0 0.05+0.407e-1.84(T-0.36)
XR-T7295
STS-1 SIGNAL REQUIREMENTS AT THE STSX For STS-1 operation, the cross-connect is referred at the STSX-1. Table 5 lists the signal requirements at the STSX-1. Instead of the DS3 isolated pulse template, an eye diagram mask is specified for STS-1 operation (TA-TSY-000253). The XR-T7295 correctly decodes any transmitted signal that meets the mask shown in Figure 6 at the STSX-1.
Parameter Line Rate Line Code Test Load Power Levels 51.84 Mbps Bipolar with three-0 substitution (B3ZS) 75$5% A wide-band power level measurement at the STSX-1 interface using a low-pass filter with a 3dB cutoff frequency of at least 200MHz is within -2.7 dBm and 4.7 dBm. Specification
Table 5. STSX-1 Interconnection Specification
1.0 Normalized Amplitude 0.8 0.6 0.4 0.2
0 -1.0
Figure 6. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253 LINE TERMINATION AND INPUT CAPACITANCE The recommended receive termination is shown in Figure 3 The 75 resistor terminates the coaxial cable with its characteristic impedance. The 0.01F capacitor to RIN couples the signal into the receive input without disturbing the internally generated DC bias level present on RIN. The input capacitance at the RIN pin is 2.8pF typical (SOJ package) and 3.6pF typical (DIP package). The distribution frame jack may introduce 0.6 $0.55 dB of loss. This loss may be any combination of flat or shaped (cable) loss. The maximum cable distance between the point where the transmitted signal exits the distribution frame jack and the XR-T7295 device is 450 ft. (see Figure 2.) The coaxial cable (Type 728A) used for specifying this distance limitation has the loss and phase characteristics shown in Figure 7 and Figure 8. Other cable types also may be acceptable if distances are scaled to maintain cable loss equivalent to Type 728A cable loss. TIMING RECOVERY External Loop Filter Capacitor The signal at the cross-connect may travel through a distribution frame, coaxial cable, connector, splitters, and back planes before reaching the XR-T7295 device. This section defines the maximum distribution frame and cable loss from the cross-connect to the XR-T7295 input.
Rev. 1.05 9
LOSS LIMITS FROM THE DSX-3 TO THE RECEIVE INPUT
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-0.5 0 0.5 1.0 1.5 2.0 Time Slots - Normalized To Peak Location
Figure 3 shows the connection to an external 0.1F capacitor at the LPF1/LPF2 pins. This capacitor is part of the PLL filter. A non-polarized, low-leakage capacitor should be used. A ceramic capacitor with the value 0.1F $ 20% is acceptable.
XR-T7295
OUTPUT JITTER The total jitter appearing on the RCLK output during normal operation consists of two components. First, some jitter appears on RCLK because of jitter on the incoming signal. (The next section discusses the jitter transfer characteristic, which describes the relationship between input and output jitter.) Second, noise sources within the XR-T7295 device and noise sources that are coupled into the device through the power supplies and data pattern dependent jitter due to misequalization of the input signal, all create jitter on RCLK. The magnitude of this internally generated jitter is a function of the PLL bandwidth, which in turn is a function of the input 1s density. For higher 1s density, the amount of generated jitter decreases. Generated jitter also depends on the quality of the power supply bypassing networks used. Figure 12 shows the suggested bypassing network, and Table 6 lists the typical generated jitter performance.
10
80 Phase (Degree)
8
60
6
40
4
2
20
0
1.0
2.0
5.0 10 20 Frequency (MHz)
50
100
Figure 7. Loss Characteristic of 728A Coaxial Cable (450 ft.) JITTER TRANSFER CHARACTERISTIC The jitter transfer characteristic indicates the fraction of input jitter that reaches the RCLK output as a function of input jitter frequency. Table 6 shows Important jitter transfer characteristic parameters. Figure 9 also shows a typical characteristic, with the operating conditions as described in Table 6. Although existing standards do not specify jitter transfer characteristic requirements, the XR-T7295 information is provided here to assist in evaluation of the device.
Generated Jitter1 All 1s pattern Repetitive "100" pattern Jitter Transfer Characteristic2 Peaking f 3dB 0 05 0.05 205 0 0.1 d dB kHz 1.0 1.5 ns peak-to-peak ns peak-to-peak
Notes 1 Repetitive input data pattern at nominal DSX-3 level with V DD = 5V TA = 25C. 2 Repetitive "100 " input at nominal DSX-3 level with V DD = 5V, TA = 25C.
Table 6. Generated Jitter and Jitter Transfer Characteristics
Rev. 1.05 10
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0 1.0 2.0 5.0 10 20 Frequency (MHz) 50 100
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12
100
Loss (dB)
Figure 8. Phase Characteristic of 728A Coaxial Cable (450 ft.)
Parameter
Typ
Max
Unit
XR-T7295
JITTER ACCOMMODATION Under all allowable operating conditions, the jitter accommodation of the XR-T7295 device exceeds all system requirements for error-free operation (BER<1E-9). The typical (VDD = 5V, T = 25C, DSX-3 nominal signal level) jitter accommodation for the XR-T7295 is shown in Figure 10. FALSE-LOCK IMMUNITY False-lock is defined as the condition where a PLL recovered clock obtains stable phase-lock at a frequency not equal to the incoming data rate. The XR-T7295 device uses a combination frequency/phase-lock architecture to prevent false-lock. An on-chip frequency comparator continuously compares the EXCLK reference to the PLL clock. If the frequency difference between the EXCLK and PLL clock exceeds approximately $0.5%, correction circuitry forces re-acquisition of the proper frequency and phase. ACQUISITION TIME If a valid input signal is assumed to be already present at RIN, the maximum time between the application of device power and error-free operation is 20ms. If power has already been applied, the interval between the application of valid data (or the action of valid data following a loss of signal) and error-free operation is 4ms. LOSS-OF-LOCK DETECTION As stated above, the PLL acquisition aid circuitry monitors the PLL clock frequency relative to the EXCLK frequency. The RLOL alarm is activated if the difference between the PLL clock and the EXCLK frequency exceeds approximately $0.5%. This will not occur until at least 250 bit periods after loss of input data.
Magnitude Response (dB)
1 0 -1 -2 -3 -4 -5
40
TR-TSY-000499 Category 2
10
TR-TSY-000499 Category 1
XR-T7295 Typical
G.824
PUB 54014
1.0
0.1
1
10
100
1K
10K
100K
1000K
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev. 1.05 11
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Peak-Peak Sinewave Jitter (U.I.)
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PEAK = 0.05dB f3dB = 205kHz 100
500 1K 5K 10K 50K100K 500K Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer Characteristic
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XR-T7295 Typical
Jitter Frequency (Hz) 5k 10k 60k 300k 1M
Jitter Amplitude (U.I.) 10 5 1 0.5 0.4
XR-T7295
A high RLOL output indicates that the acquisition circuit is working to bring the PLL into proper frequency lock. RLOL remains high until frequency lock has occurred; however, the minimum RLOL pulse width is 32 clock cycles. PHASE HITS In response to a phase hit in the input data, the XR-T7295 returns to error free operation in less than 2ms. During the requisition time, RLOS may temporarily be indicated. LOSS-OF-SIGNAL DETECTION To allow for varying levels of noise and crosstalk in different applications, three loss-of-signal threshold settings are available using the LOSTHR pin. Setting LOSTHR = VDD provides the lowest loss-of-signal threshold; LOSTHR = VDD/2 (can be produced using two 50 k $10% resistors as a voltage divider between VDDD and GNDD) provides an intermediate threshold; and LOSTHR = GND provides the highest threshold. The LOSTHR pin must be set to its desired value at power-up and must not be changed during operation. DIGITAL DETECTION In addition to the signal amplitude monitoring of the analog LOS detector, the digital LOS detector monitors the recovered data 1s density. The RLOS alarm goes high if 160 $32 or more consecutive 0s occur in the receive data stream. The alarm goes low when at least ten 1s occur in a string of 32 consecutive bits. This hysteresis prevents RLOS chattering and guarantees a minimum RLOS pulse width of 32 clock cycles. Note, however, that RLOS chatter can still occur. When REQB=1, input signal levels above the analog RLOS threshold can still be low enough to result in a high bit error rate. The resultant data stream (containing) errors can temporarily activate the digital LOS detector, and RLOS chatter can occur. Therefore, RLOS should not be used as a bit error rate monitor. RLOS chatter can also occur when RLOL is activated (high).
Figure 1 shows that analog and digital methods of loss-of-signal (LOS) detection are combined to create the RLOS alarm output. RLOS is set if either the analog or digital detection circuitry indicates LOS has occurred.
ANALOG DETECTION The analog LOS detector monitors the peak input signal amplitude. RLOS makes a high-to-low transition (input signal regained) when the input signal amplitude exceeds the loss-of signal threshold defined in Table 7. The RLOS low-to-high transition (input signal loss) occurs at a level typically 1.0 dB below the high-to-low transition level. The hysteresis prevents RLOS chattering. Once set, the RLOS alarm remains high for at least 32 clock cycles, allowing for system detection of a LOS condition without the use of an external latch.
Rev. 1.05 12
XR-T7295
Data Rate DS3 REQB 0 LOSTHR 0 VDD/2 VDD 1 0 VDD/2 VDD STS-1 0 0 VDD/2 VDD 1 0 VDD/2 VDD Min. Threshold 60 40 25 45 30 20 75 50 30 55 35 25 Max. Threshold 220 145 90 175 115 70 275 185 115 220 145 90 Unit mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk mV pk
Notes - Lower threshold is 1.5 dB below upper threshold. - The RLOS alarm is an indication of the presence of an input signal, not a bit error rate indication. Table 1 gives the minimum input amplitude needed for error free operation (BER < 1e- 9) Independent of the RLOS state, the device will attempt to recover correct timing data. The RLOS low-to-high transition typically occurs 1dB below the high to low transition.
Table 7. Analog Loss-of-Signal Thresholds RECOVERED CLOCK AND DATA TIMING IN-CIRCUIT TEST CAPABILITY When pulled low, the ICT pin forces all digital output buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL pins) to be placed in a high output impedance state. This feature allows in-circuit testing to be done on neighboring devices without concern for XR-T7295 device buffer damage. An internal pull-up device (nominally 50k) is provided on this pin therefore, users can leave this pin unconnected for normal operation. Test equipment can pull ICT low during in-circuit testing without damaging the device. This is the only pin for which internal pull-up/pull-down is provided.
Table 8 and Figure 11 summarize the timing relationships between the logic signals RCLK, RPDATA, and RNDATA. The duty cycle is referenced to VDD/2 threshold level. RPDATA and RNDATA change on the rising edge of RCLK and are valid during the falling edge of RCLK. A positive pulse at RIN creates a high level on RPDATA and a low level on RNDATA. A negative pulse at the input creates a high level on RNDATA and a low level on RPDATA, and a received zero produces low levels on both RPDATA and RNDATA.
Rev. 1.05 13
XR-T7295
TIMING CHARACTERISTICS Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40C TA +85C, VDD = 5V $10%
Symbol tRCH1RCH2 tRCL2RCL1 tRDVRCL tRCLRDX tRCHRDV Parameter Clock Rise Time (10% - 90%) Clock Fall Time (10% - 90%) Receive Data Set-up Time Receive Data Hold Time Receive Propagation Clock Duty Cycle Delay1 5.0 8.5 0.6 45 50 3.7 55 Min Typ Max 3.5 2.5 Unit ns ns ns ns ns %
Notes 1 The total delay from R to the digital outputs RPDATA and RNDATA is three and a half RCLK clocks. IN
Table 8. System Interface Timing Characteristics
tRCHRDV
tRCL2RCL1
tRCH1RCH2
RCLK (RC) RPDATA OR RNDATA (RD)
tRDVRCL
tRCLRDX
Figure 11. Timing Diagram for System Interface BOARD LAYOUT CONSIDERATIONS Power Supply Bypassing input pin. Any noise coupled into the XR-T7295 input directly degrades the signal-to-noise ratio of the input signal and may degrade sensitivity. PLL Filter Capacitor The PLL filter capacitor between pins LPF1 and LPF2 must be placed as close to the chip as possible. The LPF1 and LPF2 pins are adjacent, allowing for short lead lengths with no crossovers to the external capacitor. Noise-coupling into the LPF1 and LPF2 pins may degrade PLL performance. Handling Precautions Receive Input The connections to the receive input pin, RIN, must be carefully considered. Noise-coupling must be minimized along the path from the signal entering the board to the
Rev. 1.05 14
Figure 12 illustrates the recommended power supply bypassing network. A 0.1F capacitor bypasses the digital supplies. The analog supply VDDA is bypassed by using a 0.1F capacitor and a shield bead that removes significant amounts of high-frequency noise generated by the system and by the device logic. Good quality, high-frequency (low lead inductance) capacitors should be used. Finally, it is most important that all ground connections be made to a low-impedance ground plane.
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting.
XR-T7295
C4 0.1F GNDA VDDA Sensitive Node
COMPLIANCE SPECIFICATIONS D Compliance with AT&T Publication 54014, "ACCUNET R T45 Service Description and Interface Specifications," June 1987. D Compliance with ANSI Standard T1.102-1989, "Digital Hierarchy - Electrical Interfaces, " 1989. D Compliance with Compatibility Bulletin 119, "Interconnection Specification for Digital Cross-Connects," October 1979.
+5V
XR-T7295
Shield Bead1
GNDD GNDC
VDDC VDDD 0.1F C6
D Compliance with CCITT Recommendations G.703 and G.824, 1988. D Compliance with TR-TSY-000499, "Transport Systems Generic Requirements (TSGR): Common Requirements," December 1988. D Compliance with TA-TSY-000253, "Synchronous Optical Network (SONET) Transport System Generic Criteria," February 1990.
Notes 1 Recommended shield beads are the Fair-Rite 2643000101 or the Fair-Rite 2743019446 (surface mount).
Figure 12. Recommended Power Supply Bypassing Network
Rev. 1.05 15
XR-T7295
VCC RI EC QT B 5 678
OUTPUTS RECEIVER MONITOR
S1 SW DIP-4
RLOS
RLOL
4321
L O S T H R
VCC
2134 5678 R22 22K 11111119 5 64 3 2 1 0 3 2 4 5 26 25 11 12 1 2 3 4 5 6 7 8 SW DIP-8 17 RCLKO RCLKO RPOS 15 14 RNRZ RNEG RECEIVER OUTPUTS S2 16 15 14 13 12 11 10 9 LLOOP RLOOP T3/E3 TAOS TXLEV ICT ENCODIS DECODIS
1357 TP TP R21 22K 24 6 8 19 18 17 14 15 16
U1 XR-T7295
INPUT SIGNAL B1 C2 8 7 2 RLOL RLOS RIN R2 75 EXTERNAL CLOCK B2 13 EXCLK R6 75 C3 0.1F 5 LPF2 V D D A 20 BT1 FERRITE BEAD C4 0.1F 0.1F V D D C V D D D C6 GNDC GNDD 4 LPF1 1 10 9 TMC1 TMC2 R5 0.01F LOSTHR REQB ICT/ RCLK RNDATA RPDATA
U2 XR-T7296
LLOOP R7 R8 R10 39 39 39 1 28 27 RLOOP DS3,STS-1/E3/ TAOS ICT/ TXLEV ENCODIS DECODIS
RCLK RNDATA RPDATA
P2 3 6 50 TCLK B5 9 TCLK R1 50 GND
RPOS RNEG RNRZ
16
GNDA
B4 TNDATA 8 TNDATA
B3 TPDATA 7 TPDATA
TRING
22
R4
36
T1
B6
TTIP
11 21
TTIP MRING MTIP GNDD DMO 18 13 DMO BPV V D D A 24 V D D D BT2 6 GNDA
23 R15 19 20 10 21 R16 270 270
R3
36 PE65966
TRING
P1
TRANSFORMER # PULSE ENGINEERING PE 65966 PE 65967 IN SURFACE MOUNT
VCC RX C7 0.1F + E1 22F
BPV TRANSMITER MONITOR OUTPUTS
C8 0.1F
P3 VCC TX
FERRITE BEAD # FAIR RITE 2643000101
C9 0.1F
FERRITE BEAD
+E2 22F
C5 0.1F
Figure 13. Typical Application Schematic
Rev. 1.05 16
XR-T7295
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
20 1 D
11 10 E1 E A2
Seating Plane
A L A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.925 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 1.060 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 23.50 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 26.92 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 1.05 17
XR-T7295
20 LEAD SMALL OUTLINE J LEAD (300 MIL JEDEC SOJ)
Rev. 1.00
D
20
11
E
1 10
H
A2 Seating Plane e B C A1 R E1
A
INCHES SYMBOL A A1 A2 B C D E E1 e H R MIN 0.145 0.025 0.120 0.014 0.008 0.496 0.292 0.262 MAX 0.200 --0.140 0.020 0.013 0.512 0.300 0.272
MILLIMETERS MIN 3.60 0.64 3.05 0.36 0.20 12.60 7.42 6.65 MAX 5.08 --3.56 0.51 0.30 13.00 7.62 6.91
0.050 BSC 0.335 0.030 0.347 0.040
1.27 BSC 8.51 0.76 8.81 1.02
Note: The control dimension is the inch column
Rev. 1.05 18
XR-T7295 Notes
Rev. 1.05 19
XR-T7295
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1992 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.05 20

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