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| x CMOS Low Power Consumption x 2 Voltage Detectors Built-in x Detect Voltage Accuracy: 2% x Detect Voltage Range: 1.5V ~ 5.0V x SOT-25 Package s General Description The XC612 series consist of 2 voltage detectors, in 1 mini-molded, SOT25 package. The series provides accuracy and low power consumption through CMOS processing and laser trimming and consists of a highly accurate voltage reference source, 2 comparators, hysteresis and output driver circuits. The input (VIN1) for voltage detector 1 (VD1) dually functions as the power supply pin for both detector 1 (VD1) and detector 2 (VD2). s Applications q Memory battery back-up circuitry q Microprocessor reset circuits q Power failure detection q System power-on reset circuits q System battery life monitors and re-charge voltage monitors q Delay circuitry q s Features Highly accurate: Set-up voltage accuracy 2% Low-power consumption: Typ.2.0A (VIN1=VIN2=2.0V, quiescent state) Detect voltage: 1.5V ~ 5.0V programmable in 0.1V steps. Detector's voltages can be set-up independently Operating Voltage Range: 1.5V ~ 10.0V Temperature characteristics: 100ppm/: Output configuration: N-channel open drain Small package: SOT-25 (150mW) mini-mold * CMOS Output is under development s Pin Configuration VDET2 5 VIN2 4 s Pin Assignment PIN NUMBER 1 2 3 4 5 PIN NAME VDET1 VIN1 VSS VIN2 VDET2 FUNCTION Voltage Detector 1 output Detector 1 input, Power Supply. Ground Voltage Detector 2 Input Voltage Detector 2 Output SOT-25 (TOP VIEW) 1 VDET1 2 VIN1 3 VSS s Block Diagram VIN VDET1 s Absolute Maximum Ratings PARAMETER Input Voltage VIN1 Input Voltage VIN2 Output Voltage VDET1 Output Current VDET1 Output Voltage VDET2 Output Current VDET2 Power Dissipation SYMBOL VIN1 VIN2 VVDET1 IVDET1 VVDET2 IVDET2 Pd Topr Tstg CONDITIONS 12 VSS-0.3 ~ VIN1+0.3 VSS-0.3 ~ 12 50 VSS-0.3 ~ 12 50 150 -30 ~ +80 -40 ~ +125 UNITS V V V mA V mA mW : : VIN2 VDET2 Operating Ambient Temperature Storage Temperature VSS Vref s Electrical Characteristics PARAMETER SYMBOL VDF1 VDF2 VHYS1 VHYS2 CONDITIONS Voltage when VDET1 changes from H to L following a reduction of VIN1 Voltage when VDET2 changes from H to L following a reduction of VIN2 Voltage (VDR1) - VDF1 when VDET1 changes from L to H following an increase of VIN1 Voltage (VDR2) - VDF2 when VDET2 changes from L to H following an increase of VIN2 VIN1=1.5V 2.0V 3.0V 4.0V 5.0V VIN1=1.5V 2.0V 3.0V 4.0V 5.0V VDF (T) = 1.5V to 5.0V Nch Output Current* IVDET VDS = 0.5V VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V -30: Topr 80: 1.5 0.3 3.0 5.0 6.0 7.0 2.2 7.7 10.1 11.5 13.0 100 MIN VDF1 x 0.98 VDF2 x 0.98 TYP VDF1 VDF2 MAX VDF1 x 1.02 VDF1 x 1.02 UNITS CIRCUIT V V V 1 1 1 1 Detect Voltage VDET1 Detect Voltage VDET2 Hysteresis Range 1 Hysteresis Range 2 q VDF1(T) VDF1(T) VDF1(T) x 0.02 x 0.05 x 0.08 VDF2(T) VDF2(T) VDF2(T) x 0.02 x 0.05 x 0.08 1.35 1.50 1.95 2.40 3.00 0.45 0.50 0.65 0.80 1.00 3.90 4.50 5.10 5.70 6.30 1.30 1.50 1.70 1.90 2.10 10 Supply Current ISS A 2 Input Current VIN2 IIN2 A 2 Operating Voltage VIN V - mA 3 Temperature Characteristics* Transient Delay Time* (Release Voltage Output Conversion) 1. 2. 3. 4. VDF Topr * VDF tDLY ppm/: - (VDR VOUT conversion) 0.2 ms 4 VDF1(T), VDF2(T) : User specified detect voltage. Release voltage (VDR) = VDF +VHYS Those parameters marked with an asterisk apply to both VDET1 and VDET2. Input Voltage : please ensure that VIN1 VIN2 s Timing Chart (Pull up voltage =Input voltage VIN1) 6 Input Voltage (VIN1) Release Voltage (VDR1) Detect Voltage (VDF1) q Min. Operating Voltage (VMIN) Ground Voltage (VSS) Input Voltage (VIN1) Release Voltage (VDR2) Detect Voltage (VDF2) 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) Output Voltage (VDET1) 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) Output Voltage (VDET2) 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) 1 2 3 A 4 5 1 2 3 B 4 5 s Operational Notes Timing Chart A (VIN1=voltages above release voltage, VIN2=sweep voltage) Because a voltage higher than the minimum operating voltage is applied to the voltage input pin (VIN), ground voltage will be output at the output pin (VDET) during stage 3. (Stages 1, 2, 4, 5 are the same as in B below). Timing Chart B (VIN1=VIN2) 1. When a voltage greater than the release voltage (VDR) is applied to the voltage input pin (VIN1, VIN2), input voltage (VIN1, VIN2) will gradually fall. When a voltage greater than the detect voltage (VDF) is applied to the voltage input pin (VIN1, VIN2), a state of high impedance will exist at the output pin (VDET1, VDET2), so should the pin be pulled up, voltage will be equal to pull up voltage. When input voltage (VIN1, VIN2) falls below detect voltage (VDF), output voltage (VDET1, VDET2) will be equal to ground level (VSS). Should input voltage (VIN1, VIN2) fall below the minimum operational voltage (VMIN), output will become unstable. Should VIN2 fall below VMIN, voltage at the output pin (VDET2) will be equal to ground level (VSS) if the power supply (VIN1) is within the operating voltage range. *In general the output pin is pulled up so output will be equal to pull up voltage. Should input voltage (VIN1, VIN2) rise above ground voltage (VSS), output voltage (VDET1, VDET2) will equal ground level until the release voltage level (VDR) is reached. When input voltage (VIN1, VIN2) rises above release voltage, the output pin's (VDET1, VDET2) voltage will be equal to the voltage dependent on pull up. 2. 3. 4. 5. Note : The difference between release voltage (VDR) and detect voltage (VDF) is the Hysteresis Range (6). s Ordering Information XC612xxxxxMx ab c de q DESIGNATOR a DESCRIPTION Output Configuration: N=N-Channel Open Drain Detect Voltage (VDET1) e.g.25=2.5V 38=3.8V Detect Voltage (VDET2) e.g.33=3.3V 50=5.0V DESIGNATOR DESCRIPTION d Package Type: M=SOT-25 b e c Device Orientation R=Embossed Tape (Orientation of Device: Right) L=Embossed Tape (Orientation of Device: Left) s Marking Represents the output configuration SYMBOL N CONFIGURATION Nch open drain Represents the entry order. Denotes the production lot Number 0 to 9, A to Z repeated. (G, I, J, O, W excepted) SOT-25 (TOP VIEW) s Notes on Use 1. 2. 3. 4. 5. 6. Please ensure that input voltage VIN2 is less than VIN1 + 0.3V. (refer to N.B. 1 below) With a resistor connected between the VIN1 pin and the input, oscillation is liable to occur as a result of through current at the time of release. (refer to N.B. 2 below) With a resistor connected between the VIN1 pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN1 pin. In order to stabilise the IC's operations, please ensure that the VIN1 pin's input frequency's rise and fall times are more than 5 sec/V. Should the power supply voltage VIN1 exceed 6V, voltage detector 2's detect voltage (VDF2) and the release voltage (VDR2) will shift somewhat. Please use this IC within the specified maximum absolute ratings. q s N.B. 1. Voltage detector 2's input voltage (VIN2) An input protect diode is connected from input detector 2's input (VIN2) to input detector 1's input. Therefore, should the voltage applied to VIN2 exceed VIN1, current will flow through VIN1 via the diode. (refer to diagram1) 2. Oscillation as a result of through current Since the XC612 series are CMOS ICs, through current will flow when the IC's internal circuit switching operates (during release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current's resistor (RIN) during release voltage operations. (refer to diagram 2) Since hysteresis exists during detect operations, oscillation is unlikely to occur. Input XC612N Series RIN VIN1 VIN2 RIN x ISS* voltage drop XC612N Series VIN1 VIN2 VSS VDET1 VDET2 ISS* (includes through current) Diagram 1. Voltage detector 2's input voltage VIN2 Diagram 2. Through current oscillation s Standard Circuits Circuit 1. q VIN1 VIN2 VDET1 VDET2 VSS V VDF1, VDF2 VHYS1, VHYS2 R 100k Circuit 2. ISS A VIN1 A VIN2 VDET1 VDET2 VSS IIN2 VIN Circuit 3. VIN1 VIN VIN2 VDET1 IVDET A VDET2 VSS Circuit 4. VIN waveform measurement VDR Time VIN1 VIN2 VDET1 VDET2 VSS tDLY R 100k waveform measurement Time VDET s Typical Application Circuits q Window comparator circuit VIN VIN R R VOUT VIN1 VIN2 VSS VSS VSS VSS Time VDET1 VDET2 VDF1 VDF2 VSS VOUT q Time q Detect voltages above respective established voltages circuit VDD VIN R R1 VIN1 VIN2 VSS VDET1 VDET2 VOUT R2 VSS VSS Notes on resistors R1 and R2's (1), (2) functions : Detect voltage = { (R1 + R2) / R2} x VDF2 N.B. VDF2 = detect voltage VD2 Please set-up so that Hysteresis (VHYS2) = { (R1 + R2) / } x VHYS2 (1) (2) Note : Please ensure that input voltage 2 (VIN2) is less than VIN1 + 0.3V q Voltage detect circuit with delay built-in VDD R R1 VIN1 VIN2 R2 VSS VSS VSS VDET1 VDET2 Note : Delay operates at both times of release and detect operations. s XC612 Electrical Characteristics (1) SUPPLY CURRENT vs. INPUT VOLTAGE SUPPLY CURRENT: Iss (A) INPUT VOLTAGE: VIN1 (V) INPUT CURRENT: IIN2 (A) q INPUT VOLTAGE: VIN2 (V) (2) DETECT & RELEASE VOLTAGE vs. AMBIENT TEMPERATURE DETECT, RELEASE VOLTAGE : VDF1, VDR1 (V) AMBIENT TEMP.: Topr (:) DETECT, RELEASE VOLTAGE : VDF2, VDR2 (V) AMBIENT TEMP.: Topr (:) Note : Unless otherwise stated, pull up resistance = 100k with Nch open drain output types. (3) OUTPUT VOLTAGE vs. INPUT VOLTAGE OUTPUT VOLTAGE: VDET1 (V) INPUT VOLTAGE: VIN1 (V) OUTPUT VOLTAGE: VDET2(V) INPUT VOLTAGE: VIN2 (V) s XC612 Electrical Characteristics (4) N-CH DRIVER OUTPUT CURRENT vs. VDS OUTPUT CURRENT: IVDET1 (mA) OUTPUT CURRENT: IVET2 (mA) q OUTPUT CURRENT: IVET1 ( A) (5) N-CH DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE OUTPUT CURRENT: IVDET2 (mA) INPUT VOLTAGE: VIN1 (V) OUTPUT CURRENT: IVET1 (mA) OUTPUT CURRENT: IVET2 ( A) INPUT VOLTAGE: VIN2 (V) |
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