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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PM4318
OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DATASHEET
PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 3: APRIL 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
CONTENTS 1 FEATURES........................................................................................................................ 1 1.1 1.2 2 3 4 5 6 7 8 9 EACH RECEIVER SECTION: .............................................................................. 2 EACH TRANSMITTER SECTION:....................................................................... 2
APPLICATIONS................................................................................................................. 4 REFERENCES .................................................................................................................. 5 APPLICATION EXAMPLES............................................................................................... 7 BLOCK DIAGRAM............................................................................................................. 9 DESCRIPTION ................................................................................................................ 11 PIN DIAGRAM................................................................................................................. 12 PIN DESCRIPTION......................................................................................................... 13 FUNCTIONAL DESCRIPTION ........................................................................................ 35 9.1 9.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 OCTANTS........................................................................................................... 35 RECEIVE INTERFACE ...................................................................................... 35 CLOCK AND DATA RECOVERY (CDRC).......................................................... 36 RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38 T1 INBAND LOOPBACK CODE DETECTOR (IBCD) ....................................... 38 T1 PULSE DENSITY VIOLATION DETECTOR (PDVD) ................................... 39 PERFORMANCE MONITOR COUNTERS (PMON).......................................... 39 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION (PRBS) ............................................................................................................... 39 T1 INBAND LOOPBACK CODE GENERATOR (XIBC)..................................... 39 PULSE DENSITY ENFORCER (XPDE)............................................................. 39 TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 40 LINE TRANSMITTER......................................................................................... 44 TIMING OPTIONS (TOPS) ................................................................................ 44
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
1.14
SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE ................... 44 1.14.1 INTERFACING OCTLIUS TO A HIGH DENSITY FRAMER.................. 45
1.15 1.16 1.17 1.18 1.19 1.20 2
SBI EXTRACTER AND PISO............................................................................. 46 SBI INSERTER AND SIPO ................................................................................ 46 SBI TO CLK/DATA CONVERTER ...................................................................... 46 SERIAL PROM INTERFACE.............................................................................. 46 JTAG TEST ACCESS PORT.............................................................................. 48 MICROPROCESSOR INTERFACE ................................................................... 48
NORMAL MODE REGISTER DESCRIPTION ................................................................ 49 2.1 NORMAL MODE REGISTER MEMORY MAP................................................... 50
3
TEST FEATURES DESCRIPTION................................................................................ 169 3.1 JTAG TEST PORT............................................................................................ 169
4
OPERATION.................................................................................................................. 172 4.1 4.2 4.3 4.4 4.5 4.6 4.7 CONFIGURING THE OCTLIU FROM RESET................................................. 172 SERVICING INTERRUPTS.............................................................................. 172 USING THE PERFORMANCE MONITORING FEATURES ............................ 173 USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 173 USING THE LINE RECEIVER ......................................................................... 194 USING THE PRBS GENERATOR AND DETECTOR ...................................... 201 LOOPBACK MODES ....................................................................................... 201 4.7.1 4.7.2 4.8 LINE LOOPBACK................................................................................ 201 DIAGNOSTIC DIGITAL LOOPBACK .................................................. 202
JTAG SUPPORT .............................................................................................. 202 4.8.1 TAP CONTROLLER ............................................................................ 204
5
FUNCTIONAL TIMING .................................................................................................. 210 5.1 SBI BUS INTERFACE TIMING ........................................................................ 210
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
5.2 5.3 6 7 8 9
LINE CODE VIOLATION INSERTION ............................................................. 211 ALARM INTERFACE........................................................................................ 213
ABSOLUTE MAXIMUM RATINGS ................................................................................ 214 D.C. CHARACTERISTICS ............................................................................................ 215 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................. 217 OCTLIU TIMING CHARACTERISTICS......................................................................... 221 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 RSTB TIMING (FIGURE 33) ............................................................................ 221 XCLK INPUT TIMING (FIGURE 34)................................................................. 221 TRANSMIT SERIAL INTERFACE (FIGURE 35) .............................................. 222 RECEIVE SERIAL INTERFACE (FIGURE 36)................................................. 223 SBI INTERFACE (FIGURE 37 TO FIGURE 39)............................................... 224 SERIAL PROM (SPI) INTERFACE (FIGURE 40) ............................................ 227 ALARM INTERFACE (FIGURE 41).................................................................. 228 INGRESS CLK/DATA INTERFACE (FIGURE 42)............................................ 228 EGRESS CLK/DATA INTERFACE (FIGURE 43) ............................................. 229 JTAG PORT INTERFACE (FIGURE 44) .......................................................... 230
10 11
ORDERING AND THERMAL INFORMATION .............................................................. 232 MECHANICAL INFORMATION ..................................................................................... 233
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
LIST OF FIGURES FIGURE 1 FIGURE 2 FIGURE 3 FIGURE 4 FIGURE 5 FIGURE 6 FIGURE 7 FIGURE 8 FIGURE 9 FIGURE 10 FIGURE 11 FIGURE 12 FIGURE 13 FIGURE 14 FIGURE 15 FIGURE 16 FIGURE 17 FIGURE 18 FIGURE 19 FIGURE 20 FIGURE 21 FIGURE 22 FIGURE 23 FIGURE 24 - T1/E1 FRAMER/TRANSCEIVER APPLICATION................................................. 7 - HIGH DENSITY T1/E1 FRAMER/TRANSCEIVER APPLICATION ...................... 7 - HIGH DENSITY LEASED LINE CIRCUIT EMULATION APPLICATION.............. 7 - METRO OPTICAL ACCESS EQUIPMENT .......................................................... 8 - OCTLIU BLOCK DIAGRAM - LIUS ENABLED ................................................... 9 - OCTLIU BLOCK DIAGRAM - SBI TO CLK/DATA CONVERTER, LIUS DISABLED .......................................................................................................... 10 - PIN DIAGRAM.................................................................................................... 12 - EXTERNAL ANALOGUE INTERFACE CIRCUITS ............................................ 35 - T1 JITTER TOLERANCE ................................................................................... 37 - COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER . 38 - TJAT JITTER TOLERANCE ............................................................................... 41 - TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY........................ 42 - TJAT JITTER TRANSFER.................................................................................. 43 - SBI TO FRAMER LINE SIDE INTERFACE ........................................................ 45 - SERIAL PROM CASCADE INTERFACE ........................................................... 46 - SERIAL PROM COMMAND FORMAT ............................................................... 47 - TRANSMIT TIMING OPTIONS........................................................................... 75 - LINE LOOPBACK............................................................................................. 202 - DIAGNOSTIC DIGITAL LOOPBACK................................................................ 202 - BOUNDARY SCAN ARCHITECTURE ............................................................. 203 - TAP CONTROLLER FINITE STATE MACHINE ............................................... 205 - INPUT OBSERVATION CELL (IN_CELL) ........................................................ 208 - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE).......................... 208 - BIDIRECTIONAL CELL (IO_CELL) .................................................................. 209
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iv
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
FIGURE 25 FIGURE 26 FIGURE 27 FIGURE 28 FIGURE 29 FIGURE 30 FIGURE 31 FIGURE 32 FIGURE 33 FIGURE 34 FIGURE 35 FIGURE 36 FIGURE 37 FIGURE 38 FIGURE 39 FIGURE 40 FIGURE 41 FIGURE 42 FIGURE 43 FIGURE 44
- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ..................... 209 - SBI BUS FUNCTIONAL TIMING ...................................................................... 210 - B8ZS LINE CODE VIOLATION INSERTION ................................................... 211 - HDB3 LINE CODE VIOLATION INSERTION................................................... 212 - AMI LINE CODE VIOLATION INSERTION ...................................................... 213 - LOS ALARM SERIAL OUTPUT........................................................................ 213 - MICROPROCESSOR INTERFACE READ TIMING......................................... 218 - MICROPROCESSOR INTERFACE WRITE TIMING ....................................... 220 - RSTB TIMING................................................................................................... 221 - XCLK INPUT TIMING ....................................................................................... 221 - TRANSMIT SERIAL INTERFACE TIMING DIAGRAM..................................... 222 - RECEIVE SERIAL INTERFACE TIMING DIAGRAM ....................................... 223 - SBI FRAME PULSE TIMING............................................................................ 224 - SBI ADD BUS TIMING ..................................................................................... 225 - SBI DROP BUS TIMING .................................................................................. 226 - SPI INTERFACE TIMING ................................................................................. 227 - ALARM INTERFACE TIMING........................................................................... 228 - INGRESS CLK/DATA INTERFACE TIMING DIAGRAM................................... 229 - EGRESS CLK/DATA INTERFACE TIMING DIAGRAM.................................... 229 - JTAG PORT INTERFACE TIMING ................................................................... 231
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
v
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16 TABLE 17 TABLE 18 TABLE 19 TABLE 20 TABLE 21 TABLE 22 TABLE 23 - EXTERNAL COMPONENT DESCRIPTIONS .................................................... 36 - SERIAL PROM COMMANDS - CODE BITS ..................................................... 47 - SERIAL PROM SPECIAL COMMANDS ............................................................ 47 - NORMAL MODE REGISTER MEMORY MAP ................................................... 50 - CLOCK SYNTHESIS MODE .............................................................................. 65 - TJAT FIFO OUTPUT CLOCK SOURCE ............................................................ 74 - TJAT PLL SOURCE............................................................................................ 74 - INSBI TRIBUTARY CHARACTERISTICS .......................................................... 89 - EXSBI TRIBUTARY CHARACTERISTICS....................................................... 105 - EXSBI CLOCK GENERATION OPTIONS........................................................ 106 - TRANSMIT IN-BAND CODE LENGTH ............................................................ 114 - LOOPBACK CODE CONFIGURATIONS......................................................... 126 - LOSS OF SIGNAL THRESHOLDS .................................................................. 131 - TRANSMIT OUTPUT AMPLITUDE .................................................................. 148 - ALOS DETECTION/CLEARANCE THRESHOLDS.......................................... 154 - EQUALIZATION FEEDBACK FREQUENCIES................................................ 161 - VALID PERIOD................................................................................................. 162 - BOUNDARY SCAN REGISTER....................................................................... 170 - DEFAULT SETTINGS....................................................................................... 172 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB)175 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 7.5 DB) .......................................................................................................................... 176 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 15 DB) .......................................................................................................................... 177 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 22.5 DB) .......................................................................................................................... 178
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
vi
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 40 TABLE 41 TABLE 42 TABLE 43
- T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.) .......................................................................................................................... 179 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 - 220 FT.) ............................................................................................................. 180 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 - 330 FT.) ............................................................................................................. 181 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 - 440 FT.)............................................................................................................. 182 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 - 550 FT.) ............................................................................................................. 183 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 - 660 FT.) ............................................................................................................. 184 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB) .......................................................................................................................... 185 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.)186 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 - 220 FT.) ............................................................................................................. 187 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 - 330 FT.) ............................................................................................................. 188 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 - 440 FT.) ............................................................................................................. 189 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 - 550 FT.) ............................................................................................................. 190 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 - 660 FT.) ............................................................................................................. 191 - TRANSMIT WAVEFORM VALUES FOR E1 120 OHM.................................... 192 - TRANSMIT WAVEFORM VALUES FOR E1 75 OHM...................................... 193 - RLPS REGISTER PROGRAMMING................................................................ 194 - RLPS EQUALIZER RAM TABLE (T1 MODE) .................................................. 195 - RLPS EQUALIZER RAM TABLE (E1 MODE) .................................................. 198 - RLPS EQUALIZER RAM TABLE (MONITOR MODE) ..................................... 201 - ABSOLUTE MAXIMUM RATINGS ................................................................... 214
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
vii
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
TABLE 44 TABLE 45 TABLE 46 TABLE 47 TABLE 48 TABLE 49 TABLE 50 TABLE 51 TABLE 52 TABLE 53 TABLE 54 TABLE 55 TABLE 56 TABLE 57 TABLE 58 TABLE 59 TABLE 60 TABLE 61 TABLE 62
- D.C. CHARACTERISTICS ............................................................................... 215 - MICROPROCESSOR INTERFACE READ ACCESS ...................................... 217 - MICROPROCESSOR INTERFACE WRITE ACCESS..................................... 219 - RTSB TIMING................................................................................................... 221 - XCLK INPUT TIMING ....................................................................................... 221 - TRANSMIT SERIAL INTERFACE .................................................................... 222 - RECEIVE SERIAL INTERFACE....................................................................... 223 - CLOCKS AND SBI FRAME PULSE ................................................................. 224 - SBI ADD BUS ................................................................................................... 225 - SBI DROP BUS ................................................................................................ 225 - SPI INTERFACE............................................................................................... 227 - ALARM INTERFACE ........................................................................................ 228 - INGRESS CLK/DATA INTERFACE .................................................................. 228 - ENGRESS CLK/DATA INTERFACE................................................................. 229 - JTAG PORT INTERFACE................................................................................. 230 - ORDERING INFORMATION ............................................................................ 232 - OCTLIU THETA JC........................................................................................... 232 - OCTLIU JUNCTION TEMPERATURE ............................................................. 232 - OCTLIU THETA JA VS. AIRFLOW ................................................................... 232
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
viii
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
1 * * *
FEATURES Monolithic device which integrates eight T1/J1 or E1 short haul and long haul line interface circuits. Software switchable between T1/J1 and E1 operation on a per-device basis. Meets or exceeds T1/J1 and E1 shorthaul and longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR12 and CTR-13. Provides encoding and decoding of B8ZS, HDB3 and AMI line codes. Provides receive equalization, clock recovery and line performance monitoring. Provides transmit and receive jitter attenuation. Provides digitally programmable long haul and short haul line build out. Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy. Provides PRBS generators and detectors on each tributary for error testing at DS1 and E1 rates as recommended in ITU-T O.151. Provides either serial clock/data or parallel Scaleable Bandwidth Interconnect (SBI) interfaces on the system side. Can be configured to act as a converter between the SBI interfaces and serial clock/data. In this mode, the LIUs are unused. Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. Provides a hardware-only (no microprocessor) mode in which configuration data is read from an SPIcompatible serial PROM. The PROM interface can be cascaded such that multiple OCTLIU devices can be configured simultaneously from a single PROM. Uses line rate system clock. Provides an IEEE 1149.1 (JTAG) compliant Test Access Port (TAP) and controller for boundary scan test. Implemented in a low power 3.3 V tolerant 1.8/3.3 V CMOS technology. Available in a high density 288-pin Tape-SBGA (23 mm by 23 mm) package. Provides a -40C to +85C Industrial temperature operating range.
* * * * * * * * * *
* * * * *
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
1
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
1.1 * * * * * * * * * * *
Each Receiver Section: Supports T1 signal reception for distances with up to 36 dB of cable attenuation at nominal conditions using PIC 22 gauge cable emulation. Supports E1 signal reception for distances with up to 36 dB of cable attenuation at nominal conditions using PIC 22 gauge cable emulation. Supports G.772 compliant non-intrusive protected monitoring points. Recovers clock and data using a digital phase locked loop for high jitter tolerance. Tolerates more than 0.3 UI peak-to-peak; high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170. Outputs either dual rail recovered line pulses, a single rail DS-1/E1 signal or parallel data in SBI bus format. Performs B8ZS or AMI decoding when processing a bipolar DS-1 signal and HDB3 or AMI decoding when processing a bipolar E1 signal. Detects line code violations (LCVs), B8ZS/HDB3 line code signatures, and 4 (E1+HDB3), 8 (T1+B8ZS) or 16 (AMI) successive zeros. Accumulates up to 8191 line code violations (LCVs), for performance monitoring purposes, over accumulation intervals defined by the period between software write accesses to the LCV register. Detects loss of signal (LOS), which is defined as 10, 15, 31, 63, or 175 successive zeros. Detects programmable inband loopback activate and deactivate code sequences received in the DS1 data stream when they are present for 5.1 seconds. Optionally, enters loopback mode automatically on detection of an inband loopback code. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. A pseudo-random sequence user selectable from 2 -1, 2 -1 or 2 -1, may be detected in the T1/E1 stream in either the receive or transmit directions. The detector counts pattern errors using a 24-bit saturating PRBS error counter. Each Transmitter Section: Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s backplane buses. Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements. Generates E1 pulses compliant to G.703 recommendations.
11 15 20
* *
1.2 * * *
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
2
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
* * *
Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom long haul pulse shaping applications. Provides line outputs that are current limited and may be tristated for protection or in redundant applications. Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path. Allows bipolar violation (BPV) transparent operation for error restoring regenerator applications. Allows bipolar violation (BPV) insertion for diagnostic testing purposes. Supports all ones transmission for alarm indication signal (AIS) generation. Accepts either dual rail or single rail DS-1/E1 signals or parallel data from the SBI interface. Performs B8ZS or AMI encoding when processing a single rail or SBI-sourced DS-1 signal and HDB3 or AMI encoding when processing a single rail or SBI-sourced E1 signal. A pseudo-random sequence user selectable from 2 -1, 2 -1 or 2 -1, may be inserted into or detected from the T1 or E1 stream in either the receive or transmit directions. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density. Supports transmission of a programmable unframed inband loopback code sequence.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
3
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
2 * * * * * * * * * *
APPLICATIONS Metro Optical Access Equipment Edge Router Linecards Multiservice ATM Switch Linecards 3G Base Station Controllers (BSC) 3G Base Transceiver Stations (BTS) Digital Private Branch Exchanges (PBX) Digital Access Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX) T1/E1 Repeaters Test Equipment SBI to clk/data converter in multi-service access equipment.
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4
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
3
REFERENCES 1. ANSI - T1.102-1993 - American National Standard for Telecommunications - Digital Hierarchy - Electrical Interfaces. 2. ANSI - T1.107-1995 - American National Standard for Telecommunications - Digital Hierarchy - Formats Specification. 3. ANSI - T1.403-1999 - American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification. 4. ANSI - T1.408-1990 - American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification. 5. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, December 1990. 6. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 1, March 1991. 7. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 2, October 1992. 8. TR-TSY-000170 - Bellcore - Digital Cross-Connect System Requirements and Objectives, Issue 1, November 1985. 9. TR-N1WT-000233 - Bell Communications Research - Wideband and Broadband Digital Cross-Connect Systems Generic Criteria, Issue 3, November 1993. 10. TR-NWT-000303 - Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, Issue 2, December, 1992. 11. TR-TSY-000499 - Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, Issue 5, December, 1993. 12. ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992. 13. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates. 14. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995. 15. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993. 16. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
5
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17. FCC Rules - Part 68.308 - Signal Power Limitations. 18. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital Interface, Geneva, 1998. 19. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1998. 20. ITU-T Recommendation G.772 - Protected Monitoring Points Provided on Digital Transmission Systems, 1992. 21. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1998. 22. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993. 23. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993. 24. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital Systems at the Primary Bit Rate and Above, 1992. 25. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1995. 26. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995. 27. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 - Specification, 1995. 28. Nippon Telegraph and Telephone Corporation - Technical Reference for High-Speed Digital Leased Circuit Services, Third Edition, 1990.
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6
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
4
APPLICATION EXAMPLES Figure 1 - T1/E1 Framer/Transceiver Application
Clock and Data 8 x T1 lines
OCTLIU
PM4318
TOCTL
PM4388
Octal T1 Framer
Backplane
Clock and Data 8 x E1 lines
OCTLIU
PM4318
EOCTL
PM6388
Octal E1 Framer
Backplane
Figure 2
- High Density T1/E1 Framer/Transceiver Application
SBI H-MVIP or SBI
32 T1/J1 or E1 lines
OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318
TE32
PM4332
T1/J1/E1 Framer
4xOCTLIU
Figure 3
- High Density Leased Line Circuit Emulation Application
SBI
32 T1/J1 or E1 lines
OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318
Utopia L2
AAL1gator 32
PM73122
AAL1 SAR
ATM Backbone
4xOCTLIU
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7
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 4
- Metro Optical Access Equipment
SBI Telecom Bus
84 T1/J1 or 63 E1 lines
OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318
TEMAP-84
PM5366
T1/E1 VT/TU Mapper Cross Connect
11xOCTLIU or 8xOCTLIU
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
8
5 Figure 5 BLOCK DIAGRAM
DATASHEET
PMC- 2001578
PRELIMINARY
TXTIP1[8:1] TXTIP2[8:1] TDN[8:1] TDP[8:1] TCLK[8:1] TJAT Digital Jitter Attenuator LCODE AMI / B8ZS / HDB3 Line Encoder XPDE Pulse Density Enforcer XIBC Inband Loopback Code Generator
TXRING1[8:1] TXRING2[8:1]
XLPG Transmit LIU
ISSUE 3
EXSBI-8 SBI Extract PMON Performance Monitor (Line Loopback) PRBS Pattern Generator / Detector
ADATA[7:0] ADP APL AV5 REFCLK AC1FP DC1FP C1FPOUT
(Diagnostic Digital Loopback)
INSBI-8 SBI Insert
DDATA[7:0] DDP DPL DV5 DACTIVE RDP[8:1] RDN/RLCV[8:1] RCLK[8:1]
RXTIP[8:1] CDRC Clk/Data Recovery PDVD Pulse Density Viol. Detector RJAT Digital Jitter Attenuator
- OCTLIU Block Diagram - LIUs Enabled
RXRING[8:1]
RLPS Receive LIU
IBCD Inband Loop back Code Detector
LIU Octant x 8
SBI2CLK SBI_EN RSTB VCLK FBLOW H/W only Auto-config
XCLK JTAG uP Interface
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
TOPS Timing Options LOS Serial Output ALE CSB TDI RDB TCK INTB WRB D[7:0] A[10:0] SRCEN SRCDO LOS TDO TMS SRDI SREN SRDO TRSTB SRCLK SRCCLK LEN8[2:0] LEN7[2:0] LEN6[2:0] LEN5[2:0] LEN4[2:0] LEN3[2:0] LEN2[2:0] LEN1[2:0] LOS_L1 SRCASC SRCODE HW_ONLY
RSYNC
CSD Clock Synthesis / Distribution
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PM4318 OCTLIU
9
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 6
- OCTLIU Block Diagram - SBI to Clk/Data Converter, LIUs Disabled
DDATA[7:0] ADATA[7:0]
C1FPOUT
DACTIVE
REFCLK AC1FP DC1FP
SBI2CLK
SBI_EN
VCLK
RSTB
DDP
ADP
DPL
DV5
APL
AV5
HW _ONLY SRCODE SBI Extract SBI Insert EXSBI-8 INSBI-8 SRCEN H/W only Auto-config SRCCLK SRCDO SRCASC SREN SRCLK SRDI SRDO Elastic Store x8 ELST
INTB uP Interface RDB WRB CSB ALE A[10:0] D[7:0]
TRSTB CSD Clock Synthesis / Distribution TDO JTAG TDI TMS TCK
ECLK EFP
ICLK_IN IFP_IN IDATA[8:1]
ICLK_OUT IFP_OUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
EDATA[8:1]
XCLK
10
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
6
DESCRIPTION The PM4318 Octal E1/T1/J1 Line Interface Device (OCTLIU) is a monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The OCTLIU is configurable via microprocessor control or SPI-compatible serial PROM interface, allowing feature selection without changes to external wiring. Analogue circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024 MHz) in E1 mode or up to 36 dB cable loss (at 772 kHz) in T1 mode using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. The OCTLIU recovers clock and data from the line. Decoding of AMI, HDB3 and B8ZS line codes is supported. In T1 mode, the OCTLIU also detects the presence of in-band loop back codes. The OCTLIU supports detection of loss of signal, pulse density violation and line code violation alarm conditions. Line code violations are accumulated for performance monitoring purposes. Internal analogue circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Each channel of the OCTLIU can generate a low jitter transmit clock from the input clock source and also provide jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the OCTLIU for network timing applications. Serial PCM interfaces to each T1/E1 LIU allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Data may be transferred either as dual rail line pulses or single rail DS-1/E1 data. Alternatively, the OCTLIU supports an 8-bit parallel SBI interface for interfacing to high-density framers. The OCTLIU may be configured to operate in a mode in which the LIUs are disabled and the device acts as a converter between the SBI interface and serial clock and data. Up to 8 serial data streams (sharing a common clock and frame pulse) may be mapped on to the SBI bus in this mode. The OCTLIU may be configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. Alternatively, the device may be operated in a `hardware only' mode in which no microprocessor is required. In this case, the OCTLIU reads configuration information from an SPI-compatible serial PROM interface on power up. Multiple OCTLIUs can be configured from a single serial PROM via a cascade interface on the OCTLIU.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
11
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
7
PIN DIAGRAM The OCTLIU is packaged in a 288-pin Tape-SBGA package having a body size of 23mm by 23mm. Figure 7 - Pin Diagram
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
ALE/ LEN4[2]
VSS
D[1]/ LEN6[2]
D[2]/ LEN7[0]
D[4]/ LEN7[2]
VSS
VDD1V8
TAVS2[1]
TXRING2 [1] TXRING1 [1]
TXTIP1[1]
TXTIP2[1]
TXTIP2 [8]
TXTIP1 [8]
TXRING1 [8] TXRING2 [8]
RSTB
LOS
SRCCLK
SRCLK
VDD3V3
TDI
A
B
VDD3V3
VDD3V3
CSB/ LEN5[2]
D[0]/ LEN6[1]
D[3]/ LEN7[1]
D[6]/ LEN8[1]
SBI_EN
QAVS[4]
RES[5]
TAVD3[1]
TAVS3[8]
TAVD2[8]
QAVD[4]
VDD1V8
VDD3V3
RES[1]
RES[6]
SRCDO
SRDO
SRCASC
TDO
HW_ONLY
B
C
A[8]/ LEN3[2]
A[9]/ LEN4[0]
A[10]/ LEN4[1]
RDB/ LEN5[1]
VDD3V3
VDD3V3
VSS
D[7]/ LEN8[2]
CAVD
TAVD2[1]
TAVS3[1]
TAVD3[8]
TAVS2[8]
VSS
VSS
LOS_L1
SRCODE
SRCEN
SREN
VSS
TCK
SBI2CLK
C
D
A[4]/ LEN2[1]
A[5]/ LEN2[2]
A[6]/ LEN3[0]
VSS
WRB/ LEN5[0]
INTB/ LEN6[0]
VSS
D[5]/ LEN8[0]
CAVS
TAVS1[1]
TAVD1[1]
TAVD1[8]
TAVS1[8]
XCLK
RSYNC/ ICLK_OUT
VDD3V3
SRDI
VSS
NC
TMS
VDD3V3
RAVS1[8]
D
E
A[0]/ LEN1[0]
A[1]/ LEN1[1]
A[2]/ LEN1[2]
A[7]/ LEN3[1]
TRSTB
VSS
RAVD2[8]
RAVD2[7]
E
F
RAVS1[1]
RAVD2[1]
QAVD[1]
A[3]/ LEN2[0]
QAVS[3]
RES[4]
RAVS2[7]
TXRING2 [7]
F
G
RAVD1[1]
RXTIP[1]
RAVS2[1]
VDD3V3
RAVS2[8]
RXTIP[8]
RAVS1[7]
TXRING1 [7]
G
H
TXRING2 [2]
RAVD2[2]
RAVS2[2]
RXRING[1]
RXRING [8]
RAVD1[8]
RAVD1[7]
TXTIP1 [7]
H
J
TXRING1 [2]
RXTIP[2]
RAVS1[2]
RXRING [2]
RXRING [7]
RXTIP[7]
TAVS2[7]
TXTIP2 [7]
J
K
TXTIP1[2]
RAVD1[2]
TAVS2[2]
TAVS1[2]
TAVS1[7]
TAVD2[7]
TAVD3[7]
TXTIP2 [6]
K
L
TXTIP2 [2]
TAVD2[2]
TAVD3[2]
TAVD1[2]
Bottom View
TAVD1[7]
TAVS3[7]
TAVS3[6]
TXTIP1[6]
L
M
TXTIP2 [3]
TAVS3[2]
TAVS3[3]
TAVD1[3]
TAVD1[6]
TAVD3[6]
TAVD2[6]
TXRING1 [6]
M
N
TXTIP1 [3]
TAVD3[3]
TAVD2[3]
TAVS1[3]
TAVS1[6]
TAVS2[6]
RAVD1[6]
TXRING2 [6]
N
P
TXRING1 [3]
TAVS2[3]
RAVD1[3]
RXRING [3]
RXRING [6]
RAVS1[6]
RAVD2[6]
RXTIP[6]
P
R
TXRING2 [3]
RXTIP[3]
RAVD2[3]
RXTIP[4]
RXTIP[5]
RXRING [5]
RAVD1[5]
RAVS2[6]
R
T
RAVS1[3]
RAVS2[3]
RAVD1[4]
RAVS2[4]
QAVD[3]
RAVS2[5]
RAVD2[5]
RAVS1[5]
T
U
RXRING [4]
RAVS1[4]
RAVD2[4]
TCLK[1]/ IDATA[1]
TCLK[7]/ IDATA[7]
TDN[8]/ IFP_IN
TDP[8]/ ADATA[7]
VSS
U
V
RES[1]
QAVS[1]
VSS
TDP[2]/ ADATA[1] RDN[3]/ VDD3V3 TDN[4]/ ADP VDD3V3 VDD3V3 RLCV[3]/ C1FPOUT TDP[4]/ ADATA[3] RDP[2]/ DDATA[1] RCLK[3]/ EDATA[3] RDN[4]/ VDD3V3 RLCV[4]/ DDP RCLK[4]/ EDATA[4] TAVS2[4] TAVD3[4] TAVS3[5] TAVD2[5] RES[3] VSS TAVS1[4] TAVD1[4] TAVD1[5] TAVS1[5] VDD1V8
TDN[6]/ AV5
TCLK[6]/ IDATA[6]
TDN[7]/ ICLK_IN
TCLK[8]/ IDATA[8]
V
W
TDP[1]/ ADATA[0]
TDN[1]/ REFCLK
TCLK[2]/ IDATA[2]
RDP[5]/ DDATA[4] RDN[5]/ RLCV[5]/ DPL
RCLK[6]/ EDATA[6]
RCLK[7]/ EDATA[7]
RDP[8]/ DDATA[7]
NC
VDD3V3
TCLK[5]/ IDATA[5]
TDP[7]/ ADATA[6]
W
Y
TDN[2]/ AC1FP
TDP[3]/ ADATA[2]
VDD3V3
VSS
VDD3V3
VSS
RDP[7]/ DDATA[6]
RDN[8]/ RLCV[8]/ DACTIVE RDN[7]/ RLCV[7]/ ECLK VDD3V3 VSS
TDP[5]/ ADATA[4]
TDP[6]/ ADATA[5]
Y
AA
TCLK[3]/ IDATA[3]
TDN[3]/ DC1FP
TCLK[4]/ IDATA[4]
RCLK[1]/ EDATA[1]
RCLK[2]/ EDATA[2] RDN[1]/ RLCV[1]/ IFP_OUT
VSS
VSS
VDD1V8
QAVD[2]
TAVD2[4]
TAVS3[4]
TAVD3[5]
TAVS2[5]
QAVS[2]
VSS
VSS
RDP[6]/ DDATA[5] RDN[6]/ RLCV[6]/ DV5
VSS
TDN[5]/ APL
AA
AB
VSS
VSS
VSS
RDP[1]/ DDATA[0]
RDN[2]/ RLCV[2]/ EFP
RDP[3]/ DDATA[2]
RDP[4]/ DDATA[3]
TXRING2 [4] TXRING1 [4]
TXTIP1[4]
TXTIP2 [4]
TXTIP2 [5]
TXTIP1[5]
TXRING1 [5] TXRING2 [5]
RCLK[5]/ EDATA[5]
VDD3V3
VSS
RCLK[8]/ EDATA[8]
VDD3V3
AB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
12
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
8
PIN DESCRIPTION By convention, where a bus of eight pins indexed [8:1] is present, the index indicates to which octant the pin applies. With TCLK[8:1], for example, TCLK[1] applies to octant #1, TCLK[2] applies to octant #2, etc.
Pin Name
Type
Pin No.
Function
T1 and E1 System Side Serial Clock and Data Interface TCLK[1]/IDATA[1] TCLK[2]/IDATA[2] TCLK[3]/IDATA[3] TCLK[4]/IDATA[4] TCLK[5]/IDATA[5] TCLK[6]/IDATA[6] TCLK[7]/IDATA[7] TCLK[8]/IDATA[8] TDP[1]/ADATA[0] TDP[2]/ADATA[1] TDP[3]/ADATA[2] TDP[4]/ADATA[3] TDP[5]/ADATA[4] TDP[6]/ADATA[5] TDP[7]/ADATA[6] TDP[8]/ADATA[7] Input U19 W20 AA22 AA20 W2 V3 U4 V1 W22 V19 Y21 Y19 Y2 Y1 W1 U2 The Transmit Clock inputs (TCLK[8:1]) should be 1.544 MHz for DS1 or 2.048 MHz for E1 data streams and are used to sample the corresponding TDP[8:1] and TDN[8:1] signals. TCLK[8:1] share the same pins as the IDATA[8:1] inputs. TCLK[8:1] are selected when SBI2CLK is tied low.
Input
Transmit Positive Data (TDP[8:1]). When in single-rail mode, these inputs are the NRZ data signals to be transmitted. These inputs can be configured to be active high or active low. When in dual-rail mode, these inputs are the NRZ positive data signals to be transmitted. TDP[8:1] can be sampled on either the rising or falling edges of the corresponding TCLK[8:1]. TDP[8:1] share the same pins as the ADATA[7:0] inputs. TDP[8:1] are selected when SBI_EN and SBI2CLK are both tied low.
TDN[1]/REFCLK TDN[2]/AC1FP TDN[3]/DC1FP TDN[4]/ADP TDN[5]/APL TDN[6]/AV5 TDN[7]/ICLK_IN TDN[8]/IFP_IN
Input
W21 Y22 AA21 W18 AA1 V4 V2 U3
Transmit Negative Data (TDN[8:1]). When in dual-rail mode, these inputs are the NRZ negative data signals to be transmitted. These inputs can be sampled on either the rising or falling edges of the corresponding TCLK[8:1]. These input pins are ignored if the device is configured for single-rail (unipolar) transmit mode. TDN[8:1] share the same pins as the REFCLK, AC1FP, DC1FP, ADP, APL, AV5, ICLK_IN and IFP_IN inputs. TDN[8:1] are selected when SBI_EN and SBI2CLK are both tied low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
13
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name RCLK[1]/EDATA[1] RCLK[2]/EDATA[2] RCLK[3]/EDATA[3] RCLK[4]/EDATA[4] RCLK[5]/EDATA[5] RCLK[6]/EDATA[6] RCLK[7]/EDATA[7] RCLK[8]/EDATA[8] RDP[1]/DDATA[0] RDP[2]/DDATA[1] RDP[3]/DDATA[2] RDP[4]/DDATA[3] RDP[5]/DDATA[4] RDP[6]/DDATA[5] RDP[7]/DDATA[6] RDP[8]/DDATA[7]
Type Output
Pin No. AA19 AA18 Y16 AA15 AB6 W7 W6 AB2 AB19 Y17 AB16 AB15 W8 AA5 Y5 W5
Function Recovered Clock Output (RCLK[8:1]). RCLK[8:1] is the clock recovered from the RXTIP[8:1] and RXRING[8:1] input signals. RCLK[8:1] share the same pins as the EDATA[8:1] outputs. RCLK[8:1] are selected when SBI2CLK is tied low.
Output
Receive Digital Positive Data (RDP[8:1]). When in single rail mode, RDP[8:1] output NRZ sampled DS-1 or E1 data which has been decoded by AMI, B8ZS, or HDB3 line code rules. When in dual rail mode, RDP[8:1] output NRZ sampled bipolar positive pulses. RDP[8:1] can be updated on either the falling or rising RCLK[8:1] edge. RDP[8:1] share the same pins as the DDATA[7:0] outputs. RDP[8:1] are selected when SBI_EN and SBI2CLK are both tied low.
RDN/RLCV[1]/IFP_OUT RDN/RLCV[2]/EFP RDN/RLCV[3]/C1FPOUT RDN/RLCV[4]/DDP RDN/RLCV[5]/DPL RDN/RLCV[6]/DV5 RDN/RLCV[7]/ECLK RDN/RLCV[8]/DACTIVE
Output
AB18 AB17 W15 Y14 Y8 AB5 AA4 Y4
Receive Digital Negative Data/Line Code Violation Indication (RDN/RLCV[8:1]). When in dual rail mode, RDN/RLCV[8:1] output NRZ sampled bipolar negative pulses. When in single rail mode, RDN/RLCV[8:1] output a NRZ pulse whenever a line code violation or excess zeros condition is detected. RDN/RLCV[8:1] can be updated on either the falling or rising RCLK[8:1] edge. RDN/RLCV[8:1] share the same pins as the IFP_OUT, EFP, C1FPOUT, DDP, DPL, DV5, ECLK and DACTIVE outputs. RDN/RLCV[8:1] are selected when SBI_EN and SBI2CLK are both tied low.
SBI System Side Interface REFCLK/TDN[1] Input W21 The SBI reference clock signal (REFCLK) provides reference timing for the SBI ADD and DROP busses. REFCLK is nominally a 50% duty cycle clock of frequency 19.44 MHz 50ppm. REFCLK shares the same pin as the TDN[1] input. REFCLK is selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
14
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name AC1FP/TDN[2]
Type Input
Pin No. Y22
Function The SBI ADD bus C1 octet frame pulse signal (AC1FP) provides frame synchronisation for devices connected via an SBI interface. AC1FP must be asserted for 1 REFCLK cycle every 500 s or multiples thereof (i.e. every 9720 n REFCLK cycles, where n is a positive integer). All devices connected to the SBI ADD bus must be synchronised to a AC1FP signal from a single source. AC1FP is sampled on the rising edge of REFCLK. AC1FP shares the same pin as the TDN[2] input. AC1FP is selected when SBI_EN or SBI2CLK is tied high.
DC1FP/TDN[3]
Input
AA21
The SBI DROP bus C1 octet frame pulse signal (DC1FP) provides frame synchronisation for devices connected via an SBI interface. DC1FP must be asserted for 1 REFCLK cycle every 500 s or multiples thereof (i.e. every 9720 n REFCLK cycles, where n is a positive integer). All devices connected to the SBI DROP bus must be synchronised to a DC1FP signal from a single source. DC1FP is sampled on the rising edge of REFCLK. DC1FP shares the same pin as the TDN[3] input. DC1FP is selected when SBI_EN or SBI2CLK is tied high.
C1FPOUT/RDN/RLCV[3]
Output
W15
The C1 octet frame pulse output signal (C1FPOUT) may be used to provide frame synchronisation for devices interconnected via an SBI interface. C1FPOUT is asserted for 1 REFCLK cycle every 500 s (i.e. every 9720 REFCLK cycles). If C1FPOUT is used for synchronisation, it must be connected to the A/DC1FP inputs of all the devices connected to the SBI ADD or DROP bus. C1FPOUT is updated on the rising edge of REFCLK. C1FPOUT shares the same pin as the RDN/RLCV[3] output. C1FPOUT is selected when SBI_EN or SBI2CLK is tied high.
ADATA[0]/TDP[1] ADATA[1]/TDP[2] ADATA[2]/TDP[3] ADATA[3]/TDP[4] ADATA[4]/TDP[5] ADATA[5]/TDP[6] ADATA[6]/TDP[7] ADATA[7]/TDP[8]
Input
W22 V19 Y21 Y19 Y2 Y1 W1 U2
The SBI ADD bus data signals (ADATA[7:0]) contain time division multiplexed transmit data from up to 84 independently timed links. Link data is transported as T1 or E1 tributaries within the SBI TDM bus structure. The OCTLIU may be configured to extract data from up to 8 tributaries within the structure. ADATA[7:0] are sampled on the rising edge of REFCLK. ADATA[7:0] share the same pins as the TDP[8:1] inputs. ADATA[7:0] are selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
15
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name ADP/TDN[4]
Type Input
Pin No. W18
Function The SBI ADD bus parity signal (ADP) carries the even or odd parity for the ADD bus signals. The parity calculation encompasses the ADATA[7:0], APL and AV5 signals. Multiple devices can drive the SBI ADD bus at uniquely assigned tributary column positions. This parity signal is intended to detect accidental driver clashes in the column assignment. ADP is sampled on the rising edge of REFCLK. ADP shares the same pin as the TDN[4] input. ADP is selected when SBI_EN or SBI2CLK is tied high.
APL/TDN[5]
Input
AA1
The SBI ADD bus payload signal (APL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be deasserted during the octet following the V3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDM bus structure. APL is sampled on the rising edge of REFCLK. APL shares the same pin as the TDN[5] input. APL is selected when SBI_EN or SBI2CLK is tied high.
AV5/TDN[6]
Input
V4
The SBI ADD bus payload indicator signal (AV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. All movements indicated by this signal must be accompanied by appropriate adjustments in the APL signal. AV5 is sampled on the rising edge of REFCLK. AV5 shares the same pin as the TDN[6] input. AV5 is selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
16
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name DDATA[0]/RDP[1] DDATA[1]/RDP[2] DDATA[2]/RDP[3] DDATA[3]/RDP[4] DDATA[4]/RDP[5] DDATA[5]/RDP[6] DDATA[6]/RDP[7] DDATA[7]/RDP[8]
Type Tristate Output
Pin No. AB19 Y17 AB16 AB15 W8 AA5 Y5 W5
Function The SBI DROP bus data signals (DDATA[7:0]) contain time division multiplexed receive data from up to 84 independently timed links. Link data is transported as T1 or E1 tributaries within the SBI TDM bus structure. The OCTLIU may be configured to insert data into up to 8 tributaries within the structure. Multiple LIU devices can drive the SBI DROP bus at uniquely assigned tributary column positions. DDATA[7:0] are tristated when the OCTLIU is not outputting data on a particular tributary column. DDATA[7:0] are updated on the rising edge of REFCLK. DDATA[7:0] share the same pins as the RDP[8:1] outputs. DDATA[7:0] are selected when SBI_EN or SBI2CLK is tied high.
DDP/RDN/RLCV[4]
Tristate Output
Y14
The SBI DROP bus parity signal (DDP) carries the even or odd parity for the DROP bus signals. The parity calculation encompasses the DDATA[7:0], DPL and DV5 signals. Multiple LIU devices can drive this signal at uniquely assigned tributary column positions. DDP is tristated when the OCTLIU is not outputting data on a particular tributary column. This parity signal is intended to detect accidental source clashes in the column assignment. DDP is updated on the rising edge of REFCLK. DDP shares the same pin as the RDN/RLCV[4] output. DDP is selected when SBI_EN or SBI2CLK is tied high.
DPL/RDN/RLCV[5]
Tristate Output
Y8
The SBI DROP bus payload signal (DPL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be deasserted during the octet following the V3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDM bus structure. Multiple LIU devices can drive this signal at uniquely assigned tributary column positions. DPL is tristated when the OCTLIU is not outputting data on a particular tributary column. DPL is updated on the rising edge of REFCLK. DPL shares the same pin as the RDN/RLCV[5] output. DPL is selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name DV5/RDN/RLCV[6]
Type Tristate output
Pin No. AB5
Function The SBI DROP bus payload indicator signal (DV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. Multiple LIU devices can drive this signal at uniquely assigned tributary column positions. DV5 is tristated when the OCTLIU is not outputting data on a particular tributary column. DV5 is updated on the rising edge of REFCLK. DV5 shares the same pin as the RDN/RLCV[6] output. DV5 is selected when SBI_EN or SBI2CLK is tied high.
DACTIVE/RDN/RLCV[8]
Output
Y4
The SBI DROP bus active indicator signal (DACTIVE) is asserted whenever the OCTLIU is driving the SBI DROP bus signals, DDATA[7:0], DDP, DPL and DV5. DACTIVE is updated on the rising edge of REFCLK. DACTIVE shares the same pin as the RDN/RLCV[8] output. DACTIVE is selected when SBI_EN or SBI2CLK is tied high.
Transmit Line Interface TXTIP1[1] TXTIP1[2] TXTIP1[3] TXTIP1[4] TXTIP1[5] TXTIP1[6] TXTIP1[7] TXTIP1[8] TXTIP2[1] TXTIP2[2] TXTIP2[3] TXTIP2[4] TXTIP2[5] TXTIP2[6] TXTIP2[7] TXTIP2[8] Analogue A12 Output K22 N22 AB12 AB9 L1 H1 A9 A11 L22 M22 AB11 AB10 K1 J1 A10 Transmit Analogue Positive Pulse (TXTIP1[8:1] and TXTIP2[8:1]). When the transmit analogue line interface is enabled, the TXTIP1[x] and TXTIP2[x] analogue outputs drive the transmit line pulse signal through an external matching transformer. Both TXTIP1[x] and TXTIP2[x] are normally connected to the positive lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board. After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The HIGHZ bit of the octant's XLPG Line Driver Configuration register must be programmed to logic 0 to remove the high impedance state.
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18
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name TXRING1[1] TXRING1[2] TXRING1[3] TXRING1[4] TXRING1[5] TXRING1[6] TXRING1[7] TXRING1[8] TXRING2[1] TXRING2[2] TXRING2[3] TXRING2[4] TXRING2[5] TXRING2[6] TXRING2[7] TXRING2[8] Receive Line Interface RXTIP[1] RXTIP[2] RXTIP[3] RXTIP[4] RXTIP[5] RXTIP[6] RXTIP[7] RXTIP[8] RXRING[1] RXRING[2] RXRING[3] RXRING[4] RXRING[5] RXRING[6] RXRING[7] RXRING[8]
Type
Pin No.
Function Transmit Analogue Negative Pulse (TXRING1[8:1] and TXRING2[8:1]). When the transmit analogue line interface is enabled, the TXRING1[x] and TXRING2[x] analogue outputs drive the transmit line pulse signal through an external matching transformer. Both TXRING1[x] and TXRING2[x] are normally connected to the negative lead of the transformer primary. Two outputs are provided for better signal integrity and must be shorted together on the board. After a reset, TXRING1[x] and TXRING2[x] are high impedance. The HIGHZ bit of the octant's XLPG Line Driver Configuration register must be programmed to logic 0 to remove the high impedance state.
Analogue A13 Output J22 P22 AB13 AB8 M1 G1 A8 A14 H22 R22 AB14 AB7 N1 F1 A7
Analogue G21 Input J21 R21 R19 R4 P1 J3 G3 Analogue H19 Input J19 P19 U22 R3 P4 J4 H4
Receive Analogue Positive Pulse (RXTIP[8:1]). When the analogue receive line interface is enabled, RXTIP[x] samples the received line pulse signal from an external isolation transformer. RXTIP[x] is normally connected directly to the positive lead of the receive transformer secondary.
Receive Analogue Negative Pulse (RXRING[8:1]). When the analogue receive line interface is enabled, RXRING[x] samples the received line pulse signal from an external isolation transformer. RXRING[x] is normally connected directly to the negative lead of the receive transformer secondary.
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19
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin No.
Function
SBI to Clk/Data Converter Interface SBI_EN SBI2CLK Input B16 C1 The SBI interface enable signals (SBI_EN, SBI2CLK) select between the SBI and serial clock/data system side interfaces and allow selection of an operating mode in which the LIUs are disabled and the OCTLIU functions as a converter between the SBI interface and serial clk/data. The signals select the device operating mode as follows: SBI_EN 0 1 0 1 IDATA[1]/TCLK[1] IDATA[2]/TCLK[2] IDATA[3]/TCLK[3] IDATA[4]/TCLK[4] IDATA[5]/TCLK[5] IDATA[6]/TCLK[6] IDATA[7]/TCLK[7] IDATA[8]/TCLK[8] ICLK_IN/TDN[7] Input U19 W20 AA22 AA20 W2 V3 U4 V1 V2 0 0 1 1 SBI2CLK Mode LIUs enabled, clk/data selected on system side. LIUs enabled, SBI interface selected on system side. LIUs disabled, converter mode. Unused
The Ingress Data inputs (IDATA[8:1]) carry eight serial 1.544 Mbps or 2.048 Mbps data streams to be mapped on to the SBI interface when the device is operating as a SBI to clk/data converter. The eight serial data streams are sampled on the rising edge of ICLK_IN. IDATA[8:1] share the same pins as the TCLK[8:1] inputs. IDATA[8:1] are selected when SBI2CLK is tied high. The Ingress Input Clock (ICLK_IN) should be 1.544 MHz for DS1 or 2.048 MHz for E1 data streams and is used to sample the IDATA[8:1] and IFP_IN signals. ICLK_IN shares the same pin as the TDN[7] input. ICLK_IN is selected when SBI_EN or SBI2CLK is tied high.
Input
IFP_IN/TDN[8]
Input
U3
The Ingress Frame Pulse input (IFP_IN) should be set high during the framing bits of DS1 streams or during the first bit of the framing octet of E1 data streams. IFP_IN is sampled on the rising edge of ICLK_IN. IFP_IN shares the same pin as the TDN[8] input. IFP_IN is selected when SBI_EN or SBI2CLK is tied high.
ICLK_OUT/RSYNC
Output
D8
The Ingress Output Clock (ICLK_OUT) is a nominal 1.544 MHz (for DS1) or 2.048 MHz (for E1) clock and may be used as a source for the ICLK_IN clock if desired. ICLK_OUT shares the same pin as the RSYNC output. ICLK_OUT is selected when SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type Output
Pin No. AB18
Function The Ingress Frame Pulse output (IFP_OUT) is pulsed high every 193 ICLK_OUT cycles for DS1 and every 256 ICLK_OUT cycles for E1. It may be used as a framing reference and as a source for IFP_IN if desired. IFP_OUT is updated on the falling edge of ICLK_OUT. IFP_OUT shares the same pin as the RDN/RLCV[1] output. IFP_OUT is selected when SBI_EN or SBI2CLK is tied high.
IFP_OUT/RDN/RLCV[1]
EDATA[1]/RCLK[1] EDATA[2]/RCLK[2] EDATA[3]/RCLK[3] EDATA[4]/RCLK[4] EDATA[5]/RCLK[5] EDATA[6]/RCLK[6] EDATA[7]/RCLK[7] EDATA[8]/RCLK[8] ECLK/RDN/RLCV[7]
Output
AA19 AA18 Y16 AA15 AB6 W7 W6 AB2 AA4
The Egress Data outputs (EDATA[8:1]) carry eight serial 1.544 Mbps or 2.048 Mbps data streams de-mapped from the SBI interface when the device is operating as a SBI to clk/data converter. The eight serial data streams are updated on the falling edge of ECLK. EDATA[8:1] share the same pins as the RCLK[8:1] outputs. EDATA[8:1] are selected when SBI2CLK is tied high. The Egress Clock output (ECLK) is a 1.544 MHz (for DS1) or 2.048 MHz (for E1) clock, recovered from one of the SBI tributaries. The SBI tributary used to recover timing is selectable. ECLK shares the same pin as the RDN/RLCV[7] output. ECLK is selected when SBI_EN or SBI2CLK is tied high.
Output
EFP/RDN/RLCV[2]
Output
AB17
The Egress Frame Pulse output (EFP) is set high during the framing bits of DS1 streams or during the first bit of the framing octet of E1 data streams. EFP is updated on the falling edge of ECLK. EFP shares the same pin as the RDN/RLCV[2] output. EFP is selected when SBI_EN or SBI2CLK is tied high.
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21
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name Timing Options Control XCLK
Type
Pin No.
Function
Input
D9
Crystal Clock Input (XCLK). This signal provides a stable, global timing reference for the OCTLIU internal circuitry via an internal clock synthesizer. XCLK is a nominally jitter free clock at 1.544 MHz in T1 mode and 2.048 MHz in E1 mode. In T1 mode, a 2.048 MHz clock may be used as a reference. When used in this way, however, the intrinsic jitter specifications in AT&T TR62411 may not be met.
RSYNC/ICLK_OUT
Output
D8
Recovered Clock Synchronization Signal (RSYNC). This output signal is the recovered, jitter attenuated, receiver line rate clock (1.544 or 2.048 MHz) of one of the eight T1 or E1 channels or, optionally, the recovered, jitter attenuated clock synchronously divided by 193 (T1 mode) or 256 (E1 mode) to create a 8 kHz timing reference signal. The default is to source RSYNC from octant #1. When the OCTLIU is in a loss of signal state, RSYNC is derived from the XCLK input or, optionally, is held high. RSYNC shares the same pin as the ICLK_OUT output. RSYNC is selected when SBI2CLK is tied low.
Alarm Interface LOS Output A5 Loss of Signal Alarm (LOS). This signal outputs the LOS status of the 8 LIU octants in a serial format which repeats every 8 XCLK cycles. The presence of the LOS status for LIU #1 on this output is indicated by the LOS_L1 output pulsing high. On the following XCLK cycle, the LOS status for LIU #2 is output, then LIU #3, and so on. This signal is intended for use in Hardware Only mode. When the microprocessor interface is enabled, the status of the LOS alarm can also be determined by reading the LOSV bit in the CDRC Interrupt Status register. LOS is updated on the falling edge of XCLK. LOS_L1 Output C7 Loss of Signal LIU #1 indicator (LOS_L1). This signal is pulsed high for one XCLK cycle every 8 XCLK cycles and indicates that the LOS status for LIU #1 is being output on LOS. LOS_L1 is updated on the falling edge of XCLK.
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22
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name Misc. Control Signals RSTB
Type
Pin No.
Function
Input
A6
Active Low Reset (RSTB). This signal provides an asynchronous OCTLIU reset. RSTB is a Schmidt triggered input with an internal pull up resistor. This pin must be tied low for normal operation. These pins must be connected to an analogue ground for normal operation.
RES[1] RES[2] RES[3] RES[4] RES[5] RES[6]
Input
B7
Analogue V22 I/O Y9 F3 B14 Input B6
This pin must be tied to ground for normal operation.
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23
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin No.
Function
Microprocessor Interface A[0]/LEN1[0] A[1]/LEN1[1] A[2]/LEN1[2] A[3]/LEN2[0] A[4]/LEN2[1] A[5]/LEN2[2] A[6]/LEN3[0] A[7]/LEN3[1] A[8]/LEN3[2] A[9]/LEN4[0] A[10]/LEN4[1] ALE/LEN4[2] Input E22 E21 E20 F19 D22 D21 D20 E19 C22 C21 C20 A22 Address Bus (A[10:0]). This bus selects specific registers during OCTLIU register accesses. Signal A[10] selects between normal mode and test mode register access. A[10] has an internal pull down resistor. A[10:0] share the same pins as some of the LENx[2:0] inputs. A[10:0] are selected when HW_ONLY is tied low.
Input
Address Latch Enable (ALE). This signal is active high and latches the address bus contents, A[10:0], when low. When ALE is high, the internal address latches are transparent. ALE allows the OCTLIU to interface to a multiplexed address/data bus. The ALE input has an internal pull up resistor. ALE shares the same pin as the LEN4[2] input. ALE is selected when HW_ONLY is tied low.
WRB/LEN5[0]
Input
D18
Active Low Write Strobe (WRB). This signal is low during a OCTLIU register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. WRB shares the same pin as the LEN5[0] input. WRB is selected when HW_ONLY is tied low.
RDB/LEN5[1]
Input
C19
Active Low Read Enable (RDB). This signal is low during OCTLIU register read accesses. The OCTLIU drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. RDB shares the same pin as the LEN5[1] input. RDB is selected when HW_ONLY is tied low.
CSB/LEN5[2]
Input
B20
Active Low Chip Select (CSB). CSB must be low to enable OCTLIU register accesses. CSB must go high at least once after power up to clear internal test modes. If CSB is not used, it should be tied to an inverted version of RSTB, in which case, RDB and WRB determine register accesses. CSB shares the same pin as the LEN5[2] input. CSB is selected when HW_ONLY is tied low.
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24
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name INTB/LEN6[0]
Type Opendrain Output
Pin No. D17
Function Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, INTB will tristate. INTB shares the same pin as the LEN6[0] input. INTB is selected when HW_ONLY is tied low.
D[0]/LEN6[1] D[1]/LEN6[2] D[2]/LEN7[0] D[3]/LEN7[1] D[4]/LEN7[2] D[5]/LEN8[0] D[6]/LEN8[1] D[7]/LEN8[2]
I/O
B19 A20 A19 B18 A18 D15 B17 C15
Bidirectional Data Bus (D[7:0]). This bus provides OCTLIU register read and write accesses. D[7:0] share the same pins as some of the LENx[2:0] inputs. D[7:0] are selected when HW_ONLY is tied low.
Hardware-Only Control Interface HW_ONLY Input B1 The Hardware Only mode enable signal (HW_ONLY) selects between the microprocessor-controlled and hardware-only modes of operation. When HW_ONLY is tied low, the microprocessor interface is enabled. When HW_ONLY is tied high, the hardwareonly control interface is enabled and the microprocessor interface is unused. Serial PROM Cascade Control (SRCASC). When SRCASC is tied low, the OCTLIU acts as the Serial PROM master controller and the SREN, SRCLK, SRDI and SRDO pins should be connected to the serial PROM. When SRCASC is tied high, the OCTLIU acts as a Serial PROM cascade slave and the SREN, SRCLK and SRDO pins should be connected to the SRCEN, SRCCLK and SRCDO pins of another OCTLIU device upstream in the cascade. Serial PROM Enable (SREN). When operating as a Serial PROM master (SRCASC tied low), the SREN pin functions as an output and generates an active low chip select signal for the serial PROM. When operating as a Serial PROM slave (SRCASC tied high), the SREN pin functions as an input and indicates the validity of cascade data on the SRDO input. When configured as an output, SREN is updated on the falling edge of SRCLK. When configured as an input, SREN is sampled on the rising edge of SRCLK.
SRCASC
Input
B3
SREN
I/O
C4
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name SRCLK
Type I/O
Pin No. A3
Function Serial PROM Clock (SRCLK). When operating as a Serial PROM master (SRCASC tied low), the SRCLK pin functions as an output and generates a clock for the serial PROM. When operating as a Serial PROM slave (SRCASC tied high), the SRCLK pin functions as an input and is connected to the SRCCLK output of an OCTLIU device upstream in the serial PROM cascade. Serial PROM Data In (SRDI). When operating as a Serial PROM master (SRCASC tied low), the SRDI output is used to send read commands to the serial PROM. When operating as a Serial PROM slave (SRCASC tied high), SRDI is unused. SRDI is updated on the falling edge of SRCLK.
SRDI
Output
D6
SRDO
Input
B4
Serial PROM Data Out (SRDO). When operating as a Serial PROM master (SRCASC tied low), the SRDO input receives data from the serial PROM. When operating as a Serial PROM slave (SRCASC tied high), the SRDO input receives data from the SRCDO output of an OCTLIU device upstream in the serial PROM cascade. SRDO is sampled on the rising edge of SRCLK.
SRCEN
Output
C5
Serial PROM Cascade Enable (SRCEN). The SRCEN output is asserted when valid data is being output on SRCDO. SRCEN is updated on the falling edge of SRCCLK.
SRCCLK
Output
A4
Serial PROM Cascade Clock (SRCCLK). When operating as a Serial PROM master (SRCASC tied low), the SRCCLK output is a copy of the SRCLK output. When operating as a Serial PROM slave (SRCASC tied high), the SRCCLK output is a copy of the SRCLK input. Serial PROM Cascade Data Out (SRCDO). The SRCDO output is a buffered, retimed copy of the SRDO input. SRCDO is updated on the falling edge of SRCCLK.
SRCDO
Output
B5
SRCODE
Input
C6
Serial PROM Code (SRCODE). The SRCODE input provides a means for controlling the execution of configuration instructions stored in the serial PROM. Instructions can be coded to execute only if SRCODE is logic 0, only if SRCODE is logic 1 or unconditionally. The SRCODE input thus allows the selection of two different configuration sequences within a single PROM load. This could be used, for example, to store two configurations for T1 and E1 operation within one serial PROM.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name LEN1[0]/A[0] LEN1[1]/A[1] LEN1[2]/A[2] LEN2[0]/A[3] LEN2[1]/A[4] LEN2[2]/A[5] LEN3[0]/A[6] LEN3[1]/A[7] LEN3[2]/A[8] LEN4[0]/A[9] LEN4[1]/A[10] LEN4[2]/ALE LEN5[0]/WRB LEN5[1]/RDB LEN5[2]/CSB LEN6[0]/INTB LEN6[1]/D[0] LEN6[2]/D[1] LEN7[0]/D[2] LEN7[1]/D[3] LEN7[2]/D[4] LEN8[0]/D[5] LEN8[1]/D[6] LEN8[2]/D[7]
Type Input
Pin No. E22 E21 E20 F19 D22 D21 D20 E19 C22 C21 C20 A22 D18 C19 B20 D17 B19 A20 A19 B18 A18 D15 B17 C15
Function Line Length Build-out Select (LENn[2:0]). These signals can be preset to select one of eight different pulse templates to be used by the line transmitters, depending on line length, etc. LENn[2:0] selects the pulse template for the line transmitter of octant #n. LENn[2:0] share the same pins as the microprocessor interface signals. LENn[2:0] are selected when HW_ONLY is tied high. The LENn[2:0] inputs are latched following reset of the OCTLIU and any changes to their value will have no effect on the operation of OCTLIU until a subsequent reset.
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27
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name JTAG Interface TDO
Type
Pin No.
Function
Tristate Output
B2
Test Data Output (TDO). This signal carries test data out of the OCTLIU via the IEEE 1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output that is tristated except when scanning of data is in progress. Test Data Input (TDI). This signal carries test data into the OCTLIU via the IEEE 1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an internal pull up resistor. Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE 1149.1 test access port. Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE 1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an internal pull up resistor. Active low Test Reset (TRSTB). This signal provides an asynchronous OCTLIU test access port reset via the IEEE 1149.1 test access port. TRSTB is a Schmidt triggered input with an internal pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB should be connected to the RSTB input.
TDI
Input
A1
TCK TMS
Input Input
C2 D3
TRSTB
Input
E4
Analogue Power and Ground Pins TAVD1[1] TAVD1[2] TAVD1[3] TAVD1[4] TAVD1[5] TAVD1[6] TAVD1[7] TAVD1[8] Analogue D12 Power L19 M19 W12 W11 M4 L4 D11 Transmit Analogue Power (TAVD1[8:1]). TAVD1[8:1] provide power for the transmit LIU analogue circuitry. TAVD1[8:1] should be connected to analogue +3.3 V.
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28
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name TAVD2[1] TAVD2[2] TAVD2[3] TAVD2[4] TAVD2[5] TAVD2[6] TAVD2[7] TAVD2[8] TAVD3[1] TAVD3[2] TAVD3[3] TAVD3[4] TAVD3[5] TAVD3[6] TAVD3[7] TAVD3[8] CAVD
Type
Pin No.
Function Transmit Analogue Power (TAVD2[8:1], TAVD3[8:1]). TAVD2[8:1] and TAVD3[8:1] supply power for the transmit LIU current DACs. They should be connected to analogue +3.3 V.
Analogue C13 Power L21 N20 AA12 Y10 M2 K3 B11 B13 L20 N21 Y12 AA10 M3 K2 C11 Analogue C14 Power Analogue D13 Ground K19 N19 W13 W10 N4 K4 D10
Clock Synthesis Unit Analogue Power (CAVD). CAVD supplies power for the transmit clock synthesis unit. CAVD should be connected to analogue +3.3 V. Transmit Analogue Ground (TAVS1[8:1]). TAVS1[8:1] provide ground for the transmit LIU analogue circuitry. TAVS1[8:1] should be connected to analogue GND.
TAVS1[1] TAVS1[2] TAVS1[3] TAVS1[4] TAVS1[5] TAVS1[6] TAVS1[7] TAVS1[8]
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name TAVS2[1] TAVS2[2] TAVS2[3] TAVS2[4] TAVS2[5] TAVS2[6] TAVS2[7] TAVS2[8] TAVS3[1] TAVS3[2] TAVS3[3] TAVS3[4] TAVS3[5] TAVS3[6] TAVS3[7] TAVS3[8] CAVS
Type
Pin No.
Function Transmit Analogue Ground (TAVS2[8:1], TAVS3[8:1]). TAVS2[8:1] and TAVS3[8:1] supply ground for the transmit LIU current DACs. They should be connected to analogue GND.
Analogue A15 Ground K20 P21 Y13 AA9 N3 J2 C10 C12 M21 M20 AA11 Y11 L2 L3 B12 Analogue D14 Ground Analogue G22 Power K21 P20 T20 R2 N2 H2 H3 Analogue F21 Power H21 R20 U20 T2 P2 E1 E2
Clock Synthesis Unit Analogue Ground (CAVS). CAVS supplies ground for the transmit clock synthesis unit. CAVS should be connected to analogue GND. Receive Analogue Power (RAVD1[8:1]). RAVD1[8:1] supplies power for the receive LIU input equalizer. RAVD1[8:1] should be connected to analogue +3.3 V.
RAVD1[1] RAVD1[2] RAVD1[3] RAVD1[4] RAVD1[5] RAVD1[6] RAVD1[7] RAVD1[8] RAVD2[1] RAVD2[2] RAVD2[3] RAVD2[4] RAVD2[5] RAVD2[6] RAVD2[7] RAVD2[8]
Receive Analogue Power (RAVD2[8:1]). RAVD2[8:1] supplies power for the receive LIU peak detect and slicer. RAVD2[8:1] should be connected to analogue +3.3 V.
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30
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name RAVS1[1] RAVS1[2] RAVS1[3] RAVS1[4] RAVS1[5] RAVS1[6] RAVS1[7] RAVS1[8] RAVS2[1] RAVS2[2] RAVS2[3] RAVS2[4] RAVS2[5] RAVS2[6] RAVS2[7] RAVS2[8] QAVD[1] QAVD[2] QAVD[3] QAVD[4] QAVS[1] QAVS[2] QAVS[3] QAVS[4]
Type
Pin No.
Function Receive Analogue Ground (RAVS1[8:1]). RAVS1[8:1] supplies ground for the receive LIU input equalizer. RAVS1[8:1] should be connected to analogue GND.
Analogue F22 Ground J20 T22 U21 T1 P3 G2 D1 Analogue G20 Ground H20 T21 T19 T3 R1 F2 G4 Analogue F20 Power AA13 T4 B10 Analogue V21 Ground AA8 F4 B15
Receive Analogue Ground (RAVS2[8:1]). RAVS2[8:1] supplies ground for the receive LIU peak detect and slicer. RAVS2[8:1] should be connected to analogue GND.
Quiet Analogue Power (QAVD[4:1]). QAVD[4:1] supplies power for the core analogue circuitry. QAVD[4:1] should be connected to analogue +3.3 V. Quiet Analogue Ground (QAVS[4:1]). QAVS[4:1] supplies ground for the core analogue circuitry. QAVS[4:1] should be connected to analogue GND.
Digital Power and Ground Pins VDD1V8[1] VDD1V8[2] VDD1V8[3] VDD1V8[4] Power A16 B9 W9 AA14 Core Power (VDD1V8[4:1]). The VDD1V8[4:1] pins should be connected to a well decoupled +1.8V DC power supply.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14] VDD3V3[15] VDD3V3[16] VDD3V3[17] VDD3V3[18] VDD3V3[19]
Type Power
Pin No. A2 B8 B21 B22 C17 C18 D2 D7 G19 W3 W16 W17 W19 Y7 Y15 Y20 AA3 AB1 AB4
Function I/O Power (VDD3V3[19:1]). The VDD3V3[19:1] pins should be connected to a well decoupled +3.3V DC power supply.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] NC1 NC2
Type Ground
Pin No. A17 A21 C3 C8 C9 C16 D5 D16 D19 E3 U1 V20 W14 Y3 Y6 Y18 AA2 AA6 AA7 AA16 AA17 AB3 AB20 AB21 AB22 D4 W4
Function Ground (VSS [25:1]). The VSS[25:1] pins should be connected to Ground.
Open
These pins must be left unconnected.
NOTES ON PIN DESCRIPTIONS: 1. All OCTLIU inputs and bi-directionals present minimum capacitive loading. 2. All OCTLIU inputs and bi-directionals, when configured as inputs, tolerate TTL logic levels. 3. All OCTLIU outputs and bi-directionals have at least 8 mA drive capability, except the LOS, LOS_L1, TDO and serial PROM interface outputs, which have at least 6 mA drive capability. The transmit analogue outputs (TXTIP and TXRING) have built-in short circuit current limiting. 4. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 5. Inputs A[10], RES[1], and RES[6] have internal pull-down resistors. 6. All unused inputs should be connected to GROUND.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
7. The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, and VDD3V3) will be collectively referred to as VDDall33 in this document. 8. Power to VDDall33 should be applied before power to the VDD1V8 pins is applied. Similarly, power to the VDD1V8 pins should be removed before power to VDDall33 is removed. 9. The VDDall33 voltage level should not be allowed to drop below the VDD1V8 voltage level except when VDD1V8 is not powered.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9 9.1
FUNCTIONAL DESCRIPTION Octants The OCTLIU's eight E1/T1 line interface units operate independently and can be configured to operate uniquely. The octants do share a common XCLK clock input and internal clock synthesizer; hence only a single CSU Configuration register is present. Additionally, all octants share a common E1/T1B mode register bit to select between T1 and E1 operation.
9.2
Receive Interface The analogue receive interface is configurable to operate in both E1 and T1 short-haul and longhaul applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Shorthaul E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB. For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI) signals are received as the differential voltage between the RXTIP and RXRING inputs. The OCTLIU typically accepts unequalized signals that are attenuated for both T1 and E1 signals and are non-linearly distorted by typical cables. For short-haul, the slicing threshold is set to a fraction of the input signal's peak amplitude, and adapts to changes in this amplitude. The slicing threshold is programmable, but is typically 67% and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected when the input level is below a programmable threshold, which is typically 140 mV for E1 and 105 mV for T1. Figure 8 - External Analogue Interface Circuits
VDD
D1 L1 F1 TTip TXTIP R1 TXRING inB inA 1:n outB center tap outA L2 Z5 Z2 F2 TRing gnd ATB gnd VDD Phantom Feed Circuit or Vsupply as required F3 RTip RXTIP R2 RXRING inB inA 1:n outB center tap outA Z6 Z4 F4 RRing One of Eight T1 or E1 LIUs gnd Z3 chassis gnd Z1 chassis gnd
T1
T2
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 8 gives the recommended external protection circuitry for designs required to meet the major surge immunity and electrical safety standards including FCC Part 68, UL1950, and Bellcore TR-NWT-001089. This circuit has not been tested as of December, 1999. Please refer to an upcoming PMC application note for more details. For systems not requiring phantom feed or inter-building line protection, the Bi-directional Transient Surge Suppressors (Z1-Z4), their associated ground connection and the center tap of the transformer can be removed from the circuit. See Table 1 for the descriptions of components for Figure 8. Note that the crowbar devices (Z1 - Z4) are not required if the transformer's isolation rating is not exceeded. Table 1 - External Component Descriptions Description 36.0 1%, 0.25W Resistor 27.0 1%, 0.25W Resistor Surge Protector Diode Array 1:1.58 CT Transformers (E1 75 cable) 1:2 CT Transformers (otherwise) Bi-directional Transient Surge Suppressors Bi-directional Transient Surge Suppressors Dual Choke, 27H Telecom/Time Lag Fuses P1800SC P0720SC PE-68624 F1250T SRDA3.3-4 Semtech Pulse Teccor Teccor Pulse Teccor Part # Source
Component R1 R2 D1 T1 & T2 Z1 - Z4 Z5 - Z6 L1 & L2 F1 - F4
When operating in E1 mode with 75 cable, a 1:1.58 turns ratio transformer is specified in the above table. It is in fact also possible to use a 1:2 turns ratio transformer, in which case the value of R1 must be changed to 22.0 1% and the value of R2 must be changed to 18.0 1%. 9.3 Clock and Data Recovery (CDRC) The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC) block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line code violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals. In T1 mode, the input jitter tolerance of the OCTLIU complies with the Bellcore Document TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 9. The tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. The first algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm. Figure 9 - T1 Jitter Tolerance
10
Acceptable Range Sine W ave Jitter Am plitude P. to P. (UI) Log Scale 1.0
0.3 0.2
Bellcore Spec. AT&T Spec.
0.1 0.1 0.30 0.31 1.0 10 100
Sine W ave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy." Figure 10 illustrates this specification and the performance of the phase-locked loop when the ALGSEL register bit is logic 0.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 10 - Compliance with ITU-T Specification G.823 for E1 Input Jitter
10
SINEWAVE JITTER AMPLITUDE P. TO P. (UI) LOG SCALE
DPLL TOLERANCE WITH AMI ENCODED 15 2 -1 PRBS
IN SPEC REGION
DPLL TOLERANCE WITH HDB3 ENCODED 2 15-1 PRBS
1.5 1
REC. G823 JITTER TOLERANCE SPECIFICATION
0.2 0.1 10
3
2.4
10
4
1.8 10
5
SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE
9.4
Receive Jitter Attenuator (RJAT) The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the RXTIP/RXRING inputs. The attenuation is only performed when the RJATBYP register bit is a logic 0. The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit Jitter Attenuator (TJAT).
9.5
T1 Inband Loopback Code Detector (IBCD) The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in the receive data stream. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9.6
T1 Pulse Density Violation Detector (PDVD) The Pulse Density Violation Detection function is provided by the PDVD block. The block detects pulse density violations of the requirement that there be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication.
9.7
Performance Monitor Counters (PMON) The Performance Monitor block accumulates line code violation events with a saturating counter over consecutive intervals as defined by the period between writes to trigger registers (typically 1 second). When the trigger is applied, the PMON transfers the counter value into holding registers and resets the counter to begin accumulating events for the interval. The counter is reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive triggers, an overrun register bit is asserted. Triggering a counter transfer within an octant is performed by writing to any counter register location within the octant or by writing to the "Line Interface Interrupt Source #1 / PMON Update" register.
9.8
Pseudo Random Binary Sequence Generation and Detection (PRBS) The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software selectable 11 15 20 PRBS generator and checker for 2 -1, 2 -1 or 2 -1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated and detected in either the transmit or receive directions. The PRBS block can perform an auto synchronization to the expected PRBS pattern and accumulates the total number of bit errors in two 24-bit counters. The error count accumulates over the interval defined by successive writes to the Line Interface Interrupt Source #1 / PMON Update register. When an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available in the Error Count registers until the next accumulation.
9.9
T1 Inband Loopback Code Generator (XIBC) The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code. The contents of the code and its length are programmable from 3 to 8 bits.
9.10 Pulse Density Enforcer (XPDE) The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
This block monitors the digital output of the transmitter and detects when the stream is about to violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. When the XPDE is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered. 9.11 Transmit Jitter Attenuator (TJAT) The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. The incoming data streams are stored in a FIFO timed to the transmit clock. The respective input data emerges from the FIFO timed to the jitter attenuated clock. The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output by adjusting the Transmit clock's phase in 1/96 UI increments to minimize the phase difference between the generated Transmit clock and input data clock to TJAT. Jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the frequency of Transmit clock is equal to the average frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the generated Transmit clock. In E1 applications, the corner frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, the Transmit clock is used to read data out of the FIFO. If the FIFO read pointer (timed to the Transmit clock) comes within one bit of the write pointer (timed to the input data clock), TJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. Jitter Characteristics The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 61 Uipp of input jitter at jitter frequencies above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander, the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references. TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum. TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met. Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter tolerance is 61 Unit Intervals peak-to-peak (Uipp) with a worst case frequency offset of 354 Hz. It is 80 Uipp with no frequency offset. The frequency offset is the difference between the frequency of XCLK and that of the input data clock. Figure 11 - TJAT Jitter Tolerance
100 28 JITTER AMPLITUDE, UI pp 10
JAT MIN.TOLER ANCE
61
1.0
unacceptable
acceptable
0.4
0.1
0.01
1
10
100
1k
10k
100k
JITTER FREQUENCY, Hz
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance. Given that the TJAT PLL reference clock accuracy can be 200 Hz and that the XCLK input accuracy can be 100 ppm, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK are shown in Figure 12.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 12 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy
70 68 65 JAT MIN. JITTER TOLERANCE, 60 UI pp 55 66
61
MAX. FREQUENCY 100 OFFSET XCLK ACCURACY
200 0
250 32
300
354 100
Hz , ppm
Jitter Transfer For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above 5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 13. The figure is valid for the case where the N1 = 2FH in the TJAT Jitter Attenuator Divider N1 Control register and N2 = 2FH in the TJAT Divider N2 Control register.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 13 - TJAT Jitter Transfer
0 -10 JITTER -20 GAIN dB -30 -40 -50 1 5.7 10 100 1k 10k
62411 min JAT response 62411 max 43802 max
JITTER FREQUENCY Hz
T1 In the non-attenuating mode, when the FIFO is within one UI of overrunning or underrunning, the tracking range is 1.48 MHz to 1.608 MHz. The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (61 Uipp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 1.544 MHz 963 Hz with no jitter or system clock frequency offset. E1 In the non-attenuating mode, when the FIFO is within one UI of overrunning or underrunning, the tracking range is 2.13 MHz to 1.97 MHz. The guaranteed linear operating range for the jittered input clock is 2.048 MHz 300 Hz with worst case jitter (61 Uipp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 2.048 MHz 1277 Hz with no jitter or system clock frequency offset. Jitter Generation In the absence of input jitter, the output jitter shall be less than 0.025 Uipp. This complies with the AT&T TR 62411 requirement of less than 0.025 Uipp of jitter generation.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9.12 Line Transmitter The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating. The output pulse shape is synthesized digitally with current digital-to-analogue (DAC) converters, which produce 24 samples per symbol. The current DAC's produce differential bipolar outputs that directly drive the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] pins. The current output is applied to a terminating resistor and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and ensures a small positive to negative pulse imbalance. The pulse shape is user programmable. For T1 short haul, the cable length between the OCTLIU and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. Hence, the data applied to the converter must account for different cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for LBO's of 15 dB or 22.5 dB the previous 3 or 4 bits effect what the transmitter must send out. Refer to the Operation section for details on creating the synthesized pulse shape. 9.13 Timing Options (TOPS) The Timing Options block provides a means of selecting the source of the internal input clock to the TJAT block, and the reference clock for the TJAT digital PLL. 9.14 Scaleable Bandwidth Interconnect (SBI) Interface The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. The bus is timed to a reference 19.44MHz clock and a 2 kHz (or fraction thereof) frame pulse. All sources and sinks of data on the bus are timed to the reference clock and frame pulse. Timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet for DS3 mappings which are not used by the OCTLIU). When the source is slower than the SBI the floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI control signals.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelized DS3 payloads (not used by OCTLIU) follow a byte synchronous structure modeled on the SONET/SDH format. The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3 relative to the STS-3/STM-1 transport frame. The SBI is also of fixed frequency and alignment as determined by the reference clock (REFCLK) and frame indicator signal (C1FP). Frequency deviations are compensated by adjusting the location of the T1/J1/E1/DS3 channels using floating tributaries as determined by the V5 indicator and payload signals (DV5, AV5, DPL and APL). Note that the OCTLIU always operates as a clock slave on the SBI ADD bus and as a clock master on the SBI DROP bus, i.e. it does not support the AJUST_REQ and DJUST_REQ timing adjustment request signals defined in the SBI bus specification. The multiplexed links are separated into three Synchronous Payload Envelopes (SPE). Each envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s or a DS3. The OCTLIU may be configured to use any eight T1/J1 tributaries or any eight E1 tributaries from any of the three SPE's. The eight tributaries need not all be selected from the same SPE. A single OCTLIU device cannot, however, use T1/J1 and E1 tributaries simultaneously. 9.14.1 Interfacing OCTLIUs to a High Density Framer Figure 14 - SBI to Framer Line Side Interface
19.44MHz LREFCLK LAC1 LAC1J1V1 LADATA[7:0] LADP LATPL LAV5 LAPL LDC1J1V1 LDDATA[7:0] LDDP LDTPL LDV5 LDPL LDAIS Framer REFCLK C1FPOUT AC1FP ADATA[7:0] ADP APL AV5 DC1FP DDATA[7:0] DDP DPL DV5
OCTLIUs
Figure 14 shows how the SBI interfaces of multiple OCTLIU's may be connected to the line side interface of a high density framer. With the exception of C1FPOUT, all signals on the OCTLIU side are simply bussed in parallel to the multiple devices. The C1FPOUT port of a single OCTLIU is used to provide a frame reference for all the devices. Alternatively, the C1 frame pulse can be generated by external circuitry if desired. The framer's interface must be configured such that VT pointer processors are bypassed, VT's are byte synchronously mapped, and that the STS-1 SPE's are locked to the STS-3 transport envelope with a fixed pointer offset of 522.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9.15 SBI Extracter and PISO The SBI Extract block receives data from the SBI ADD BUS and converts it to serial bit streams for transmission. The SBI Extract block may be configured to enable or disable extraction of individual tributaries within the SBI ADD bus. It may also be configured to generate an all-1s output to the transmit LIU when an alarm indication is signalled for a particular tributary via the SBI bus. 9.16 SBI Inserter and SIPO The SBI Insert block receives serial data from the LIU octants and inserts it on the SBI DROP BUS. The SBI Insert block may be configured to enable or disable transmission of individual tributaries on to the SBI DROP bus. 9.17 SBI to Clk/Data Converter The OCTLIU may be configured (by setting the SBI_EN and SBI2CLK inputs) to operate in a mode in which the LIUs are disabled and the device performs conversion between the SBI interface and serial clock and data (see Figure 6). Up to eight tributaries may be converted to serial format. The serial data streams are required to share a common clock and frame pulse. In the egress direction (from SBI ADD BUS to egress clk/data), elastic stores are provided to align the tributary outputs to a common clock and frame alignment. 9.18 Serial PROM Interface The serial PROM interface is used to configure the OCTLIU in the absence of a microprocessor. A single SPI-compatible serial PROM can be used to configure a number of OCTLIU devices simultaneously (provided all such devices are intended to be configured identically) by connecting the devices in a cascade as shown in Figure 15. Figure 15 - Serial PROM Cascade Interface
SRCASC VCC HOLD WP
VCC SRCASC
CS SCK SI SO
SREN SRCLK SRDI SRDO
SRCEN SRCCLK n.c. SRCDO
SREN SRCLK SRDI SRDO
SRCEN SRCCLK SRCDO
SPI PROM
OCTLIU Cascade Master
OCTLIU Cascade Slave
SPI-compatible PROMs are organised as n x 8-bit words. The contents of the PROM are read sequentially starting at address 0 and continuing until a specially coded stop command is encountered. Each configuration command is coded in 3-bytes as follows:
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 16 - Serial PROM Command Format
Code1
Code0
Reg[13:8] Reg[7:0] Data[7:0]
Reg[13:0] specifies one of the OCTLIU registers defined in Table 4. Data[7:0] is the value to be written to the specified register. Commands are interpreted depending on the Code1 and Code0 bits as follows: Table 2 - Serial PROM Commands - Code Bits Code0 0 1 0 1 Special Command Write Data[7:0] to Reg[13:0] only if SRCODE = 0 Write Data[7:0] to Reg[13:0] only if SRCODE = 1 Write Data[7:0] to Reg[13:0] regardless of value of SRCODE Action
Code1 0 0 1 1
The SRCODE input to OCTLIU provides a means to execute configuration instructions conditionally. Two different configuration sequences can be stored in a single PROM (for T1 or E1 operation, for example) and the SRCODE input used to select which one will be applied. Different OCTLIU devices in a cascade can have their SRCODE inputs set to different values. When Code1 = Code0 = `0', the Reg[13:0] and Data[7:0] fields are interpreted as a special command, not as a register/data pair. The following special commands are defined: Table 3 - Serial PROM Special Commands Action Resume acting upon register write commands. Only meaningfull if a 3FFD command (see below) has previously been received. No-op. Ignore subsequent register write commands. This command is only acted upon by the first OCTLIU in the cascade which receives it and which is not already ignoring register write commands. The OCTLIU which acts upon this command does not propagate the command down the cascade, but instead substitutes the 3FFC special command.
Reg[13:0] 3FFB 3FFC 3FFD
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Reg[13:0] 3FFE 3FFF
Action Pause for Data[7:0] x 4096 XCLK periods before reading next PROM command. Stop, i.e. configuration of OCTLIU has finished.
The `ignore subsequent register write commands' command can be used to configure multiple OCTLIU's in a cascade individually (for example, to allocate different SBI tributaries to different OCTLIU devices). It provides a means to progressively `switch off' each device in the cascade once it has been configured. Consider for example the following sequence of configuration commands: Command (hex) C00102 : : 3FFD00 C00103 : : : 3FFD00 C00104 : : : Explanation Write 02 to register 01 of all devices in the cascade, regardless of SRCODE. (Subsequent configuration commands are acted upon by all devices in the cascade.) First device in cascade ignores all further register writes. Write 03 to register 01 of all devices in the cascade except the first, regardless of SRCODE. (Subsequent configuration commands are acted upon by all devices in the cascade except the first.) Second device in cascade ignores all further register writes. Write 04 to register 01 of all devices in the cascade except the first two, regardless of SRCODE. (Subsequent configuration commands are acted upon by all devices in the cascade except the first and second.)
The pause command can be used, for example, to allow the clock synthesis circuitry within the CSD block time to stablise before configuring the rest of the device. 9.19 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. 9.20 Microprocessor Interface The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the OCTLIU.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the OCTLIU. Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. The Register Memory Map in Table 4 below shows where the normal mode registers are accessed. The OCTLIU contains 1 set of master configuration, SBI, and CSU registers and 8 sets of T1/E1 LIU registers. Where only 1 set is present, the registers apply to the entire device. Where 8 sets are present, each set of registers apply to a single octant of the OCTLIU. By convention, where 8 sets of registers are present, address space 000H - 07FH applies to octant #1, 080H - 0FFH applies to octant #2, etc, up to 380H - 3FFH for octant #8. On reset the OCTLIU defaults to T1 mode. For proper operation some register configuration is expected. By default interrupts will not be enabled, and automatic alarm generation is disabled. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the OCTLIU to determine the programming state of the chip. 3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect OCTLIU operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with functions that are unused in this application. To ensure that the OCTLIU operates as intended, reserved register bits must only be written with their default values unless otherwise stated. Similarly, writing to reserved registers should be avoided unless otherwise stated.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
10.1 Normal Mode Register Memory Map Table 4 Addr 000H 080H, 100H, 180H, 200H, 280H, 300H, 380H 001H 081H, 101H, 181H, 201H, 281H, 301H, 381H 002H 082H, 102H, 182H, 202H, 282H, 302H, 382H 003H 083H, 103H, 183H, 203H, 283H, 303H, 383H 004H 084H, 104H, 184H, 204H, 284H, 304H, 384H 005H 085H, 105H, 185H, 205H, 285H, 305H, 385H 006H 086H, 106H, 186H, 206H, 286H, 306H, 386H 007H 087H, 107H, 187H, 207H, 287H, 307H, 387H 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH - Normal Mode Register Memory Map Register Reset / Revision ID / Device ID Reserved Global Configuration / Clock Monitor Reserved Master Interrupt Source #1 Reserved Master Interrupt Source #2 Reserved Master Test Control #1 Reserved Master Test Control #2 Reserved CSU Configuration Reserved CSU Reserved Reserved Receive Line Interface Configuration #1 Receive Line Interface Configuration #2 Transmit Line Interface Configuration Transmit Line Interface Timing Options / Clock Monitor / Pulse Template Selection
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH 010H - 03FH 090H - 0BFH 110H - 13FH 190H - 1BFH 210H - 23FH 290H - 2BFH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H
Register Line Interface Interrupt Source #1 / PMON Update Line Interface Interrupt Source #2 Line Interface Diagnostics Line Interface PRBS Position Reserved Reserved Reserved Reserved Reserved Reserved INSBI Control INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Page A Octant to Tributary Mapping #1 INSBI Page A Octant to Tributary Mapping #2 INSBI Page A Octant to Tributary Mapping #3 INSBI Page A Octant to Tributary Mapping #4 INSBI Page A Octant to Tributary Mapping #5 INSBI Page A Octant to Tributary Mapping #6 INSBI Page A Octant to Tributary Mapping #7 INSBI Page A Octant to Tributary Mapping #8 INSBI Page B Octant to Tributary Mapping #1 INSBI Page B Octant to Tributary Mapping #2 INSBI Page B Octant to Tributary Mapping #3 INSBI Page B Octant to Tributary Mapping #4 INSBI Page B Octant to Tributary Mapping #5 INSBI Page B Octant to Tributary Mapping #6 INSBI Page B Octant to Tributary Mapping #7
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 322H 323H 324H 325H 326H 327H 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH - 330H 331H 332H 333H - 33FH 390H 391H 392H 393H 394H 395H 396H 397H 398H 399H 39AH - 39FH 3A0H 3A1H
Register INSBI Page B Octant to Tributary Mapping #8 INSBI Link Enable INSBI Link Enable Busy INSBI Tributary Control #1 INSBI Tributary Control #2 INSBI Tributary Control #3 INSBI Tributary Control #4 INSBI Tributary Control #5 INSBI Tributary Control #6 INSBI Tributary Control #7 INSBI Tributary Control #8 INSBI Minimum Depth INSBI FIFO Thresholds INSBI Reserved INSBI Depth Check Interrupt Status INSBI Master Interrupt Status INSBI Reserved EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Parity Error Interrupt Reason EXSBI Depth Check Interrupt Status EXSBI Master Interrupt Status EXSBI Minimum Depth EXSBI FIFO Thresholds EXSBI Link Enable EXSBI Link Enable Busy EXSBI Reserved EXSBI Tributary Control #1 EXSBI Tributary Control #2
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 3A2H 3A3H 3A4H 3A5H 3A6H 3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H 3B1H 3B2H 3B3H 3B4H 3B5H 3B6H 3B7H 3B8H - 3BFH 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H
Register EXSBI Tributary Control #3 EXSBI Tributary Control #4 EXSBI Tributary Control #5 EXSBI Tributary Control #6 EXSBI Tributary Control #7 EXSBI Tributary Control #8 EXSBI Page A Octant to Tributary Mapping #1 EXSBI Page A Octant to Tributary Mapping #2 EXSBI Page A Octant to Tributary Mapping #3 EXSBI Page A Octant to Tributary Mapping #4 EXSBI Page A Octant to Tributary Mapping #5 EXSBI Page A Octant to Tributary Mapping #6 EXSBI Page A Octant to Tributary Mapping #7 EXSBI Page A Octant to Tributary Mapping #8 EXSBI Page B Octant to Tributary Mapping #1 EXSBI Page B Octant to Tributary Mapping #2 EXSBI Page B Octant to Tributary Mapping #3 EXSBI Page B Octant to Tributary Mapping #4 EXSBI Page B Octant to Tributary Mapping #5 EXSBI Page B Octant to Tributary Mapping #6 EXSBI Page B Octant to Tributary Mapping #7 EXSBI Page B Octant to Tributary Mapping #8 EXSBI Reserved ELST Configuration ELST Interrupt Enable/Status T1 PDVD Reserved T1 PDVD Interrupt Enable/Status
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H
Register T1 XPDE Reserved T1 XPDE Interrupt Enable/Status T1 XIBC Control T1 XIBC Loopback Code RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor (N1) Control TJAT Output Clock Divisor (N2) Control TJAT Configuration IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code CDRC Configuration CDRC Interrupt Control
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H 059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H 05AH, 0DAH, 15AH, 1DAH, 25AH, 2DAH, 35AH, 3DAH 05BH, 0DBH, 15BH, 1DBH, 25BH, 2DBH, 35BH, 3DBH 05CH, 0DCH, 15CH, 1DCH, 25CH, 2DCH, 35CH, 3DCH 05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H 063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H 067H, 0E7H, 167H, 1E7H, 267H, 2E7H, 367H, 3E7H
Register CDRC Interrupt Status CDRC Alternate Loss of Signal PMON Interrupt Enable/Status PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON LCV Count (LSB) PMON LCV Count (MSB) PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status PRBS Pattern Select PRBS Reserved PRBS Error Count #1 PRBS Error Count #2 PRBS Error Count #3 PRBS Reserved
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH 06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH 06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H
Register XLPG Control/Status XLPG Pulse Waveform Scale XLPG Pulse Waveform Storage Write Address #1 XLPG Pulse Waveform Storage Write Address #2 XLPG Pulse Waveform Storage Data XLPG Reserved XLPG Reserved XLPG Reserved RLPS Configuration and Status RLPS ALOS Detection/Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization Read/WriteB Select RLPS Equalizer Loop Status and Control RLPS Equalizer Configuration RLPS Equalization Indirect Data Register RLPS Equalization Indirect Data Register
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH 07EH, 0FEH, 17EH, 1FEH, 27EH, 2FEH, 37EH, 3FEH 07FH, 0FFH, 17FH, 1FFH, 27FH, 2FFH, 37FH, 3FFH 400H - 7FFH
Register RLPS Indirect Data Register RLPS Indirect Data Register RLPS Voltage Thresholds #1 RLPS Voltage Thresholds #2 RLPSReserved RLPS Reserved Reserved for Test
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 000H: Reset / Revision ID / Device ID Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET: The RESET bit implements a software reset. If the RESET bit is a logic 1, the OCTLIU is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the OCTLIU out of reset. Holding the OCTLIU in a reset state effectively puts it into a low-power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the software reset. TYPE: The device identification bits, TYPE[2:0], are set to a fixed value of "100" ID: The version identification bits, ID[3:0], are set to a fixed value representing the version number of the OCTLIU. Type R/W R R R R R R R Function RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] Default 0 1 0 0 0 0 0 0
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 001H: Global Configuration / Clock Monitor Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XCLKA: The XCLK active (XCLKA) bit detects low to high transitions on the XCLK input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read. A lack of transitions is indicated by the register bit reading low. This register bit may be read at periodic intervals to detect clock failures. REFCLKA: The REFCLK active (REFCLKA) bit detects low to high transitions on the REFCLK input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read. A lack of transitions is indicated by the register bit reading low. This register bit may be read at periodic intervals to detect clock failures. SIMUL_REGWR: The Simultaneous Register Write (SIMUL_REGWR) bit enables registers for all 8 octants to be written simultaneously. When SIMUL_REGWR is set high, a write to an octant register will result in the same data also being written simultaneously to the corresponding registers belonging to the other 7 octants. When SIMUL_REGWR is set low, a write to a register will result in the addressed register, and that register only, being written. Note - SIMUL_REGWR must be set low prior to reading any OCTLIU register. SBI_SYNCH: The SBI Synchronous Mode (SBI_SYNCH) bit configures the INSBI to operate in SBI Synchronous mode when set to 1. Synchronous mode should only be selected when the device is operating as a SBI to clk/data converter (SBI2CLK input tied high). When operating in synchronous mode, the ICLK_OUT and IFP_OUT outputs must be used as clock and Type R R R/W R/W R/W R/W R/W R/W Function XCLKA REFCLKA SIMUL_REGWR SBI_SYNCH RSYNC_SEL[2] / ELST_SEL[2] RSYNC_SEL[1] / ELST_SEL[1] RSYNC_SEL[0] / ELST_SEL[0] E1/T1B Default X X 0 0 0 0 0 0
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59
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
frame pulse references, but need not be looped back to the ICLK_IN and IFP_IN inputs. (In synchronous mode, the loopback is done internally and the ICLK_IN and IFP_IN inputs are ignored.) RSYNC_SEL[2:0]: When the SBI2CLK input is tied low, the RSYNC Select register bits, RSYNC_SEL[2:0], select the source of the RSYNC OCTLIU output. When RSYNC_SEL[2:0] = "000", octant #1 is selected as the source. When RSYNC_SEL[2:0] = "001", octant #2 is selected as the source. When RSYNC_SEL[2:0] = "010", octant #3 is selected as the source. When RSYNC_SEL[2:0] = "011", octant #4 is selected as the source. When RSYNC_SEL[2:0] = "100", octant #5 is selected as the source. When RSYNC_SEL[2:0] = "101", octant #6 is selected as the source. When RSYNC_SEL[2:0] = "110", octant #7 is selected as the source. When RSYNC_SEL[2:0] = "111", octant #8 is selected as the source. ELST_SEL[2:0]: When the SBI2CLK input is tied high, the Elastic Store Select register bits, ELST_SEL[2:0], select the source of the clock and frame pulse used to read data from the Elastic Stores. The clock and frame pulse are derived from one of the SBI tributaries de-mapped from the SBI BUS and are output on ECLK and EFP respectively. When ELST_SEL[2:0] = "000", EXSBI link #1 is selected as the source. When ELST_SEL[2:0] = "001", EXSBI link #2 is selected as the source. When ELST_SEL[2:0] = "010", EXSBI link #3 is selected as the source. When ELST_SEL[2:0] = "011", EXSBI link #4 is selected as the source. When ELST_SEL[2:0] = "100", EXSBI link #5 is selected as the source. When ELST_SEL[2:0] = "101", EXSBI link #6 is selected as the source. When ELST_SEL[2:0] = "110", EXSBI link #7 is selected as the source. When ELST_SEL[2:0] = "111", EXSBI link #8 is selected as the source. E1/T1B: The global E1/T1B bit selects the operating mode of all eight of the OCTLIU octants. If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected for all eight octants. If E1/T1B is logic 0, the 1.544 Mbit/s T1 mode is selected for all eight octants.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 002H: Master Interrupt Source #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LIU[8:1]: The LIU[8:1] register bits allow software to determine which octant's LIU(s) is/are producing an interrupt on the INTB output pin. A logic 1 indicates an interrupt is being produced from the corresponding octant. Reading this register does not remove the interrupt indication; within the corresponding octant, the corresponding block's interrupt status register must be read to remove the interrupt indication. Type R R R R R R R R Function LIU[8] LIU[7] LIU[6] LIU[5] LIU[4] LIU[3] LIU[2] LIU[1] Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 003H: Master Interrupt Source #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INSBI, EXSBI: The INSBI and EXSBI register bits allow software to determine whether the INSBI and/or EXSBI blocks are producing an interrupt on the INTB output pin. A logic 1 indicates an interrupt is being produced from the corresponding block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. R R Type Function Unused Unused Unused Unused Unused Unused EXSBI INSBI Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 004H: Master Test Control #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type W W W W W R/W W R/W Function Reserved Reserved Reserved Reserved Reserved Reserved HIZDATA HIZIO Default X X X X 0 0 0 0
This register is used to select OCTLIU test features. All bits, except for 7,6,5 and 4 are reset to zero by a hardware reset of the OCTLIU, a software reset of the OCTLIU does not affect the state of the bits in this register. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the OCTLIU. While the HIZIO bit is a logic 1, all output pins of the OCTLIU except TDO and the data bus are held in a highimpedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 005H: Master Test Control #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: These bits must be 0 for correct operation. R/W R/W R/W Type R/W R/W R/W R/W Function Reserved Reserved Reserved Reserved Unused Unused Unused Unused Default 0 0 0 0 X X X X
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64
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 006H: CSU Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE[2:0]: The MODE[2:0] selects the mode of the CSU. Table 5 indicates the required XCLK frequency, and output frequencies for each mode. Table 5 - Clock Synthesis Mode MODE[2:0] 000 001 01X 10X 110 111 CSU_LOCK: The CSU_LOCK bit can be used to determine whether or not the embedded clock synthesis unit (CSU) has achieved phase and frequency lock to XCLK. If the CSU_LOCK bit is polled repetitively and is persistently a logic 1, then the divided down synthesized clock frequency is within 244 ppm of the XCLK frequency. A persistent logic 0 may indicate a mismatch between the actual and expected XCLK frequency or a problem with the analogue supplies (CAVS and CAVD). IDDQ_EN: The IDDQ enable bit (IDDQ_EN) is used to configure the embedded CSU for IDDQ tests. When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1 register is a XCLK frequency 2.048 MHz 1.544 MHz Reserved Reserved Reserved 2.048 MHz Transmit clock frequency 2.048 MHz 1.544 MHz Reserved Reserved Reserved 1.544 MHz R R/W R/W R/W Type R/W R/W Function CSU_RESET IDDQ_EN Unused Unused CSU_LOCK MODE[2] MODE[1] MODE[0] Default 0 0 X X X 0 0 0
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65
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
logic 1, the digital outputs of the CSU are pulled to ground. When either the IDDQ_EN bit or IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration register must also be set to logic 1. CSU_RESET: Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a frequency much lower than normal operation.
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66
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: Receive Line Interface Configuration #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LLB_AIS: When the LLB_AIS bit is set to logic 1, the LIU will generate AIS on the receive data output whenever line loopback is active. When the LLB_AIS bit is set to logic 0, the LIU receive path will operate normally, regardless of whether or not line loopback is active. If LLB_AIS is logic 0, AIS may be inserted manually via the RAIS register bit. AUTO_LLB: When the AUTO_LLB bit is set to logic 1, the LIU will activate and deactivate line loopback automatically upon detection of the line loopback activate/deactivate codes by the IBCD. The AUTO_LLB bit is only valid in T1 mode and must be set to logic 0 in E1 mode. LOS_SBI: The LOS_SBI bit enables the indication of loss of signal over the SBI interface. When LOS_SBI is set to logic 1, loss of signal will result in the ALM (alarm) bit of the affected tributary being asserted on the SBI interface. When LOS_SBI is set to logic 0, the tributary's ALM bit will be set to 0. LOS_AIS: If the LOS_AIS bit is logic 1, AIS is inserted in the receive path for the duration of a loss of signal condition. [ref: T1.403-1995 Annex H]. If LOS_AIS is logic 0, AIS may be inserted manually via the RAIS register bit. RDUAL: The RDUAL bit configures the LIU receive path for dual-rail (bipolar) operation. When RDUAL is set to logic 1, NRZ sampled bipolar positive and negative pulses are output on RDP[n] and RDN[n] respectively. When RDUAL is set to logic 0, NRZ sampled unipolar data Type R/W R/W R/W R/W R/W R/W R/W R/W Function LLB_AIS AUTO_LLB LOS_SBI LOS_AIS RDUAL BPV RINV RFALL Default 0 0 0 0 0 0 0 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
is output on RDP[n] (decoded according to AMI, B8ZS or HDB3) and line code violations / excessive zeros are signalled on RLCV[n]. If RDUAL is set to logic 1, the PDVD, IBCD and PRBS blocks, and also the ability to generate AIS, are disabled in the LIU receive path. BPV: In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs (provided they are not part of a valid B8ZS signature if B8ZS line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (provided they are not part of a valid B8ZS signature if B8ZS line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than seven bits long for a B8ZS-coded signal. In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. (The O162 bit in the CDRC Configuration register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (provided they are not part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (provided they are not part of a valid HDB3 signature if HDB3 line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than four bits long for an HDB3-coded signal. RINV: When RINV is set to logic 1, the receive digital outputs RDP[n] and RDN/RLCV[n] are assumed to be active low and all output data and LCV indications are inverted. When RINV is set to logic 0, the receive digital outputs RDP[n] and RDN/RLCV[n] are assumed to be active high. RINV must be set to 0 when the SBI interface is enabled (SBI_EN = 1). RFALL: When RFALL is set to logic 1, the RDP[n] and RDN/RLCV[n] outputs are updated on falling edges of RCLK[n]. When RFALL is set to logic 0, the outputs are updated on rising edges of RCLK[n]. RFALL must be set to 1 when the SBI interface is enabled (SBI_EN = 1).
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: Receive Line Interface Configuration #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RJATBYP: The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the receiver section by typically 40 bits. When RJATBYP is set to logic 0, the LIU's RSYNC output is jitter attenuated. When the RJAT is bypassed, the octant's RSYNC is not jitter attenuated. RSYNC_ALOSB: The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the RSYNC output. If RSYNC_ALOSB is a logic 0, analogue loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used. When the LIU is in a loss of signal state, the RSYNC output is derived from XCLK or held high, as determined by the RSYNC_MEM bit. When the LIU is not in a loss of signal state, the RSYNC output is derived from the receive recovered clock of the selected octant. The octant to be used as the source of RSYNC is determined by the RSYNC_SEL[2:0] bits. RSYNC_MEM: The RSYNC_MEM bit controls the octant's RSYNC output under a loss of signal condition (as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the octant's RSYNC output is held high during a loss of signal condition. When RSYNC_MEM is a logic 0, the octant's RSYNC output is derived from the CSU 1x line rate clock during a loss of signal condition. RSYNCSEL: The RSYNCSEL bit selects the frequency of the receive reference presented on the octant's RSYNC output. If RSYNCSEL is a logic 1, the octant's RSYNC will be an 8 kHz clock. If R/W R/W R/W Type R/W Function RJATBYP Unused Unused Unused Unused RSYNC_ALOSB RSYNC_MEM RSYNCSEL Default 1 X X X X 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RSYNCSEL is a logic 0, the octant's RSYNC will be an 1.544 MHz (T1) or 2.048 MHz (E1) clock.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: Transmit Line Interface Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TJATBYP: The TJATBYP bit enables the transmit jitter attenuator to be removed from the transmit data path. When the transmit jitter attenuator is bypassed, the latency through the transmitter section is reduced by typically 40 bits. TAISEN: The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the TXTIP[n] and TXRING[n]. When TAISEN is set to logic 1, the bipolar TXTIP[n] and TXRING[n] outputs are forced to pulse alternately, creating an all-ones signal. The transition to transmitting AIS on the TXTIP[n] and TXRING[n] outputs is done in such a way as to avoid introducing any bipolar violations. The diagnostic digital loopback point is prior to the AIS insertion point. (Implementation note. TAISEN has priority over TAUXP, which in turn has priority over TDATINV.). TAUXP: The TAUXP bit enables the interface to generate an unframed alternating zeros and ones (i.e. 010101...) auxiliary pattern (AUXP) on the TXTIP[n] and TXRING[n]. When TAUXP is set to logic 1, the bipolar TXTIP[n] and TXRING[n] outputs are forced to pulse alternately every other cycle. The transition to transmitting AUXP on the TXTIP[n] and TXRING[n] outputs is done in such a way as to avoid introducing any bipolar violations. The diagnostic digital loopback point is prior to the AUXP insertion point. SBI_AIS: The SBI_AIS bit enables the insertion of AIS in the transmit path in response to an alarm indication from the SBI interface. When SBI_AIS is set to logic 1, setting the ALM (alarm) bit Type R/W R/W R/W R/W R/W R/W R/W R/W Function TJATBYP TAISEN TAUXP SBI_AIS TDUAL AMI TINV TRISE Default 0 0 0 1 0 0 0 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
of a tributary on the SBI interface causes the bipolar TXTIP[n] and TXRING[n] outputs to be forced to pulse alternately, creating an all-ones signal. The transition to transmitting AIS on the TXTIP[n] and TXRING[n] outputs is done in such a way as to avoid introducing any bipolar violations. The diagnostic digital loopback point is prior to the AIS insertion point. TDUAL: The TDUAL bit configures the LIU transmit path for dual-rail (bipolar) operation. When TDUAL is set to logic 1, NRZ bipolar positive and negative data is input on TDP[n] and TDN[n] respectively. When TDUAL is set to logic 0, NRZ unipolar data is input on TDP[n] and TDN[n] is ignored. TDUAL must be set to logic 0 when operating in SBI mode (i.e. when the SBI_EN input is logic 1). If TDUAL is set to logic 1, the XIBC, XPDE, LCODE and PRBS blocks are disabled in the LIU transmit path. AMI: The AMI bit enables AMI line coding. If AMI is set to a logic 1, the LIU will perform AMI line encoding on the TDP[n] single-rail input data stream. If AMI is set to a logic 0, the LIU will perform B8ZS (if operating in T1 mode) or HDB3 (if operating in E1 mode) line encoding on the TDP[n] data stream. The AMI bit is ignored if the TDUAL bit is set to logic 1. TINV: When TINV is set to logic 1, the transmit digital inputs TDP[n] and TDN[n] are assumed to be active low and all input data is inverted. When TINV is set to logic 0, the transmit digital inputs TDP[n] and TDN[n] are assumed to be active high. TRISE: When TRISE is set to logic 1, the TDP[n] and TDN[n] inputs are sampled on rising edges of TCLK[n]. When TRISE is set to logic 0, the inputs are sampled on falling edges of TCLK[n].
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH: Transmit Timing Options / Clock Monitor / Pulse Template Selection Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT_SEL[3:0]: The Pulse Template Selection (PT_SEL[3:0]) bits determine which of the twelve pulse template waveforms stored in the XLPG is used to generate transmit data pulses on the TXTIP[n] and TXRING[n] outputs. PT_SEL[3:0] must be set to a value between 0 and 11. PT_SEL[3:0] are not used when operating in hardware-only mode (HW_ONLY input = 1). In hardware-only mode, the LENx[2:0] inputs select which pulse template is to be used and only pulse templates 0 to 7 may be selected. TCLKA: The TCLK[n] active (TCLKA) bit detects low to high transitions on the TCLK[n] input. TCLKA is set high on a rising edge of TCLK[n], and is set low when this register is read. A lack of transitions is indicated by the register bit reading low. This register bit may be read at periodic intervals to detect clock failures. OCLKSEL: The OCLKSEL bit selects the source of the Transmit Jitter Attenuator FIFO output clock signal. Type R/W R/W R/W R/W R R/W R/W R/W Function PT_SEL[3] PT_SEL[2] PT_SEL[1] PT_SEL[0] TCLKA OCLKSEL PLLREF[1] PLLREF[0] Default 0 0 0 0 X 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 6
- TJAT FIFO Output Clock Source OCLKSEL 0 1 Source of FIFO Output Clock The TJAT FIFO output clock is connected to the internal jitter-attenuated 1.544 MHz or 2.048 MHz clock. The TJAT FIFO output clock is connected to the FIFO input clock. In this mode the jitter attenuation is disabled and the input clock must be jitter-free. PLLREF[1:0] must be set to "00" in this mode.
PLLREF: The PLLREF bit selects the source of the Transmit Jitter Attenuator phase locked loop reference signal as follows: Table 7 - TJAT PLL Source PLLREF[1:0] 00 01 1X Source of PLL Reference TJAT FIFO input clock (either the transmit clock or the receive recovered clock, as selected by LINELB) Receive recovered clock CSU transmit clock (see Table 5)
Upon reset of the OCTLIU, the OCLKSEL and PLLREF bits are cleared to zero, selecting jitter attenuation with transmit line clock referenced to the transmit clock, TCLK[n] (or the SBI tributary clock). Figure 17 illustrates the various bit setting options, with the reset condition highlighted.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 17 - Transmit Timing Options
1
Transmit data in
Transmit data out TJA TBY P Transmit line clock OCLKSEL OR TJA TBYP
0
TJAT FIFO
TCLK[n] / SBI transmit clock
0 1
LINELB
FIFO input data clock FIFO output data clock
0 1
Receive recovered clock CSU transmit clock
00 01 1X
PLLREF
TJAT PLL
"Jitter-free" line rate clock (1.544MHz or 2.048MHz) 24x line rate clock for pulse generation
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH: Line Interface Interrupt Source #1 / PMON Update Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PMON PRBS IBCD PDVD XPDE TJAT RJAT CDRC Default X X X X X X X X
This register allows software to determine the block which produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. Writing any value to this register causes the octant's performance monitor LCV counter and PRBS error counter to be updated.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: Line Interface Interrupt Source #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type R Function ELST Unused Unused Unused Unused Unused Unused RLPS Default X X X X X X X X
This register allows software to determine the block that produced the interrupt on the INTB output pin. A logic 1 indicates an interrupt was produced from the block. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH: Line Interface Diagnostics Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCVINS: The LCVINS bit introduces a single line code violation on the transmitted data stream. In B8ZS, the violation is generated by masking the first violation pulse of a B8ZS signature. In AMI, one pulse is sent with the same polarity as the previous pulse. In HDB3, the violation is generated by causing the next HDB3-code generated bipolar violation pulse to be of the same polarity as the previous bipolar violation. To generate another violation, this bit must first be written to 0 and then to logic 1 again. At least one bit period should elapse between writing LCVINS 0 and writing it 1 again, or vice versa, if an error is to be successfully inserted. LCVINS has no effect when TDUAL is set to logic 1. LINELB: The LINELB bit selects the line loopback mode, where the recovered data are internally directed to the digital inputs of the transmit jitter attenuator. The data sent to the TJAT is the recovered data from the output of the CDRC block. When LINELB is set to logic 1, the line loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 mode / FFH in E1 mode and the Transmit Timing Options register should be cleared to all zeros. Only one of LINELB and DDLB can be enabled at any one time. RAIS: When the RAIS bit is set to logic 1, the receive output data stream of the octant is forced to all ones. DDLB: The DDLB bit selects the diagnostic digital loopback mode, where the octant is configured to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail RZ R/W R/W R/W R/W R/W R/W Type Function Unused Unused LCVINS LINELB RAIS DDLB Reserved Reserved Default X X 0 0 0 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
outputs of the TJAT are directed to the dual-rail inputs of the CDRC. When DDLB is set to logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to logic 0, the diagnostic digital loopback mode is disabled. Only one of LINELB and DDLB can be enabled at any one time. Reserved: These bits must be a logic 0 for correct operation.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: Line Interface PRBS Position Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX_GEN: The Transmit Path Generate, TX_GEN, bit controls the output of the PRBS generator. When TX_GEN is set to logic 1, the PRBS generator output is inserted into the transmit path. When TX_GEN is set to logic 0, the transmit path functions normally. RX_GEN: The Receive Path Generate, RX_GEN, bit controls the output of the PRBS generator. When RX_GEN is set to logic 1, the PRBS generator output is inserted into the receive path. When RX_GEN is set to logic 0, the receive path functions normally. TX_DET: The Transmit Path Detect, TX_DET, bit controls the input of the PRBS checker. When TX_DET is set to logic 1, the PRBS checker monitors the transmit path. When TX_DET is set to logic 0, the PRBS detector monitors the receive path. R/W R/W R/W Type Function Unused Unused Unused Unused Unused TX_GEN RX_GEN TX_DET Default X X X X X 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 310H: INSBI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBI_PAR_CTL: The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI data parity signal, DDP as follows: * * TS_EN: The TS_EN bit is used to enable the SBI tributary to LIU octant data stream mapping capability. * When TS_EN is a `0', the mapping is fixed to a one to one mapping and is not programmable. The 8 LIU data streams are mapped to tributaries 1 to 8 of SPE #1 within the SBI structure. When TS_EN is a `1', SBI tributary to LIU octant data stream mapping is enabled and is specified by the contents of the INSBI Tributary Mapping registers. When SBI_PAR_CTL is a `0' parity will be even. When SBI_PAR_CTL is a `1' parity will be odd. R/W Type R/W R/W R/W R/W R/W R/W Function APAGE DC_ENBL DC_INT_EN FIFO_OVRE FIFO_UDRE TS_EN Unused SBI_PAR_CTL Default 0 1 0 0 0 0 X 1
*
FIFO_UDRE: The FIFO_UDRE bit is used to enable/disable the generation of an interrupt when a FIFO underrun is detected. * * When FIFO_UDRE is a `0' underrun interrupt generation is disabled. When FIFO_UDRE is a `1' underrun interrupt generation is enabled.
FIFO_OVRE: The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO overrun is detected. * When FIFO_OVRE is a `0' overrun interrupt generation is disabled.
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81
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
*
When FIFO_OVRE is a `1' overrun interrupt generation is enabled.
DC_INT_EN: This bit is set to enable the generation of an interrupt when either of the following events occurs: * * DC_ENBL: This bit enables depth check resets. The depth checker periodically monitors the link FIFO depths and compares them against the read and write pointers. Discrepancies are reported in the Depth Checker Interrupt Status Register. If DC_ENBL is `1', the affected link is automatically reset. If DC_ENBL is `0', the link is not reset. APAGE: The tributary mapping register active page select bit (APAGE) controls the selection of one of two pages of tributary mapping registers. When APAGE is set low, the configuration in page A of the tributary mapping registers is used to associate SBI tributaries to LIU octant data streams. When APAGE is set high, the configuration in page B of the tributary mapping registers is used to associate SBI tributaries to LIU octant data streams. When APAGE changes state, any data streams where the mapping registers do not match are automatically reset. A Depth Check error An external resynchronization event occurs on the DC1FP signal
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82
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 311H: INSBI FIFO Underrun Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO_UDRI: This bit is set when a FIFO underrun is detected. It is cleared when the register is read (but may be set again immediately thereafter if a further underrun report is pending). LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the underrun was detected. LINK[3:0] should only be looked at when FIFO_UDRI is a `1'. Valid values of LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] FIFO_UDRI Default X X X 0 0 0 0 0
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83
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 312H: INSBI FIFO Overrun Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO_OVRI: This bit is set when a FIFO overrun is detected. It is cleared when the register is read (but may be set again immediately thereafter if a further overrun report is pending). LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the overrun was detected. LINK[3:0] should only be looked at when FIFO_OVRI is a `1'. Valid values of LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] FIFO_OVRI Default X X X 0 0 0 0 0
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84
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 313H - 31AH: INSBI Page A Octant to Tributary Mapping #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] Default X 0 0 0 0 0 0 0
SPE[1:0] and TRIB[4:0]: The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI tributary mapping when APAGE is set to 0. The output of the octant corresponding to the register (1-8) is mapped to the SPE and tributary specified by the value of SPE[1:0] and TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1 to 28 in T1 mode and from 1 to 21 in E1 mode. Note: The mapping of more than one tributary to the same LIU octant data stream or more than one LIU octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all LIU octants and tributaries are uniquely mapped when using multiple OCTLIU's on the same SBI bus. Failure to do so will result in bus contention.
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85
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 31BH - 322H: INSBI Page B Octant to Tributary Mapping #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] Default X 0 0 0 0 0 0 0
SPE[1:0] and TRIB[4:0]: The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI tributary mapping when APAGE is set to 1. The output of the octant corresponding to the register (1-8) is mapped to the SPE and tributary specified by the value of SPE[1:0] and TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1 to 28 in T1 mode and from 1 to 21 in E1 mode. Note: The mapping of more than one tributary to the same LIU octant data stream or more than one LIU octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all LIU octants and tributaries are uniquely mapped when using multiple OCTLIU's on the same SBI bus. Failure to do so will result in bus contention.
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86
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 323H: INSBI Link Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ENBL8 ENBL7 ENBL6 ENBL5 ENBL4 ENBL3 ENBL2 ENBL1 Default 0 0 0 0 0 0 0 0
ENBL1 - ENBL8: The ENBLx bits are used to enable the LIU octant data streams. Setting the ENBL bit for a particular LIU octant data stream enables the INSBI8 to take data from the octant and transmit that data to the SBI tributary mapped to that stream.
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87
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 324H: INSBI Link Enable Busy Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BUSY: A write to the INSBI Link Enable Register sets BUSY to `1'. BUSY is cleared to `0' approximately three REFCLK cycles later after the register contents have been synchronized to REFCLK. The user must check that BUSY is `0' before writing to the INSBI Link Enable Register. Following a reset, BUSY will be `1' until startup circuitry has finished automatically initializing certain RAMs within INSBI. R Type Function Unused Unused Unused Unused Unused Unused Unused BUSY Default X X X X X X X 0
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88
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 325H - 32CH: INSBI Tributary Control #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused Reserved Reserved TRIB_TYP[1] TRIB_TYP[0] Reserved Default X X X 0 0 1 0 0
A tributary control register should only be written when the associated ENBLx bit is `0'. Reserved: The reserved bits must be set to 0 for correct operation of the OCTLIU device. TRIB_TYP[1:0]: The TRIB_TYP[1:0] field specifies the characteristics of the SBI tributary, as shown in Table 8. Table 8 - INSBI Tributary Characteristics TRIB_TYP[1:0] 00 01 10 11 Description Reserved. Framed (IFP_IN determines frame alignment). Unframed (IFP_IN ignored). Reserved.
The TRIB_TYP[1:0] bits must be set to "10" whenever the LIUs are enabled (SBI2CLK tied low).
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89
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 32DH: INSBI Minimum Depth Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIN_DEP [3:0]: The MIN_DEPTH[3:0] bits specify the tributary FIFO Minimum Depth, i.e. the depth that must be reached before the FIFO reader starts to take data from the FIFO. R/W R/W R/W R/W Type Function Unused Unused Unused Unused MIN_DEP[3] MIN_DEP[2] MIN_DEP[1] MIN_DEP[0] Default X X X X 0 1 1 1
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90
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 32EH: INSBI FIFO Thresholds Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIN_THR[3:0]: The MIN_THR[3:0] bits specify the tributary FIFO minimum threshold, i.e. the FIFO depth below which a positive justification is performed. Note - The default value of this register is the recommended value when operating in T1 mode. When operating in E1 mode, it is recommended that MIN_THR[3:0] be set to "0010". MAX_THR[3:0]: The MAX_THR[3:0] bits specify the tributary FIFO maximum threshold, i.e. the FIFO depth which when exceeded will cause a negative justification. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MIN_THR[3] MIN_THR[2] MIN_THR[1] MIN_THR[0] MAX_THR[3] MAX_THR[2] MAX_THR[1] MAX_THR[0] Default 0 1 1 0 1 1 1 0
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91
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 331H: INSBI Depth Check Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DCR_INTI: This bit is set when a depth check error is detected. It is cleared when the register is read (but may be set again immediately thereafter if a further depth check error report is pending). LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the depth check error was detected. LINK[3:0] should only be looked at when DCR_INTI is a `1'. Valid values for LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] DCR_INTI Default X X X 0 0 0 0 0
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92
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 332H: INSBI Master Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type Function Unused Unused DCR_INTI_SHDW Unused FIFO_UDRI_SHDW FIFO_OVRI_SHDW Unused C1FP_SYNC_INTI Default X X 0 X 0 0 X 0
C1FP_SYNC_INTI: This bit is set when a DC1FP realignment has been detected. It is cleared when the register is read. FIFO_OVRI_SHDW: This bit is a shadow of the FIFO_OVRI bit in the INSBI FIFO Over Run Interrupt Status Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is set. Reading this register has no affect on the interrupt status. FIFO_UDRI_SHDW: This bit is a shadow of the FIFO_UDRI bit in the INSBI FIFO Under Run Interrupt Status Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is set. Reading this register has no affect on the interrupt status. DCR_INTI_SHDW: This bit is a shadow of the DCR_INTI bit in the INSBI Depth Check Interrupt Status Register. It is set when the DCR_INTI bit is set and the interrupt enable DCR_INT_EN is set. Reading this register has no affect on the interrupt status.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 390H: EXSBI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBI_PAR_CTL: The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI data parity signal, ADP as follows: * * When SBI_PAR_CTL is a `0' parity will be even. When SBI_PAR_CTL is a `1' parity will be odd. Type R/W R/W R/W R/W R/W R/W R/W R/W Function APAGE DC_ENBL DC_INT_EN FIFO_OVRE FIFO_UDRE TS_EN SBI_PERR_EN SBI_PAR_CTL Default 0 1 0 0 0 0 0 1
SBI_PERR_EN: The SBI_PERR_EN bit is used to enable the SBI Parity Error interrupt generation * * When SBI_PERR_EN is `0' SBI Parity Error Interrupts will be disabled When SBI_PERR_EN is `1' SBI Parity Error Interrupts will be enabled
In both cases the SBI Parity checker logic will update the SBI Parity Error Interrupt Reason Register. TS_EN: The TS_EN bit is used to enable the SBI tributary to LIU octant data stream mapping capability. * When TS_EN is a `0', the mapping is fixed to a one to one mapping and is not programmable. The 8 LIU data streams are mapped to tributaries 1 to 8 of SPE #1 within the SBI structure. When TS_EN is a `1', SBI tributary to LIU octant data stream mapping is enabled and is specified by the contents of the EXSBI Tributary Mapping registers.
*
FIFO_UDRE: The FIFO_UDRE bit is used to enable/disable the generation of an interrupt when a FIFO underrun is detected.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
* *
When FIFO_UDRE is a `0' underrun interrupt generation is disabled. When FIFO_UDRE is a `1' underrun interrupt generation is enabled.
FIFO_OVRE: The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO overrun is detected. * * When FIFO_OVRE is a `0' overrun interrupt generation is disabled. When FIFO_OVRE is a `1' overrun interrupt generation is enabled.
DC_INT_EN: This bit is set to enable the generation of an interrupt when either of the following events occurs: * * DC_ENBL: This bit enables depth check resets. The depth checker periodically monitors the link FIFO depths and compares them against the read and write pointers. Discrepancies are reported in the Depth Checker Interrupt Status Register. If DC_ENBL is `1', the affected link is automatically reset. If DC_ENBL is `0', the link is not reset. APAGE: The tributary mapping active page select bit (APAGE) controls the group of mapping registers used to associate SBI tributaries and LIU octant data streams. When mapping is enabled and APAGE is low, the A set of mapping registers (0x3A8 to 0x3AF) is used. When mapping is enabled and APAGE is high, the B set of mapping registers (0x3B0 to 0x3B7) is used. When APAGE changes state, any data streams where the mapping registers do not match are automatically reset. A Depth Check error An external resynchronization event occurs on the AC1FP signal
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 391H: EXSBI FIFO Underrun Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO_UDRI: This bit is set when a FIFO underrun is detected. It is cleared when the register is read. LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the underrun was detected. LINK[3:0] should only be looked at when FIFO_UDRI is a `1'. Valid values of LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] FIFO_UDRI Default X X X 0 0 0 0 0
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96
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 392H: EXSBI FIFO Overrun Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO_OVRI: This bit is set when a FIFO overrun is detected. It is cleared when the register is read. LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the over-run was detected. LINK[3:0] should only be looked at when FIFO_OVRI is a `1'. Valid values of LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] FIFO_OVRI Default X X X 0 0 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 393H: EXSBI Parity Error Interrupt Reason Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERRI: When set PERRI indicates that an SBI parity error has been detected. It is cleared when the register is read. TRIB[4:0] and SPE[1:0]: The TRIB[4:0] and SPE[1:0] field are used to specify the SBI tributary for which a parity error was detected. These fields are only valid only when PERRI is set. When a parity error has not been detected the TRIB[4:0] field may contain an out of range tributary value. If the type of the SPE where the parity error occurred does not correspond to the operating mode of the OCTLIU (e.g. a parity error in a SPE containing E1s when the OCTLIU is operating in T1 mode), SPE[1:0] will be valid but TRIB[4:0] will be invalid. Values in these fields should only be looked at when PERRI is a `1'. Type R R R R R R R R Function SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] PERRI Default 0 0 0 0 0 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 394H: EXSBI Depth Check Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DCRI: This bit is set when a Depth Check error is detected. It is cleared when the register is read. LINK[3:0]: The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO buffer in which the depth check error was detected. LINK[3:0] should only be looked at when DCRI is a `1'. Valid values for LINK[3:0] are from 1 to 8. This register will contain the interrupt status even if the corresponding interrupt enable is not set. R R R R R Type Function Unused Unused Unused LINK[3] LINK[2] LINK[1] LINK[0] DCRI Default X X X 0 0 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 395H: EXSBI Master Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C1FP_SYNCI: This bit is set when a AC1FP realignment has been detected. Reading this register clears this interrupt source. FIFO_OVRI_SHDW: This bit is a shadow of the FIFO_OVRI bit in the EXSBI FIFO Overrun Interrupt Status Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is set. Reading this register has no affect on this interrupt source. FIFO_UDRI_SHDW: This bit is a shadow of the FIFO_UDRI bit in the EXSBI FIFO Underrun Interrupt Status Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is set. Reading this register has no affect on this interrupt source. PERRI_SHDW: This bit is a shadow of the PERRI bit in the EXSBI Parity Error Interrupt Reason Register. It is set when the PERRI bit is set and the interrupt enable SBI_PERR_EN is set. Reading this register has no affect on this interrupt source. DCRI_SHDW: This bit is a shadow of the DCRI bit in the EXSBI Depth Check Interrupt Status Register. It is set when the DCRI bit is set and the interrupt enable DCR_INT_EN is set. Reading this register has no affect on this interrupt source. Reserved: The reserved bit must be set to 0 for correct operation of the OCTLIU device. R R R R R Type R/W Function Reserved Unused DCRI_SHDW PERRI_SHDW FIFO_UDRI_SHDW FIFO_OVRI_SHDW Unused C1FP_SYNCI Default 0 X 0 0 0 0 X 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 396H: EXSBI Minimum Depth Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIN_DEP[3:0]: The MIN_DEPTH[3:0] bits specify the tributary FIFO Minimum Depth, i.e. the depth that must be reached before the FIFO reader starts to take data from the FIFO. R/W R/W R/W R/W Type Function Unused Unused Unused Unused MIN_DEP[3] MIN_DEP[2] MIN_DEP[1] MIN_DEP[0] Default X X X X 0 1 1 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 397H: EXSBI FIFO Thresholds Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIN_THR[3:0]: The MIN_THR[3:0] bits specify the tributary FIFO minimum threshold, i.e. the FIFO depth below which the serial data stream to the LIU octant is slowed down (when CLK_MODE[1:0] = "00" in the EXSBI Tributary Control Register for the octant). MAX_THR[3:0]: The MAX_THR[3:0] bits specify the tributary FIFO maximum threshold, i.e. the FIFO depth above which the serial data stream to the LIU octant is sped up (when CLK_MODE[1:0] = "00" in the EXSBI Tributary Control Register for the octant). Type R/W R/W R/W R/W R/W R/W R/W R/W Function MIN_THR[3] MIN_THR[2] MIN_THR[1] MIN_THR[0] MAX_THR[3] MAX_THR[2] MAX_THR[1] MAX_THR[0] Default 0 0 1 0 1 1 0 1
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102
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 398H: EXSBI Link Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LINK_ENBL[8] LINK_ENBL[7] LINK_ENBL[6] LINK_ENBL[5] LINK_ENBL[4] LINK_ENBL[3] LINK_ENBL[2] LINK_ENBL[1] Default 0 0 0 0 0 0 0 0
LINK_ENBL[8:1]: The LINK_ENBL[8:1] bits enable the operation of the corresponding LIU octant data streams. When LINK_ENBL is `1' for a stream, the EXSBI8 will take data from an SBI tributary and transmit that data to the LIU octant. The tributary to octant mapping is determined by the Octant to Tributary Mapping Registers and APAGE.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 399H: EXSBI Link Enable Busy Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BUSY: A write to the EXSBI Link Enable Register sets BUSY to `1'. BUSY is cleared to `0' approximately three REFCLK cycles later after the register contents have been synchronized to REFCLK. The user must check that BUSY is `0' before writing to the EXSBI Link Enable Register. Following a reset, BUSY will be `1' until startup circuitry has finished automatically initializing certain RAMs within EXSBI. R Type Function Unused Unused Unused Unused Unused Unused Unused BUSY Default X X X X X X X 0
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104
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 3A0H - 3A7H: EXSBI Tributary Control #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused CLK_MODE[1] CLK_MODE[0] Reserved TRIB_TYP[1] TRIB_TYP[0] Reserved Unused Default X 0 0 0 1 0 0 X
A tributary control register should only be written when the associated LINK_ENBL bit is `0'. Reserved: The reserved bits must be set to 0 for correct operation of the OCTLIU device. TRIB_TYP[1:0]: The TRIB_TYP[1:0] field specifies the characteristics of the SBI tributary, as shown in Table 9. Table 9 - EXSBI Tributary Characteristics TRIB_TYP[1:0] 00 01 10 11 Description Reserved. Framed (EFP indicates frame alignment). Unframed (EFP remains low). Reserved.
The TRIB_TYP[1:0] bits must be set to "10" whenever the LIUs are enabled (SBI2CLK tied low). CLK_MODE[1:0]: The CLK_MODE[1:0] field selects one of three different methods whereby the frequency of the serial data stream output to the LIU octant is determined, as shown in Table 10.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 10 - EXSBI Clock Generation Options CLK_MODE[1:0] 00 Description Speed up and slow down the output serial clock depending on the FIFO fill level and the thresholds specified in the EXSBI Thresholds Register. Speed up and slow down the output serial clock depending on the `ClkRate' field of the tributary's Link Rate Octet on the SBI bus. Speed up and slow down the output serial clock depending on the `Phase' field of the tributary's Link Rate Octet on the SBI bus. Reserved.
01
10
11
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 3A8H - 3AFH: EXSBI Page A Octant to Tributary Mapping #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] Default X 0 0 0 0 0 0 0
SPE[1:0] and TRIB[4:0]: The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI tributary mapping when APAGE is set to 0. The input of the octant corresponding to the register (1-8) is sourced from the SPE and tributary specified by the value of SPE[1:0] and TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1 to 28 in T1 mode and from 1 to 21 in E1 mode.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 3B0H to 3B7H: EXSBI Page B Octant to Tributary Mapping #1 - #8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] Default X 0 0 0 0 0 0 0
SPE[1:0] and TRIB[4:0]: The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI tributary mapping when APAGE is set to 1. The input of the octant corresponding to the register (1-8) is sourced from the SPE and tributary specified by the value of SPE[1:0] and TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1 to 28 in T1 mode and from 1 to 21 in E1 mode. Note: The mapping of more than one tributary to the same LIU octant data stream or more than one LIU octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all LIU octants and tributaries are uniquely mapped when using multiple OCTLIU's on the same SBI bus. Failure to do so will result in bus contention.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H: ELST Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IR: The IR bit selects the data rate to be used at the input of the Elastic Store. This bit should be set to 0 for T1/J1 operation and to 1 for E1 operation. OR: The OR bit selects the data rate to be used at the output of the Elastic Store. This bit should be set to 0 for T1/J1 operation and to 1 for E1 operation. R/W R/W Type R/W Function Reserved Unused Unused Unused Unused Unused IR OR Default 0 X X X X X 1 1
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H: ELST Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: The SLIPE bit enables an interrupt to be generated on the microprocessor INTB pin when a frame slip occurs in the Elastic Store. When SLIPE is set to logic 1, interrupt generation is enabled. When SLIPE is set to logic 0, interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last frame slip. When SLIPD is set to logic 1, the last frame slip was a write slip (frame skipped due to buffer becoming full). When SLIPE is set to logic 0, the last frame slip was a read slip (frame repeated due to buffer becoming empty). SLIPI: The SLIPI bit indicates the occurrence of a frame slip when set to 1. SLIPI is cleared to 0 when this register is read. Note that the SLIPI interrupt indication operates regardless of whether interrupts are enabled or disabled. R/W R R Type Function Unused Unused Unused Unused Unused SLIPEE SLIPD SLIPI Default X X X X X 0 X X
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: T1 PDVD Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R/W Type Function Unused Unused Unused PDV Z16DI PDVI Z16DE PDVE Default X X X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether interrupts are enabled or disabled. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled. PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H: T1 XPDE Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R R R R R/W R/W Function STUFE STUFF STUFI PDV Z16DI PDVI Z16DE PDVE Default 0 0 X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. STUFE: The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB. When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff. When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB. STUFF: The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse density rule. Bit stuffing is performed in such a way that the resulting data stream no longer violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF is a logic 0, PCM data passes through XPDE unaltered. STUFI: The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff occurred to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating that the stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this register is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register is read. PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
this bit may not return a logic 1 even though a pulse density violation has occurred. When the XPDE is enabled for pulse stuffing, PDV remains logic 0. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether the corresponding interrupt enables are enabled or disabled. When STUFF is set to logic 1, the PDVI and Z16DI bits are forced to logic 0. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled. PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist (if STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: T1 XIBC Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type R/W R/W Function EN Reserved Unused Unused Unused Unused CL1 CL0 Default 0 0 X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. EN: The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit position enables transmission of inband codes; a logic 0 in the EN bit position disables inband code transmission. Reserved: The reserved bit must be set to 0 for correct operation of the OCTLIU device. CL1, CL0: The bit positions CL1 and CL0 of this register indicate the length of the inband loopback code sequence, as follows: Table 11 - Transmit In-band Code Length CL1 0 0 1 1 CL0 0 1 0 1 Code Length 5 6 7 8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e., a 3-bit code would use the 6-bit code length setting).
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: T1 XIBC Loopback Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 Default X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register contains the inband loopback code pattern to be transmitted. The code is transmitted most significant bit (IBC7) first, followed by IBC6 and so on. The code, regardless of the length, must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (i.e., the 3-bit code `011' would be written as the 6-bit code `011011'). When the OCTLIU is reset, the contents of this register are not affected.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H: RJAT Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: The UNDI bit is asserted when an attempt is made to read data from the receive FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the receive FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0. R R Type Function Unused Unused Unused Unused Unused Unused OVRI UNDI Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H: RJAT Reference Clock Divisor (N1) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] Default 0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH: RJAT Output Clock Divisor (N2) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0] Default 0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock, RCLK[n], and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH. Recommendations In general, the relationship N1 = N2 must always be true in order for the PLL to operate correctly. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the recommended values are N1 = N2 = FFH.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH: RJAT Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST: Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset. LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during R/W R/W R/W R/W R/W Type Function Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT Default X X X 0 0 0 0 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: TJAT Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0. R R Type Function Unused Unused Unused Unused Unused Unused OVRI UNDI Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: TJAT Reference Clock Divisor (N1) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] Default 0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the reference clock (as selected by the PLLREF1 and PLLREF0 bits of the Transmit Line Interface Timing Options register) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH: TJAT Output Clock Divisor (N2) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0] Default 0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH. Recommendations In general, the relationship N1 = N2 must always be true in order for the PLL to operate correctly. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the recommended values are N1 = N2 = FFH.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: TJAT Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST: Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset. LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during R/W R/W R/W R/W R/W Type Function Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT Default X X X 0 0 0 0 1
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
125
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: IBCD Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W Function Reserved Unused Unused Unused DSEL1 DSEL0 ASEL1 ASEL0 Default 0 X X X 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register provides the selection of the Activate and De-activate loopback code lengths (from 3 bits to 8 bits) as follows: Table 12 - Loopback Code Configurations DEACTIVATE Code DSEL1 0 0 1 1 Note: 3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and by programming two repetitions of the code sequence. The Reserved bit is used for production test purposes only. The Reserved bit must be logic 0 for normal operation. DSEL0 0 1 0 1 ACTIVATE Code ASEL1 0 0 1 1 ASEL0 0 1 0 1 CODE LENGTH 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: IBCD Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R/W R/W R R R R Function LBACP LBDCP LBAE LBDE LBAI LBDI LBA LBD Default X X 0 0 X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. LBACP, LBDCP: The LBACP and LBDCP bits indicate when the corresponding loopback code is present during a 39.8 ms interval. LBAE: The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA) detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is set to logic 1, any change in the state of the LBA detect indication generates an interrupt. When LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state. LBDE: The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate (LBD) detect indication to generate an interrupt on the microprocessor INTB pin. When LBDE is set to logic 1, any change in the state of the LBD detect indication generates an interrupt. When LBDE is set to logic 0, no interrupt is generated by changes in the LBD detect state. LBAI, LBDI: The LBAI and LBDI bits indicate which of the two expected loopback codes generated the interrupt when their state changed. A logic 1 in these bit positions indicates that a state change in that code has generated an interrupt; a logic 0 in these bit positions indicates that no state change has occurred. After the Enable/Status Register has been read, the LBAI and LBDI bits are set to logic 0. LBA, LBD: The LBA and LBD bits indicate the current state of the corresponding loopback code detect indication. A logic 1 in these bit positions indicates the presence of that code has been detected; a logic 0 in these bit positions indicates the absence of that code.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: IBCD Activate Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0 Default 0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Activate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 00001, the first 8 bits of two repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7 corresponds to the first code bit received.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: IBCD Deactivate Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function DACT7 DACT6 DACT5 DACT4 DACT3 DACT2 DACT1 DACT0 Default 0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Deactivate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 001, the first 8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that bit DACT7 corresponds to the first code bit received.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: CDRC Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: These bits must be a logic 0 for correct operation. O162: If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit (O162) allows selection between two line code violation definitions: If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not part of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per Recommendation O.162. The O162 bit has no effect in T1 mode. ALGSEL: The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL for clock and data recovery. The choice of algorithm determines the high frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1, the CDRC jitter tolerance is increased to approach 0.5 Uipp for jitter frequencies above 20 kHz. When ALGSEL is set to logic 0, the jitter tolerance is increased for frequencies below 20 kHz (i.e. the tolerance is improved by 20% over that of ALGSEL=1 at these frequencies), but the tolerance approaches 0.4 Uipp at the higher frequencies. AMI: The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A logic 1 selects AMI line coding by disabling HDB3 decoding in E1 mode and B8ZS in T1 mode. In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an HDB3 Type R/W R/W R/W R/W R/W R/W R/W R/W Function AMI LOS[1] LOS[0] Reserved Reserved ALGSEL O162 Reserved Default 0 0 0 0 0 0 0 0
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
signature with four zeros. In T1 mode, a logic 0 selects B8ZS line decoding which entails substituting an B8ZS signature with eight zeros. LOS[1:0]: The loss of signal threshold is set by the operating mode and the state of the AMI, LOS[1] and LOS[0] bits: Table 13 - Loss of Signal Thresholds Mode E1 T1 X X X X AMI 0 0 1 X X X LOS[1] 0 0 0 0 1 1 LOS[0] 0 0 0 1 0 1 Threshold (PCM periods) 10 15 15 31 63 175
When the number of consecutive zeros on the incoming PCM line exceeds the programmed threshold, the LOSV status bit is set. For example, if the threshold is set to 10, the 11th zero causes the LOSV bit to be set.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: CDRC Interrupt Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W Function LCVE LOSE LCSDE ZNDE Unused Unused Unused Unused Default 0 0 0 0 X X X X
The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are interrupt enables to select which of the status events (Line Code Violation , Loss Of Signal, HDB3 signature, B8ZS signature or N Zeros), either singly or in combination, are enabled to generate an interrupt on the microprocessor INTB pin when they are detected. A logic 1 bit in the corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0 bit in the corresponding bit position disables that signal from generating an interrupt.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: CDRC Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type R R R R Function LCVI LOSI LCSDI ZNDI Unused Unused Unused LOSV Default X X X X X X X X
The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status events have occurred since the last time this register was read. A logic 1 in any of these bit positions indicates that the corresponding event was detected. Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register. LOSV: The LOSV bit reflects the status of the LOS alarm. ZNDI: The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI coded signal. LCSDI: The line code signature detection interrupt (LCSDI) indicates that a valid line code signature has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the previous impulse is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3 signature is defined as a bipolar violation preceded by two zeros. This bit can be used to detect an HDB3 coded signal in E1 mode and B8ZS coded signal in T1. LOSI: The LOSI bit is set to a logic 1 when the LOSV bit changes state. LCVI: The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred in contradiction to the defined line code (AMI, B8ZS or HDB3).
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H: CDRC Alternate Loss of Signal Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type R/W R Function ALTLOSE ALTLOSI Unused Unused Unused Unused Unused ALTLOSV Default 0 X X X X X X X
The alternate loss of signal status provides a more stringent criteria for the deassertion of the alarm than the LOS indication in the CDRC Interrupt Status register. ALTLOSE: If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOSV status bit changes state. ALTLOSI: The ALTLOSI bit is set high when the ALTLOSV status bit changes state. It is cleared when this register is read. ALTLOSV: The ALTLOSV bit is asserted upon the absence of marks for the threshold of bit periods specified by the LOS[1:0] register bits. The ALTLOSV bit is deasserted only after pulse density requirements have been met. In T1 mode, there must be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOSV is deasserted only after 255 bit periods during which no sequence of four zeros has been received.
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134
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: PMON Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R Type Function Unused Unused Unused Unused Unused INTE XFER Unused Default X X X X X 0 0 X
This register contains status information indicating when counter data has been transferred into the holding registers and indicating whether the holding registers have been overrun. INTE: The INTE bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE position enables the generation of an interrupt via the INTB output; a logic 0 bit in the INTE position disables the generation of an interrupt. XFER: The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations or the Octant PMON Update register, was received and a transfer of the counter values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is cleared (acknowledged) by reading this register.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH: PMON LCV Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0] Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH: PMON LCV Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCV[12:0]: The LCV[12:0] bits indicate the number of LCV error events that occurred during the previous accumulation interval. An LCV event is defined as the occurrence of a Bipolar Violation or Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the Receive Line Interface Configuration #1 register. The LCV count registers for a octant are updated by writing to the PMON LCV Count (LSB) register. A write to this location loads count data located in the PMON into the internal holding registers. Alternatively, the LCV count registers for the octant are updated by writing to the Line Interface Interrupt Source #1 / PMON Update register. The data contained in the holding registers can then be subsequently read by microprocessor accesses into the PMON count register address space. The latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. The PMON is loaded with new count data within 3.5 recovered clock periods of the triggering register write. With nominal line rates, the PMON registers should not be polled until 2.3 sec have elapsed from the triggering register write. When the OCTLIU is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed. R R R R R Type Function Unused Unused Unused LCV[12] LCV[11] LCV[10] LCV[9] LCV[8] Default X X X X X X X X
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137
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRBS Generator/Checker Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 QRSS: The quasi-random signal source (QRSS) bit enables the zero suppression feature required when generating a QRSS sequence. When QRSS is a logic 1, a one is forced in the generated PRBS stream when the following 14 bit positions are all zeros. When QRSS is a logic 0, the zero suppression feature is disabled. Note that in order to generate the AT&T TR 62411 QRSS sequence, or the 2 -1 sequence as specified in ITU-T O.151, the PATSEL[1:0] field in the PRBS Pattern Select Register must be set to "01" and QRSS set to 1. TINV: The TINV bit controls the logical inversion of the generated data stream. When TINV is a logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted. RINV: The RINV bit controls the logical inversion of the received stream before processing. When RINV is a logic 1, the received data is inverted before being processed by the pattern detector. When RINV is a logic 0, the data is not inverted AUTOSYNC: The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The automatic resynchronization is activated when 10 or more bit errors are detected in a fixed 48-bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is accomplished using the MANSYNC bit.
20
Type
Function Unused Unused
Default X X 0 X 0 0 1 0
R/W
QRSS Unused
R/W R/W R/W R/W
TINV RINV AUTOSYNC MANSYNC
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
MANSYNC: The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRBS Checker Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYNCE: The SYNCE bit enables the generation of an interrupt when the PRBS checker changes synchronization state. When SYNCE is set to logic 1, the interrupt is enabled. BEE: The BEE bit enables the generation of an interrupt when a bit error is detected in the receive data. When BEE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. SYNCV: The SYNCV bit indicates the synchronization state of the PRBS checker. When SYNCV is a logic 1 the PRBS checker is synchronized (the PRBS checker has observed at least 32 consecutive error free bit periods). When SYNCV is a logic 0, the PRBS checker is out of sync (the PRBS checker has detected 6 or more bit errors in a 64 bit period window). SYNCI: The SYNCI bit indicates that the detector has changed synchronization state since the last time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost synchronization at least once. SYNCI is set to logic 0 when this register is read. Type R/W R/W R/W R R R R Function SYNCE BEE XFERE SYNCV SYNCI BEI XFERI Unused Default 0 0 0 X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
BEI: The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of the error count has occurred. A logic 1 in this bit position indicates that the error counter holding registers has been updated. This update is initiated by writing to one of the PRBS Error Count register locations, or by writing to the Line Interface Interrupt Source #1 / PMON Update register. XFERI is set to logic 0 when this register is read.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRBS Pattern Select Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PATSEL[1:0]: PATSEL[1:0] determines which of the three PRBS patterns are generated and checked for errors. PATSEL[1:0] 00 01 10 11 Pattern 2 -1 2 -1 2 -1 Reserved
11 20 15
Type
Function Unused Unused Unused Unused Unused Unused
Default X X X X X X 0 0
R/W R/W
PATSEL[1] PATSEL[0]
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRBS Error Count #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ERRCNT[7] ERRCNT[6] ERRCNT[5] ERRCNT[4] ERRCNT[3] ERRCNT[2] ERRCNT[1] ERRCNT[0] Default X X X X X X X X
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143
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H: PRBS Error Count #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ERRCNT[15] ERRCNT[14] ERRCNT[13] ERRCNT[12] ERRCNT[11] ERRCNT[10] ERRCNT[9] ERRCNT[8] Default X X X X X X X X
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144
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H: PRBS Error Count #3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERRCNT[23:0]: ERRCNT[23:0] contain the error counter holding register. The value in this register represents the number of bit errors that have been accumulated since the last accumulation 24 interval, up to a maximum (saturation) value of 2 -1. Note that bit errors are not accumulated while the pattern detector is out of sync. The Error Count registers for each individual PRBS generator/checker are updated by writing to any one of the Error count registers. Alternatively, the Error Count registers are updated with all other octant counter registers by writing to the Line Interface Interrupt Source #1 / PMON Update register. Type R R R R R R R R Function ERRCNT[23] ERRCNT[22] ERRCNT[21] ERRCNT[20] ERRCNT[19] ERRCNT[18] ERRCNT[17] ERRCNT[16] Default X X X X X X X X
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: XLPG Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGHZ: The HIGHZ bit controls tristating of the TXTIP[x] and TXRING[x] outputs. When the HIGHZ bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to a logic 1, the outputs are put into high impedance. Setting HIGHZ to logic 1 has the same effect as setting SCALE[4:0] to 00H. ARST: The Analogue Reset bit (ARST) resets the analogue portion of the XLPG (without affecting the digital portion) when set to logic 1. INITRAM: The Waveform Storage RAM initialisation bit (INITRAM) causes the XPLG waveform storage RAM to be initialised to 12 standard waveform patterns when set to logic 1. This bit remains at logic 1 while the initialisation is in progress and is cleared to logic 0 when the initialisation has completed. The 12 waveform patterns to which the RAM is initialised are listed in Table 20 thru Table 29, Table 37 and Table 38. OVRFLW: The overflow detection value bit (OVRFLW) indicates the presence or absence of an overflow condition in the waveform computation pipeline. An overflow occurs when the sum of the five unit interval (UI) samples exceeds the maximum D/A value. The XLPG detects overflows and saturates the output value to minimize their impact on the output signal. Overflows can easily be eliminated by changing the waveform programming. This status bit is set to logic 1 when an overflow condition is detected and it is reset to logic 0 only when this register is read. It is suggested that this register be read twice after the programming of a new waveform and transmission of data to ensure the maximum output amplitude is never exceeded. R/W R R/W R/W R/W Type R/W R/W Function HIGHZ ARST Unused INITRAM OVRFLW Reserved Reserved Reserved Default 1 0 X 0 X 0 0 1
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146
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Reserved: The Reserved bits must remain in their default state for correct operation.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: XLPG Pulse Waveform Scale Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCALE[4:0]: The SCALE[4:0] bits specify a scaling factor to be applied to the amplitude of the D/A output waveform. Each of the 12 waveforms stored in the XLPG's pulse template RAM may have a different scaling factor. When a particular waveform is selected for use (by the PT_SEL[3:0] register bits or LENx[2:0] inputs), the scaling factor corresponding to that waveform is chosen automatically. When this register is written to, the value of SCALE[4:0] is stored in one of 12 storage locations indexed by the WAVEFORM[3:0] bits of the Pulse Waveform Storage Write Address #2 register. Thus to set up scaling factors for more than one waveform, this register should be written to a number of times, with WAVEFORM[3:0] set to the different waveform numbers, as appropriate. The SCALE[4:0] bits scale the maximum output amplitude by increments of 11.14 mA. A value of 0 (00H) tristates the output while the maximum value of 21 (15H) sets the full scale current to 234 mA. Table 14 - Transmit Output Amplitude SCALE[4:0] 00000 00001-10100 10101 10110-11111 Decimal Equiv. 0 1-20 21 >21 Output Amplitude 0 mA (tristate) Increments of 11.14 mA for each scale step 234 mA total Reserved R/W R/W R/W R/W R/W Type Function Unused Unused Unused SCALE[4] SCALE[3] SCALE[2] SCALE[1] SCALE[0] Default X X X 0 0 0 0 0
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148
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH: XLPG Pulse Waveform Storage Write Address #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UI[2:0]: The pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. The unit interval selector (UI[2:0]) specifies the unit interval portion of the address. There are 5 unit intervals, numbered from 0 to 4. UI[2:0] can take the values 0H, 1H, 2H, 3H and 4H. The values 5H, 6H and 7H are undefined. SAMPLE[4:0]: The pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. The sample selector (SAMPLE[4:0]) specifies the sample portion of the address. There are 24 samples, numbered from 0 to 23. SAMPLE[4:0] can thus have any value from 00H to 17H. The values from 18H to 1FH are undefined. Note - The Pulse Waveform Storage Write Indirect Address Registers #1 and #2 must be written to before the Pulse Waveform Storage Data register. In addition, waveform samples must be written in groups of 5. Within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. See the Operation section for more details on setting up waveform templates. Type R/W R/W R/W R/W R/W R/W R/W R/W Function SAMPLE[4] SAMPLE[3] SAMPLE[2] SAMPLE[1] SAMPLE[0] UI[2] UI[1] UI[0] Default 0 0 0 0 0 0 0 0
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH: XLPG Pulse Waveform Storage Write Address #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused WAVEFORM[3] WAVEFORM[2] WAVEFORM[1] WAVEFORM[0] Default X X X X 0 0 0 0
WAVEFORM[3:0]: The pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. The waveform number (WAVEFORM[3:0]) specifies the waveform portion of the address. There are 12 waveforms, numbered from 0 to 11. WAVEFORM[3:0] can thus have any value from 0H to BH. The values from CH to FH are undefined. Note - The Pulse Waveform Storage Write Indirect Address Registers #1 and #2 must be written to before the Pulse Waveform Storage Data register. In addition, waveform samples must be written in groups of 5. Within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. See the Operation section for more details on setting up waveform templates.
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150
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH: XLPG Pulse Waveform Storage Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDAT[6:0]: The WDAT[6:0] bits contain the write data to be stored in the pulse template RAM, as addressed by the UI[2:0], SAMPLE[4:0] and WAVEFORM[3:0] bits in the Pulse Waveform Storage Write Address registers. When writing to the RAM, the address must first be written to the Pulse Waveform Storage Write Address registers. Writing to the Pulse Waveform Storage Data register triggers the transfer of data. If the UI portion of the address is 0, 1, 2 or 3, WDAT[6:0] are transferred to internal holding registers. If the UI portion of the address is 4, WDAT[6:0] are combined with the contents of the holding registers to form a 35-bit long word which is then stored in the pulse template RAM. Waveform samples must therefore be written in groups of 5 and within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. WDAT[6:0] are coded in signed magnitude representation. WDAT[6] is the sign bit, WDAT[5] is the most significant data bit and WDAT[0] is the least significant data bit. The data values thus can range from -63 to +63. See the Operation section for more details on setting up custom waveform templates. W W W W W W W Type Function Unused WDAT[6] WDAT[5] WDAT[4] WDAT[3] WDAT[2] WDAT[1] WDAT[0] Default X X X X X X X X
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151
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H: RLPS Configuration and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: The Reserved bit must be logic 1 for correct operation. DB_VALID: The DB_VALID bit indicates if the adaptive equalizer has stabilized. This bit is set if the equalisation has not changed by more than 2dB (or +/-8 steps in the RAM table) in more than a selectable count of sampling periods. IDDQ_EN: The IDDQ enable bit (IDDQ_EN) is used to configure the analogue receiver for IDDQ tests. When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1 register (004H) is a logic 1, the digital outputs of the analogue receiver are pulled to ground. SQUELCHE: The output data squelch enable (SQUELCHE) allows control of data squelching in response to an analogue loss of signal (ALOS) condition. When SQUELCHE is set to logic 1, the recovered data are forced to all-zeros if the ALOSV register bit is asserted. When SQUELCHE is set to logic 0, squelching is disabled. ALOSE: The loss of signal interrupt enable bit (ALOSE) enables the generation of device level interrupt on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is generated by asserting INTB low when there is a change of the ALOSV status. When ALOSE is set to logic 0, interrupts are disabled. ALOSV: The loss of signal value bit (ALOSV) indicates the loss of signal alarm state. R/W Type R R R/W R/W R/W R Function ALOSI ALOSV ALOSE SQUELCHE IDDQ_EN DB_VALID Unused Reserved Default X X 0 0 0 X X 1
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152
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
ALOSI: The loss of signal interrupt bit (ALOSI) is a logic 1 whenever the Loss of Signal indicator state (ALOSV) changes. This bit is cleared when this register is read.
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153
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H: RLPS ALOS Detection/Clearance Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CLR_THR[3] CLR_THR[2] CLR_THR[1] CLR_THR[0] DET_THR[3] DET_THR[2] DET_THR[1] DET_THR[0] Default 0 0 0 0 0 0 0 0
Table 15 - ALOS Detection/Clearance Thresholds THR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Signal level (dB) 8 9 10 11 20 21 22 30 31 32 33 34 35 36 37 38 G.775 (E1) Detection (if >= 35dB) I.431 (T1) Detection (if > 30dB) and Clearance I.431 (E1) ETSI 300 233 Detection (if > 20dB) and Clearance G.775(E1) Clearance (if <= 9dB) Applicable Standard Detection/Clearance
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154
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DET_THR[3:0]: DET_THR[3:0] references one of the threshold settings in Table 15 as the ALOS detection criteria. If the equalised cable loss is greater than or equal to the threshold for N consecutive pulse periods, where N = 16 * DET_PER stored in the RLPS ALOS Detection Period Register, ALOS is declared and interrupt set. CLR_THR[3:0]: CLR_THR[3:0] references one of the threshold settings listed in Table 15 as the ALOS clearance criteria. ALOS is cleared when the equalised cable loss is less than the threshold for N consecutive pulse intervals, where N = 16 * CLR_PER stored in the RLPS ALOS Clearance Period Register.
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155
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H: RLPS ALOS Detection Period Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DET_PER[7:0]: This register specifies the time duration that the equalised cable loss has to remain above the detection threshold in order for the ALOS to be issued. This duration is equal to DET_PER * 16 number of pulse intervals, the resulting range is from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS detection standards/recommendations. Type R/W R/W R/W R/W R/W R/W R/W R/W Function DET_PER[7] DET_PER[6] DET_PER[5] DET_PER[4] DET_PER[3] DET_PER[2] DET_PER[1] DET_PER[0] Default 0 0 0 0 0 0 0 1
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156
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H: RLPS ALOS Clearance Period Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLR_PER[7:0]: This register specifies the time duration that the equalised cable loss has to remain below the clearance threshold in order for the ALOS to be cleared. This duration is equal to CLR_PER * 16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS clearance standards/ recommendations. Type R/W R/W R/W R/W R/W R/W R/W R/W Function CLR_PER[7] CLR_PER[6] CLR_PER[5] CLR_PER[4] CLR_PER[3] CLR_PER[2] CLR_PER[1] CLR_PER[0] Default 0 0 0 0 0 0 0 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H: RLPS Equalization Indirect Address Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EQ_ADDR [7:0]: Writing to this register initiates an internal uP access request cycle to the RAM. Depending on the setting of the RWB bit inside the RLPS Equalization Read/WriteB Select, a read or a write will be performed. During a write cycle, the indirect data bits located in the RLPS Equalization Indirect Data registers are written into the RAM. For a read request, the content of the addressed RAM location is written into the RLPS Equalization Indirect Data registers. This register should be the last register to be written for a uP access. A waiting period of at least three line rate cycles is needed from when this register is written until the next indirect data bits are written into any of the respective octant's RLPS Equalization Indirect Data registers. Type R/W R/W R/W R/W R/W R/W R/W R/W Function EQ_ADDR[7] EQ_ADDR[6] EQ_ADDR[5] EQ_ADDR[4] EQ_ADDR[3] EQ_ADDR[2] EQ_ADDR[1] EQ_ADDR[0] Default 0 0 0 0 0 0 0 0
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158
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H: RLPS Equalization Read/WriteB Select Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RWB: This bit selects the operation to be performed on the RAM: when RWB is `1', a read from the equalization RAM is requested; when RWB is set to `0', a write to the RAM is desired. Type R/W Function RWB Unused Unused Unused Unused Unused Unused Unused Default 1 X X X X X X X
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159
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H: RLPS Equalizer Loop Status and Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOCATION[7:0]: Writing to this register overwrites a counter which serves as the read address to the equalization RAM. Reading this register returns the current value of the counter and thus an indication of the cable loss as estimated by the equaliser. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LOCATION[7] LOCATION[6] LOCATION[5] LOCATION[4] LOCATION[3] LOCATION[2] LOCATION[1] LOCATION[0] Default 0 0 0 0 0 0 0 0
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160
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H: RLPS Equalizer Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EQ_FREQ[2:0]: The EQ_FREQ[2:0] field selects the frequency of the EQ feedback loop as indicated by Table 16. Table 16 - Equalization Feedback Frequencies EQ_FREQ[2:0] EQ Feedback Frequency T1 mode 000 001 010 011 100 101 110 111 EQ_EN: The EQ_EN bit enables operation of the equaliser when set to logic 1. This bit defaults to logic 0 after reset and must be set to logic 1, but only after the equalisation RAM has been initialised. Reserved: This bit must be programmed to logic 0 for normal operation. 24.125 kHz 12.063 kHz 8.0417 kHz 6.0313 kHz 4.8250 kHz 4.0208 kHz 3.4464 kHz 3.0156 kHz E1 mode 32.000 kHz 16.000 kHz 10.667 kHz 8.0000 kHz 6.40 kHz 5.333 kHz 4.5714 kHz 4.0 kHz How Frequency Derived Line rate / 64 Line rate / 128 Line rate / 192 Line rate / 256 Line rate / 320 Line rate / 384 Line rate / 448 Line rate / 512 R/W R/W R/W R/W R/W Type R/W R/W Function VALID_PER[1] VALID_PER[0] Unused Reserved EQ_EN EQ_FREQ[2] EQ_FREQ[1] EQ_FREQ[0] Default 0 0 X 0 0 0 1 1
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
VALID_PER[1:0]: The VALID_PER[1:0] bits select the length of time that the dB loss counter must be stable before DB_VALID is asserted. The duration is measured in number of periods of the EQ feedback loop (specified by the EQ_FREQ bits) as indicated by Table 17. Table 17 - Valid Period VALID_PER 00 01 10 11 Number of periods 32 64 128 256
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H: RLPS Equalization Indirect Data Bit 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EQ_DATA[31] EQ_DATA[30] EQ_DATA[29] EQ_DATA[28] EQ_DATA[27] EQ_DATA[26] EQ_DATA[25] EQ_DATA[24] Default 0 0 0 0 0 0 0 0
EQ_DATA[31:24]: This register consists of 2-parts: read-only and write-only. Writing this register affects the most significant byte of the input-data to the equalization RAM. Reading it returns the MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H: RLPS Equalization Indirect Data Bit 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EQ_DATA[23] EQ_DATA[22] EQ_DATA[21] EQ_DATA[20] EQ_DATA[19] EQ_DATA[18] EQ_DATA[17] EQ_DATA[16] Default 0 0 0 0 0 0 0 0
EQ_DATA[23:16]: This register consists of 2-parts: read-only and write-only. Writing this register affects the second most significant byte of the input-data to the equalization RAM. Reading it returns the second MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH: RLPS Equalization Indirect Data Bit 7 6 5 4 3 2 1 0 EQ_DATA[15:8]: This register consists of 2-parts: read-only and write-only. Writing this register affects the second least significant byte of the input-data to the equalization RAM. Reading it returns the corresponding bits of the RAM location indexed by the RLPS Equalization Indirect Address register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function EQ_DATA[15] EQ_DATA[14] EQ_DATA[13] EQ_DATA[12] EQ_DATA[11] EQ_DATA[10] EQ_DATA[9] EQ_DATA[8] Default 0 0 0 0 0 0 0 0
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165
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH: RLPS Equalization Indirect Data Bit 7 6 5 4 3 2 1 0 EQ_DATA[7:0]: This register consists of 2-parts: read-only and write-only. Writing this register affects the least significant byte of the input-data to the equalization RAM. Reading it returns the LSB of the RAM location indexed by the RLPS Equalization Indirect Address register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function EQ_DATA[7] EQ_DATA[6] EQ_DATA[5] EQ_DATA[4] EQ_DATA[3] EQ_DATA[2] EQ_DATA[1] EQ_DATA[0] Default 0 0 0 0 0 0 0 0
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166
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH: RLPS Equalizer Voltage Thresholds #1 Bit 7 6 5 4 3 2 1 0 VREF[5:0]: The VREF[5:0] bits set the voltage thresholds of amplitude comparators within the RLPS. For T1 mode, the VREF[5:0] bits must be programmed to 35H (`b110101). For E1 mode, the VREF[5:0] bits must be programmed to 35H (`b110101). R/W R/W R/W R/W R/W R/W Type Function unused unused VREF[5] VREF[4] VREF[3] VREF[2] VREF[1] VREF[0] Default X X 1 1 0 1 0 1
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167
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH: RLPS Equalizer Voltage Thresholds #2 Bit 7 6 5 4 3 2 1 0 CUTOFF[1:0]: The CUTOFF[1:0] bits control cutoff frequencies of the bandlimiter and equaliser within the RLPS. For T1 mode, the CUTOFF[1:0] bits must be programmed to 3H (`b11). For E1 mode, the CUTOFF[1:0] bits must be programmed to 0H (`b00). VREF[8:6]: The VREF[8:6] bits set the voltage thresholds of amplitude comparators within the RLPS. For T1 mode, the VREF[8:6] bits must be programmed to 3H (`b011). For E1 mode, the VREF[8:6] bits must be programmed to 3H (`b011). R/W R/W R/W Type R/W R/W Function CUTOFF[1] CUTOFF[0] Unused Unused Unused VREF[8] VREF[7] VREF[6] Default 0 0 X X X 0 1 1
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168
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
11
TEST FEATURES DESCRIPTION Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing.
11.1 JTAG Test Port The OCTLIU JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Identification Register Length - 32 bits Version number - 0H for Rev A. Part Number - 4318H Manufacturer's identification code - 0CDH Device identification - 043180CDH for Rev. A Boundary Scan Register Length - 131
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169
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 18 - Boundary Scan Register Pin/Enable Cell Type Device ID Scan Register Bit
130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 -
Pin/Enable
Cell Type Scan Register Bit
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL -
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] TCLK[1] TDP[1] TDN[1] TCLK[2] TDP[2] TDN[2] TCLK[3] TDP[3] TDN[3] TCLK[4] TDP[4] TDN[4] OEB_RCLK[1] RCLK[1] OEB_RDP[1] RDP[1] OEB_RDN[1] RDN[1] OEB_RCLK[2] RCLK[2] OEB_RDP[2] RDP[2] OEB_RDN[2] RDN[2] OEB_RCLK[3] RCLK[3]
RDN[8] OEB_RDP[8] RDP[8] OEB_RCLK[8] RCLK[8] TDN[5] TDP[5] TCLK[5] TDN[6] TDP[6] TCLK[6] TDN[7] TDP[7] TCLK[7] TDN[8] TDP[8] TCLK[8] HW_ONLY SRCASC OEB_SREN SREN OEB_SRCLK SRCLK OEB_SRDI SRDI SRDO OEB_SRCEN SRCEN OEB_SRCCLK SRCCLK OEB_SRCDO SRCDO SRCODE OEB_LOS_L1 LOS_L1 OEB_LOS LOS
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
OEB_RDP[3] RDP[3] OEB_RDN[3] RDN[3] OEB_RCLK[4] RCLK[4] OEB_RDP[4] RDP[4] OEB_RDN[4] RDN[4] OEB_RDN[5] RDN[5] OEB_RDP[5] RDP[5] OEB_RCLK[5] RCLK[5] OEB_RDN[6] RDN[6] OEB_RDP[6] RDP[6] OEB_RCLK[6] RCLK[6] OEB_RDN[7] RDN[7] OEB_RDP[7] RDP[7] OEB_RCLK[7] RCLK[7] OEB_RDN[8]
93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OEB_RSYNC RSYNC RES[1] RSTB XCLK SBI_EN OEB_D[7] D[7] OEB_D[6] D[6] OEB_D[5] D[5] OEB_D[4] D[4] OEB_D[3] D[3] OEB_D[2] D[2] OEB_D[1] D[1] OEB_D[0] D[0] OEB_INTB INTB CSB RDB WRB ALE
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
Notes: 1. OEB signals, when set low, will set the corresponding bidirectional signal to an output. 2. OEB signals, when set high, will set the corresponding output to high impedance. 3. ALE is the first bit in the boundary scan chain scanned in and out. It is closest to TDO in the scan chain.
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171
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
12
OPERATION
12.1 Configuring the OCTLIU from Reset After a system reset (either via the RSTB pin or via the RESET register bit), the OCTLIU will default to the following settings: Table 19 - Default Settings Setting T1/E1 mode Line Code Line interface Receiver Section T1 B8ZS Pins RXTIP[x] and RXRING[x] active short haul analogue inputs Not applicable Transmitter Section T1 B8ZS TXTIP1[x], TXTIP2[x], TXRING1[x], TXRING2[x] tristated Jitter attenuation enabled, with output clock frequency referenced to TCLK[n] All diagnostic modes disabled
Timing Options
Diagnostics
All diagnostic modes disabled
12.2 Servicing Interrupts The OCTLIU will assert INTB to logic 0 when a condition that is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. Read the bits of the Master Interrupt Source registers (002H and 003H) to identify which octants and/or SBI interface blocks generated the interrupt. For example, a logic one read in the LIU[2] bit of the Master Interrupt Source #1 register indicates that octant #2 produced the interrupt. 2. Read the bits of the second level Line Interface Interrupt Source registers to identify the block within the octant generating the interrupt. The Interrupt Source registers for octant #1 are at addresses 00CH and 00DH. The Interrupt Source registers for octant #2 are at addresses 08CH and 08DH. The Interrupt Source registers for octant #3 are at addresses 10CH and 10DH. The Interrupt Source registers for octant #4 are at addresses 18CH and 18DH. The Interrupt Source registers for octant #5 are at addresses 20CH and 20DH. The Interrupt Source registers for octant #6 are at addresses 28CH and 28DH. The Interrupt Source registers for octant #7 are at addresses 30CH and 30DH. The Interrupt Source registers for octant #8 are at addresses 38CH and 38DH.
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172
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
3. Read the third level Interrupt Source bits to identify the interrupt source. (These bits are contained within the registers for the various functional blocks.) 4. Service the interrupt. 5. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB 12.3 Using the Performance Monitoring Features The PMON blocks are provided for performance monitoring purposes. The PMON blocks within each LIU are used to monitor LCV events. An accumulation interval is initiated by writing to one of the PMON event counter register addresses or by writing to the Line Interface Interrupt Source / PMON Update register. After initiating an accumulation interval, 3.5 recovered clock periods must be allowed to elapse to permit the PMON counter values to be properly transferred before the PMON registers may be read. 12.4 Using the Transmit Line Pulse Generator The internal D/A pulse waveform template RAM, accessible via the microprocessor bus, can be used to create up to 12 custom waveforms. The RAM is accessed indirectly through the XLPG Pulse Waveform Storage Write Address and XLPG Pulse Waveform Storage Data registers. The values written into the pulse waveform storage registers correspond to one of 127 quantized levels. 24 samples are output during every transmit clock cycle. The waveform being programmed is completely arbitrary and programming must be done properly in order to meet the various T1 and E1 template specifications. The SCALE[4:0] bits of Line Driver Configuration Register bits are used to obtain a proper output amplitude. It must also be noted that since samples from the 5 UI are added before driving the DAC, it is possible to create arithmetic overflows. The XLPG detects overflows and saturates the resulting value to -62 or +62 as appropriate. However, it is recommended that the pulse amplitude be programmed such that overflows are avoided. It is possible to verify if an overflow condition occurred by reading the OVRFLW register bit after programming a new waveform and transmission of data. The following tables contain the waveform values to be programmed for different situations. Table 20 to Table 29 specify waveform values typically used for T1 long haul and short haul transmission. Table 30 to Table 36 specify waveform values for compliance to the AT&T TR62411 ACCUNET T1.5 pulse template. Table 37 and Table 38 specify waveform values for E1 transmission. The T1 and E1 waveforms shown in these tables (but not the TR62411 waveforms) are also stored in a ROM within the OCTLIU. The ROM contents can be automatically loaded into the waveform template RAM by setting the INITRAM bit in XLPG Control/Status register. Note that the programming of template values must observe the following sequencing rule: Samples must be written in groups of 5 at a time, each group consisting of the 5 UI values corresponding to a particular waveform and sample number. For example, the following programming sequence fragment is legal:
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173
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
: Write Write Write Write Write Write Write Write Write Write :
data data data data data data data data data data
for for for for for for for for for for
WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=1, WAVEFORM=1, WAVEFORM=1, WAVEFORM=1, WAVEFORM=1,
SAMPLE=0, UI=0 SAMPLE=0, UI=1 SAMPLE=0, UI=2 SAMPLE=0, UI=3 SAMPLE=0, UI=4 SAMPLE=12, UI=0 SAMPLE=12, UI=1 SAMPLE=12, UI=2 SAMPLE=12, UI=3 SAMPLE=12, UI=4
whereas the following sequence fragment is illegal:
: Write Write Write Write Write Write Write Write Write Write :
data data data data data data data data data data
for for for for for for for for for for
WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0, WAVEFORM=0,
SAMPLE=0, SAMPLE=1, SAMPLE=2, SAMPLE=3, SAMPLE=4, SAMPLE=5, SAMPLE=6, SAMPLE=7, SAMPLE=8, SAMPLE=9,
UI=0 UI=0 UI=0 UI=0 UI=0 UI=0 UI=0 UI=0 UI=0 UI=0
This restriction is necessary because each group of five 7-bit samples is stored in a temporary holding register as it is written. The 5 samples are then transferred to the pulse template RAM as th a single 35-bit word when the 5 sample (i.e. the sample whose UI[2:0] address field is set to 4) is written. Prior to commencing normal operation, the HIGHZ bit of the octant's XLPG Line Driver Configuration register must be programmed to logic 0 to remove the high impedance state from the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] Transmit outputs.
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174
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 20 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 0 dB) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 08 15 28 36 3A 3A 38 38 38 38 37 36 34 30 1B 00 4E 4C 49 47 47 46 46 UI #1 44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0AH.
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175
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 21 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 01 02 04 08 0C 10 16 1A 1E 22 26 2A 2B 2C 2D 2C 28 24 20 1C 18 14 12 UI #1 10 0E 0C 0A 08 06 04 02 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 06H.
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176
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 22 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 15 dB) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 00 00 00 01 02 04 06 08 0A 0D 10 13 16 18 1A 1D 1F 22 23 24 25 25 23 UI #1 22 20 1E 1D 1B 1A 18 16 15 14 13 12 11 0F 0E 0D 0C 0B 0A 0A 09 08 08 07 UI #2 07 06 06 06 06 05 05 04 04 04 03 03 03 02 02 02 02 02 02 01 01 01 01 01 UI #3 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 03H.
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177
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 23 - T1.102 Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 00 00 00 00 00 01 02 03 04 05 08 0B 0E 12 16 1A 1E 22 25 28 2B 2E 30 UI #1 31 33 35 36 37 38 39 39 38 38 37 36 35 33 31 2F 2E 2D 2B 2A 29 27 25 24 UI #2 23 22 21 20 1E 1D 1C 1B 1A 19 18 17 16 15 13 12 11 10 0F 0E 0D 0D 0B 0A UI #3 0A 09 08 08 07 06 06 05 05 05 04 04 04 03 03 03 03 03 02 02 02 02 02 01 UI #4 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 01H.
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178
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 24 - T1.102 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1A 28 3D 3C 3B 39 39 38 38 37 36 34 30 1D 00 56 53 4F 4C 49 47 46 UI #1 44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0AH.
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179
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 25 - T1.102 Transmit Waveform Values for T1 Short Haul (110 - 220 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1B 29 33 33 30 2F 2E 2E 2D 2C 2C 29 26 00 54 51 4D 49 48 47 46 45 UI #1 45 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0DH.
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180
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 26 - T1.102 Transmit Waveform Values for T1 Short Haul (220 - 330 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1E 2D 36 34 30 2F 2D 2D 2C 2B 2A 29 26 00 58 54 4F 4A 49 47 47 46 UI #1 44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0EH.
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181
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 27 - T1.102 Transmit Waveform Values for T1 Short Haul (330 - 440 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 24 2C 36 34 2F 2D 2C 2C 2B 2A 29 28 1C 00 5A 54 4F 4A 49 47 47 46 UI #1 44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0FH.
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182
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 28 - T1.102 Transmit Waveform Values for T1 Short Haul (440 - 550 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 25 37 33 31 2F 2D 2B 2B 2A 2A 28 25 1A 00 5E 59 4F 4A 49 47 47 46 UI #1 44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 10H.
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183
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 29 - T1.102 Transmit Waveform Values for T1 Short Haul (550 - 660 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 08 30 3B 3B 31 30 2F 2E 2D 2C 2B 2A 28 0C 00 68 5D 51 4B 4A 48 48 47 UI #1 45 45 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 10H.
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184
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 30 - TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 08 15 28 36 3A 3A 38 38 38 38 37 36 34 30 1B 00 4E 4C 49 46 43 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0AH.
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185
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 31 - TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1A 28 3D 3C 3B 39 39 38 38 37 36 34 30 1D 00 4F 4C 49 46 43 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0AH.
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186
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 32 - TR62411 Transmit Waveform Values for T1 Short Haul (110 - 220 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1B 29 33 33 30 2F 2E 2E 2D 2C 2C 29 26 00 54 50 4C 48 45 42 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0DH.
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187
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 33 - TR62411 Transmit Waveform Values for T1 Short Haul (220 - 330 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 1E 2D 36 34 30 2F 2D 2D 2C 2B 2A 29 26 00 58 54 4F 4B 47 43 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0EH.
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188
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 34 - TR62411 Transmit Waveform Values for T1 Short Haul (330 - 440 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 24 2C 36 34 2F 2D 2C 2C 2B 2A 29 28 1C 00 5A 54 4F 4B 47 43 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0FH.
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189
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 35 - TR62411 Transmit Waveform Values for T1 Short Haul (440 - 550 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 0A 25 37 33 31 2F 2D 2B 2B 2A 2A 28 25 1A 00 5E 59 53 4E 49 44 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 10H.
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190
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 36 - TR62411 Transmit Waveform Values for T1 Short Haul (550 - 660 ft.) Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 08 30 3B 3B 31 30 2F 2E 2D 2C 2B 2A 28 0C 00 68 5D 53 4D 49 44 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 10H.
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191
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 37 - Transmit Waveform Values for E1 120 Ohm Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 00 0A 26 32 32 32 32 32 32 32 32 32 32 26 0A 00 00 00 00 00 00 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0AH.
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192
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 38 - Transmit Waveform Values for E1 75 Ohm Sample number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UI #0 00 00 0A 28 34 34 34 34 34 34 34 34 34 34 2D 0A 00 00 00 00 00 00 00 00 UI #1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UI #4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
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193
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
12.5 Using the Line Receiver The line receiver must be properly initialized for correct operation. Several register bits must be programmed and the equalizer RAM table must be initialized according to the appropriate table below. The RLPS equalizer RAM content is programmed by the RLPS Equalization Indirect Data registers for each address location. The address location is given by the octant's RLPS Equalization Indirect Address register. A read or write request is done by setting the RWB bit in the octant's RLPS Equalization Read/WriteB Select register. Note that several registers are not their default values. The EQ_EN bit of the RLPS Equalizer Configuration register must be set to logic 1. The CUTOFF[1:0] bits of the RLPS Voltage Thresholds #2 register must be programmed to 3H (11B) for T1 mode or 0H (00B) for E1 mode. Table 39 summarizes the values the RLPS registers are to contain. Table 39 - RLPS Register Programming Register RLPS Configuration and Status RLPS ALOS Detection/ Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization RAM Read/WriteB Select RLPS Equalizer Loop Status and Control RLPS Equalizer Configuration RLPS Equalization Indirect Data[31:24] RLPS Equalization Indirect Data[23:16] RLPS Equalization Indirect Data[15:8] RLPS Equalization Indirect Data[7:0] RLPS Voltage Thresholds #1 RLPS Voltage Thresholds #2 (T1 mode) (E1 mode) 11XXX011 00XXX011 C3H 03H Data Value Bin XX000XX1 X000X000 00000001 00000001 00000000 1XXXXXXX 00000000 00X01011 * * * * XX101110 Hex 01H 00H 01H 01H 00H 80H 00H 0BH * * * * 2EH
Since the line receiver supports both E1 and T1 standards over either short haul or long haul cables, the line receiver has two normal modes of operation, as selected by the E1/T1B bit of the Global Configuration register. Access to the Equalizer RAM is provided by means of Indirect Access Registers A typical programming sequence follows. This programming sequence is repeated for each of the 256 Equalizer RAM Addresses.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
WRITE RLPS Indirect Data Register WRITE RLPS Indirect Data Register WRITE RLPS Indirect Data Register WRITE RLPS Indirect Data Register
<31 - 24 Bits of Data> <23 - 16 Bits of Data> <15 - 8 Bits of Data> <7 - 0 Bits of Data>
ACTION RLPS Equalisation Read/WriteB Select Register WRITE RLPS Equalisation Indirect Address Register

PAUSE
Table 40 - RLPS Equalizer RAM Table (T1 mode) RAM Address
00D 01D 02D 03D 04D 05D 06D 07D 08D 09D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D
Content (MSB..LSB)
03061C3BH 03061C3BH 03061C3BH 03061C3BH 03061C3BH 03062C3BH 03062C3BH 03062C3BH 03062C3BH 03062C3BH 030E2C3BH 030E2C3BH 030E2C3BH 03162C3BH 03162C3BH 03162C3BH 03162C3BH 03163C3BH 03163C3BH 03163C3BH 03163C3BH 03163C3BH 03163C3BH 031E3C3BH 031C3C3BH 031C3C3BH
RAM Address
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D
Content (MSB..LSB)
766B38BBH 766B38BBH 766B38BBH 7E6B38BBH 7E7338BBH 7E73393BH 7E733D3BH 7E7B3D3BH 7E7B3D3BH 867B3D3BH 867B4D3BH 867B4D3BH 867B4D3BH 867B5D3BH 867B5D3BH 8E7B5D3BH 8E7B6D3BH 8E7B6D3BH 8E7B6D3BH 8E7B7D3BH 8E7B7D3BH 967B7D3BH 967B7D3BH 967B7D3BH 967B793BH 967B793BH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
26D 27D 28D 29D 30D 31D 32D 33D 34D 35D 36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D 64D 65D 66D 67D 68D
Content (MSB..LSB)
031C3C3BH 031C3C3BH 031C3C3BH 03243C3BH 03244C3BH 03244C3BH 03244C3BH 03244C3BH 03244C3BH 032C4C3BH 032E4C3BH 032E5C3BH 032E6C3BH 032E6C3BH 032E6C3BH 032E7C3BH 032E7C3BH 032E7C3BH 072E8C3BH 072E8C3BH 0F2E8C3BH 0F2E8C3BH 0F368C3BH 0F368C3BH 0F368C3BH 0F368C3BH 17368C3BH 17369C3BH 17369C3BH 17369C3BH 1736AC3BH 1736AC3BH 1F3EAC3BH 1F3E9C3BH 1F3E9C3BH 1F469C3BH 1E469C3BH 1E469C3BH 26469C3BH 2646AC3BH 2646AC3BH 2646AC3BH 2646BC3BH
RAM Address
154D 155D 156D 157D 158D 159D 160D 161D 162D 163D 164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D 192D 193D 194D 195D 196D
Content (MSB..LSB)
967B793BH 9E7B793BH 9E7B793BH 9E7B793BH 9E83793BH 9D83793BH 9D83793BH 9D83793BH A583793BH A583893BH A583893BH A583893BH A583993BH A583993BH AD83993BH AD8B993BH AD8BA93BH AD89A93BH AD89A93BH AD89A93BH B589A93BH B589A93BH B589B93BH B589B53BH B589B53BH B589B53BH BD89B53BH BD89B53BH BD91B53BH BD91B53BH BD91B53BH BD91B53BH C591B53BH C591C53BH C591C53BH C591C53BH C591D53BH C591D53BH CD91D53BH CD99D53BH CC99D53BH CC99D4BBH CCA1D4BBH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
69D 70D 71D 72D 73D 74D 75D 76D 77D 78D 79D 80D 81D 82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D 111D
Content (MSB..LSB)
2646BC3BH 2E46BC3BH 2E46BC3BH 2E4EBC3BH 2E4ECC3BH 2E4ECC3BH 2E4ECC3BH 364ECC3BH 364ECC3BH 3656CC3BH 3656DC3BH 3656DC3BH 3656DC3BH 3E56DC3BH 3E56DC3BH 3E56EC3BH 3E54EC3BH 3E54EC3BH 3E54EC3BH 4654EC3BH 4654EC3BH 465CEC3BH 465CEC3BH 465CEC3BH 465CEC3BH 4E5CEC3BH 4E5CEC3BH 4E5CFC3BH 4E5EFC3BH 4E5EF83BH 4E5EF83BH 4E5EF83BH 565EF83BH 565F083BH 565F083BH 565F083BH 565F183BH 565F183BH 5E5F183BH 5E5F183BH 5E5F283BH 5E67283BH 5E67283BH
RAM Address
197D 198D 199D 200D 201D 202D 203D 204D 205D 206D 207D 208D 209D 210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D 239D
Content (MSB..LSB)
CCA1D4BBH D4A1D4BBH D4A1D4BBH D4A1D53BH D4A1D13BH D4A3D13BH D4A3D13BH DCA3D13BH DCA3D13BH DCABD13BH DCA9D13BH DCA9D13BH DCA9D13BH E4A9D13BH E4A9D1BBH E4B1D1BBH E4B1D1BBH E4B1C1BBH E4B1C1BBH ECB1C1BBH ECB1C1BBH ECB1D1BBH ECB1D1BBH ECB1D1BBH ECB1D1BBH F4B1D1BBH F4B1D1BBH F4B1D23BH F4B9D23BH F4B9C23BH F4B9C23BH F4B9C23BH FCB9C23BH FCB9D23BH FCB9D23BH FCB9D23BH FCB9E23BH FCB9E23BH FCB9E23BH FCB9E23BH FCB9E2BBH FCB9D2BBH FCB9D2BBH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
112D 113D 114D 115D 116D 117D 118D 119D 120D 121D 122D 123D 124D 125D 126D 127D
Content (MSB..LSB)
5E67283BH 6667283BH 6665283BH 6665283BH 6665283BH 6663283BH 6663283BH 6E63283BH 6E6B283BH 6E6B28BBH 6E6B2CBBH 6E732CBBH 6E732CBBH 76732CBBH 767328BBH 767338BBH
RAM Address
240D 241D 242D 243D 244D 245D 246D 247D 248D 249D 250D 251D 252D 253D 254D 255D
Content (MSB..LSB)
FCB9D2BBH FCB9D2BBH FCB9D2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9E2BBH FCB9F2BBH FCB9F2BBH FCB9F2BBH FCB9F2BBH
Table 41 - RLPS Equalizer RAM Table (E1 mode) RAM Address
00D 01D 02D 03D 04D 05D 06D 07D 08D 09D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D
Content (MSB..LSB)
03062C3BH 03062C3BH 03062C3BH 03062C3BH 030E2C3BH 030E2C3BH 03162C3BH 03162C3BH 03162C3BH 03163C3BH 031E3C3BH 031E3C3BH 031E3C3BH 031E3C3BH 031E3C3BH 031E4C3BH 031E4C3BH 031E4C3BH 031E4C3BH 031E4C3BH 03264C3BH 03264C3BH 032E4C3BH 032E4C3BH
RAM Address
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D
Content (MSB..LSB)
8A80F93BH 8A80F9BBH 8A80F9BBH 9280F9BBH 928109BBH 918109BBH 918119BBH 918119BBH 998129BBH 998125BBH 998135BBH 998135BBH 998131BBH A18131BBH A18931BBH A18931BBH A18931BBH A19131BBH A19131BBH A99131BBH A99131BBH A991323BH A991323BH A991323BH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
24D 25D 26D 27D 28D 29D 30D 31D 32D 33D 34D 35D 36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D 64D 65D 66D
Content (MSB..LSB)
032E4C3BH 032E4C3BH 032E5C3BH 032E5C3BH 032E5C3BH 032E5C3BH 032E5C3BH 03365C3BH 03366C3BH 03366C3BH 03366C3BH 03366C3BH 03366C3BH 03367C3BH 03367C3BH 03367C3BH 0B367C3BH 0B3E7C3BH 0B3E8C3BH 0B3E8C3BH 0B3E8C3BH 133E8C3BH 13468C3BH 13469C3BH 13469C3BH 13469C3BH 13469C3BH 1B469C3BH 1B4E9C3BH 1B4EAC3BH 1B4EAC3BH 1B4EAC3BH 234EAC3BH 2346AC3BH 2346ACBBH 2346ACBBH 2346ACBBH 2B46ACBBH 2B4EACBBH 2B4EBCBBH 2B4EBCBBH 2B56BCBBH 2B56BCBBH
RAM Address
152D 153D 154D 155D 156D 157D 158D 159D 160D 161D 162D 163D 164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D 192D 193D 194D
Content (MSB..LSB)
B191323BH B191323BH B199323BH B199323BH B199323BH B999323BH B999323BH B999423BH B9A1423BH B9A1423BH B9A1423BH C1A1423BH C1A1523BH C1A1523BH C1A1623BH C1A1623BH C9A1623BH C9A1623BH C9A1723BH C9A172BBH C9A172BBH D1A172BBH D1A972BBH D1A972BBH D1A972BBH D1B172BBH D1B172BBH D9B172BBH D9B172BBH D9B972BBH D9B972BBH D9B972BBH E1B982BBH E1BB82BBH E0BB82BBH E0BB92BBH E0BB92BBH E8BB92BBH E8BB92BBH E8BBA2BBH E8C3A2BBH E8C3A2BBH E8C3A2BBH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D 79D 80D 81D 82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D
Content (MSB..LSB)
3356BCBBH 3356BCBBH 3356CCBBH 3356CCBBH 3356CCBBH 3B56CCBBH 3B5ECCBBH 3B5EDCBBH 3B5EDCBBH 3B5EDCBBH 435EDCBBH 435EDCBBH 4366DCBBH 4364DCBBH 4364DCBBH 4364DCBBH 4B64DCBBH 4B6CDCBBH 4B6CECBBH 4B6CECBBH 4B6CECBBH 536CECBBH 536CE8BBH 536CF8BBH 536CF83BH 536CF83BH 5B6CF83BH 5B6CF83BH 5B6CF8BBH 5B64F8BBH 5B64F8BBH 5B64F8BBH 6364F8BBH 636CF8BBH 626CF8BBH 6274F8BBH 6274F8BBH 6A74F8BBH 6A74F8BBH 6A74F93BH 6A74F93BH 6A74F93BH 7274F93BH
RAM Address
195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D 207D 208D 209D 210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D
Content (MSB..LSB)
F0C3A2BBH F0C3A2BBH F0CBA2BBH F0CBA2BBH F0CBA2BBH F8CBA2BBH F8C3A2BBH F8C3A33BH F8C3A33BH F8C3A33BH F8C3A33BH F8C3A33BH F8CBA33BH F8C9A33BH F8C9A33BH F8C9A33BH F8C9A33BH F8C9A73BH F8C9A7BBH F8C9B7BBH F8C9B7BBH F8C9B7BBH F8C9BBBBH F8D1BBBBH F8D1BBBBH F8D1BBBBH F8D1BBBBH F8D1BBBBH F8D1CBBBH F8D1CBBBH F8D1CBBBH F8D1CBBBH F8D1CBBBH F8D9CBBBH F8D9CBBBH F8E1CBBBH F8E1CBBBH F8E1CBBBH F8E1CBBBH F8E1C7BBH F8D9C7BBH F8D9D7BBH F8D9D7BBH
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RAM Address
110D 111D 112D 113D 114D 115D 116D 117D 118D 119D 120D 121D 122D 123D 124D 125D 126D 127D
Content (MSB..LSB)
7274F93BH 7274F93BH 7272F93BH 7272F93BH 7272F93BH 7A72F93BH 7A70F93BH 7A70E93BH 7A78E93BH 7A78E93BH 8278E93BH 8278E93BH 8278E8BBH 8278E8BBH 8278E8BBH 8A78E8BBH 8A78E93BH 8A78F93BH
RAM Address
238D 239D 240D 241D 242D 243D 244D 245D 246D 247D 248D 249D 250D 251D 252D 253D 254D 255D
Content (MSB..LSB)
F8D9D7BBH F8D9E7BBH F8D9E3BBH F8D9E3BBH F8D9E3BBH F8D9E3BBH F8D9E3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH F8D9F3BBH
Table 42 - RLPS Equalizer RAM Table (Monitor Mode) TBD 12.6 Using the PRBS Generator and Detector PRBS patterns may be generated and detected in either the transmit or receive directions, as configured by the TX_GEN, RX_GEN and TX_DET bits of the Line Interface PRBS Position registers. 12.7 Loopback Modes The OCTLIU provides two loopback modes to aid in network and system diagnostics. The network (line) loopback can be initiated at any time via the P interface, but is usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the LIU. 12.7.1 Line Loopback When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Line Interface Diagnostics Register to logic 1, the LIU is configured to internally connect the recovered data to the transmit jitter attenuator, TJAT. The data sent to the TJAT is the recovered data from the output of the CDRC block. Note that when line loopback is enabled, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
mode / FFH in E1 mode to correctly attenuate the jitter on the receive clock. Conceptually, the data flow through a single octant of the OCTLIU in this loopback mode is illustrated in Figure 18. Figure 18 - Line Loopback
TDP[n] TDN[n] TCLK[n]
XIBC
XPDE
LCODE
TJAT
XLPG
TXTIP[x] TXRING[x]
Line Loopback
RDP[n] RDN/RLCV[n] RCLK[n]
RJAT
IBCD
PDVD
CDRC
RLPS
RXTIP[x] RXRING[x]
12.7.2 Diagnostic Digital Loopback When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the Line Interface Diagnostics Register to logic 1, the OCTLIU octant is configured to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. Conceptually, the data flow through a single octant of the OCTLIU in this loopback condition is illustrated in Figure 19. Figure 19 - Diagnostic Digital Loopback
TDP[n] TDN[n] TCLK[n]
XIBC
XPDE
LCODE
TJAT
XLPG
TXTIP[x] TXRING[x]
Diagnostic Loopback
RDP[n] RDN/RLCV[n] RCLK[n]
RJAT
IBCD
PDVD
CDRC
RLPS
RXTIP[x] RXRING[x]
12.8 JTAG Support The OCTLIU supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on the TDI primary input and to output data on the TDO primary output. The TMS primary input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. Figure 20 - Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single-bit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs. 12.8.1 TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 21 - TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run/test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out of the output, TDO, using the Shift-DR state. Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFTDR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 22 - Input Observation Cell (IN_CELL) IDCODE
Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
Figure 23 - Output Cell (OUT_CELL) or Enable Cell (ENABLE) Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 24 - Bidirectional Cell (IO_CELL) Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 1
INPUT to internal logic
MUX
OUTPUT to pin
D C
D C
Figure 25 - Layout of Output Enable and Bidirectional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
13
FUNCTIONAL TIMING
13.1 SBI BUS Interface Timing Figure 26 - SBI BUS Functional Timing REFCLK C1FP DATA[7:0] PL V5 DP C1 *** *** *** *** *** *** V3 V3 V3 DS0#4. V5 DS0#9.
Figure 26 illustrates the operation of the SBI Bus, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting PL high during the V3 octet. The timing diagram also shows the location of one of the tributaries by asserting V5 high during the V5 octet. Note - the SBI ADD and DROP busses operate in an identical manner. Signal names on the ADD bus have an A prepended to the names shown in Figure 26 (e.g, AC1FP, ADATA[7:0], etc.) and those on the DROP bus have an D prepended to them (e.g, DC1FP, DDATA[7:0], etc.)
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
13.2 Line Code Violation Insertion Figure 27 - B8ZS Line Code Violation Insertion B8ZS Signature Pattern
000VB0VB
TCLK TDP TXTIP TXRING
B8ZS Signature Pattern
000VB0VB continuous zeros 000V B 0V B
TCLK TDP TXTIP TXRING
continuous zeros 0000 B0V LCVINS = 1 causes omission of first bipolar violation pulse. B
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in Figure 27. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative purposes. Setting LCVINS to a logic 1 generates one line code violation and 3 bit errors by causing the omission of the first line code violation pulse when a string of 8 consecutive zeros occurs in the unipolar data stream TDP. To generate another line code violation, the LCVINS bit must be reset to logic 0 and then set to logic 1 again.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 28 - HDB3 Line Code Violation Insertion
TCLK TDP TXTIP TXRING
continuous zeros
000V 100V
100V 1
TCLK TDP TXTIP TXRING
continuous zeros
000V 100V000V
1
LCVINS = 1 causes omission of bipolar pulse and violation of same polarity as previous violation.
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in Figure 28. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative purposes. Setting LCVINS to a logic 1 generates one line code violation by causing the omission of a bipolar pulse and hence a bipolar violation pulse of the same polarity as the previous bipolar violation pulse when a string of 4 consecutive zeros occurs in the unipolar data stream TDP. To generate another line code violation, the LCVINS bit must be reset to logic 0 and then set to logic 1 again.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 29 - AMI Line Code Violation Insertion
TCLK TDP TXTIP TXRING TCLK TDP TXTIP TXRING
LCVINS = 1 causes a bipolar violation V
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in Figure 29. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative purposes. Setting LCVINS to a logic 1 generates one line code violation by causing the next pulse to be of the same polarity as the previous pulse. Subsequent pulses will be of alternate polarity. To generate another line code violation, the LCVINS bit must be reset to logic 0 and then set to logic 1 again. 13.3 Alarm Interface Figure 30 - LOS Alarm Serial Output
XCLK
LOS_L1
LOS
LOS8
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
LOS1
Figure 30 shows the operation of the Alarm Interface. The LOS status of the 8 LIU octants is output continuously in a serial format with a marker signal LOS_L1 to indicate the presence of the LOS status for LIU #1.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
14
ABSOLUTE MAXIMUM RATINGS Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 43 - Absolute Maximum Ratings Case Temperature under Bias Storage Temperature Supply Voltage VDDall331 Supply Voltage VDD1V8 Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature -40C to +85C -40C to +125C -0.3V to +4.6V -0.3V to +3.6V -0.3V to VDDall33 + 0.3V 1000V 100mA 20mA +230C +150C
Not Withstanding the values in the above table 3.3V power supplies must always be at a voltage greater than or equal to the 1.8V power supplies.
1
The OCTLIU 3.3 Volt digital and analogue power pins are collectively referred to as VDDall33.
214
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
15
D.C. CHARACTERISTICS TA = -40C to +85C, VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5% (Typical Conditions: TA = 25C, VDDall33 = 3.3V, VDD1V8 = 1.8V) Table 44 - D.C. Characteristics
Symbol VDD3V3, TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD VDD1V8 VIL VIH VOL Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage Output or Bidirectional High Voltage Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input Low Current Input High Current Input Low Current Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance +20 -10 -10 -200 -10 -10 2.4 2.0 0.1 0.4 1.71 1.8 1.89 0.8 Volts Volts Volts Volts Note 5. Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -6mA for LOS, LOS_L1, TDO and Serial PROM interface outputs; -8mA for others. Notes 3, 5 VDD = min, IOH = 6mA for LOS, LOS_L1, TDO and Serial PROM interface outputs; 8mA for others. Notes 3,5 Applies to TTL Schmidt-triggered inputs (RSTB, TRSTB) only. Note 5. Applies to TTL Schmidt-triggered inputs (RSTB, TRSTB) only. Note 5. Applies to TTL Schmidt-triggered inputs (RSTB, TRSTB) only. Note 5. VIL = GND. Notes 1, 3, 5 VIH = VDD. Notes 1, 3, 5 VIL = GND. Notes 4, 3, 5 VIH = VDD. Notes 4, 3, 5 VIL = GND. Notes 2, 3, 5 VIH = VDD. Notes 2, 3, 5 Excluding Package, Package Typically 2 pF. Note 5. Excluding Package, Package Typically 2 pF. Note 5. Parameter Power Supply Min 3.135 Typ 3.3 Max 3.465 Units Volts Conditions Note 5.
VOH
2.7
Volts
VT+ VTVTH
2.0
1.6 1.1 0.5 0.8
Volts Volts Volts
IILPU IIHPU IILPD IIHPD IIL IIH CIN COUT
+83 0 0 -83 0 0 5 5
+200 +10 +10 -20 +10 +10
A A A A A A pF pF
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Symbol CIO IDDOP 3V3 IDDOP 1V8
Parameter Bidirectional Capacitance 3.3V Operating Current 1.8V Operating Current
Min
Typ 5
Max
Units pF
Conditions Excluding Package, Package Typically 2 pF. Note 5. Digital output pads loaded wih max capacitance. Transmission of pattern containing 50% ones.
400
mA
150
mA
Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up or pull-down resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Input pin or bi-directional pin with internal pull-down resistor. 5. Typical values are given as a design aid. This product is not tested to the typical values given in the datasheet.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TA = -40C to +85C, VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 45 - Microprocessor Interface Read Access Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state Min 10 5 10 10 20 0 5 70 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 31 - Microprocessor Interface Read Timing
tSAR A[10:0] tS ALR tVL ALE tSLR (CSB+RDB) tZ INTH INTB tHLR tHALR
Valid
Address
tH AR
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable. 5. Parameter tHAR is not applicable if address latching is used.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. Table 46 - Microprocessor Interface Write Access Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW TVWR Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 5 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 32 - Microprocessor Interface Write Timing
A[9:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17
OCTLIU TIMING CHARACTERISTICS
17.1 RSTB Timing (Figure 33) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 47 - RTSB Timing Symbol tVRSTB Description RSTB Pulse Width Min 100 Max Units ns
Figure 33 - RSTB Timing
tV RSTB RSTB
17.2 XCLK Input Timing (Figure 34) Table 48 - XCLK Input Timing Symbol tXCLK tLXCLK tHXCLK Description XCLK Frequency (1.544 MHz or 2.048 MHz 100ppm) XCLK Low Pulse Width (Note 1) XCLK High Pulse Width (Note 1) Min 1.544 - 100ppm 160 160 Max 2.048 +100ppm Units MHz ns ns
Figure 34 - XCLK Input Timing
tH
XCLK
XCLK
t L XCLK
t
XCLK
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.3 Transmit Serial Interface (Figure 35) (TA = -40C to +85C, VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 49 - Transmit Serial Interface Symbol Description TCLK[8:1] Frequency (1.544MHz 200ppm or 2.048MHz 200 ppm) TCLK[8:1] Jitter TCLK[8:1] Duty Cycle tSTD tHTD TDP[n], TDN[n] to TCLK[n] Set-up Time TDP[n], TDN[n] to TCLK[n] Hold Time Min 1.544 - 200ppm -50 35 20 20 Max 2.048 +200ppm 50 65 Units MHz ns % ns ns
Figure 35 - Transmit Serial Interface Timing Diagram
TDP[n] TDN[n]
Valid tS TD tH TD
TCLK[n] Inputs Samped on Rising Edge
TDP[n] TDN[n]
Valid tS TD tH TD
TCLK[n] Inputs Samped on Falling Edge
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.4 Receive Serial Interface (Figure 36) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 50 - Receive Serial Interface Symbol tPRD Description RCLK[n] to RDP[n], RDN/RLCV[n] Propagation Delay Min -20 Max 50 Units ns
Figure 36 - Receive Serial Interface Timing Diagram
RCLK[n]
RDP[n] RDN/RLCV[n] tPRD
Valid
Output on Rising Edge
RCLK[n]
RDP[n] RDN/RLCV[n] tPRD
Valid
Output on Falling Edge
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.5 SBI Interface (Figure 37 to Figure 39) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 51 - Clocks and SBI Frame Pulse Symbol Description REFCLK Frequency REFCLK Duty Cycle TSC1FP THC1FP TPC1FPOUT AC1FP, DC1FP Set-Up Time to REFCLK AC1FP, DC1FP Hold Time to REFCLK REFCLK to C1FPOUT Valid Min 19.44 - 50ppm 40 4 0 1 20 Max 19.44 +50ppm 60 Units MHz % ns ns ns
Figure 37 - SBI Frame Pulse Timing
REFCLK tSC1FP AC1FP DC1FP tPC1FPOUT C1FPOUT tHC1FP
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 52 - SBI ADD BUS Symbol tSSBIADD tHSBIADD Description All SBI ADD BUS Inputs Set-Up Time to REFCLK All SBI ADD BUS Inputs Hold Time to REFCLK Min 4 0 Max Units ns ns
Figure 38 - SBI ADD BUS Timing
REFCLK tSSBIADD ADATA[7:0] ADP, APL AV5 tHSBIADD
Table 53 - SBI DROP BUS Symbol tPDACTIVE tPSBIDROP tZSBIDROP Description REFCLK to DACTIVE Valid REFCLK to All SBI DROP BUS Outputs (except DACTIVE) Valid REFCLK to All SBI DROP BUS Outputs (except DACTIVE) Tristate Min 2 2 2 Max 15 20 20 Units ns ns ns
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 39 - SBI DROP BUS Timing
REFCLK tPDACTIVE DACTIVE tPSBIDROP DDATA[7:0] DDP, DPL, DV5 tZSBIDROP DDATA[7:0] DDP, DPL, DV5
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.6 Serial PROM (SPI) Interface (Figure 40) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 54 - SPI Interface Symbol Description SRCLK Frequency SRCCLK Frequency TSSPI THSPI TPSPI SPI Input Set-Up Time to SRCLK, SRRCLK SPI Input Set-Up Time to SRCLK, SRRCLK SRCLK, SRRCLK to SPI Output Prop. Time Min Max Units
XCLK frequency / 4 XCLK frequency / 4 50 50 -50 50 ns ns ns
Figure 40 - SPI Interface Timing
SRCLK
tS SP I SREN (Slave) SRDO
tH SPI
tP SP I SREN (Master) SRDI
SRCCLK
tP SPI SRCEN SRCDO
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.7 Alarm Interface (Figure 41) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 55 - Alarm Interface Symbol TPLOS Description XCLK to LOS, LOS_L1 Output Prop. Time Min -50 Max 50 Units ns
Figure 41 - Alarm Interface Timing
XCLK
tP LOS LOS LO S_L1
17.8 Ingress Clk/Data Interface (Figure 42) Table 56 - Ingress Clk/Data Interface Symbol Description ICLK_IN Frequency (1.544MHz 200ppm or 2.048MHz 200 ppm) ICLK_IN Duty Cycle tSINGRESS tHINGRESS tPINGRESS IDATA[8:1], IFP_IN Set-up Time IDATA[8:1], IFP_IN Hold Time ICLK_OUT to IFP_OUT Propagation Delay Min 1.544 - 200ppm 35 20 20 -20 50 Max 2.048 +200ppm 65 Units MHz % ns ns ns
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 42 - Ingress Clk/Data Interface Timing Diagram
ICLK_IN tSINGRESS IDATA[8:1] IFP_IN tHINGRESS
ICLK_OUT tPINGRESS IFP_OUT
17.9 Egress Clk/Data Interface (Figure 43) Table 57 - Engress Clk/Data Interface Symbol Description Min Max Units
tPEGRESS
ECLK to EDATA[8:1], EFP Propagation Delay
-20
50
ns
Figure 43 - Egress Clk/Data Interface Timing Diagram
ECLK tPEGRESS EDATA[8:1] EFP
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
17.10 JTAG Port Interface (Figure 44) (TA = -40C to +85C VDDall33 = 3.3V 5%, VDD1V8 = 1.8V 5%) Table 58 - JTAG Port Interface Symbol Description Min Max Units
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100
1 60
MHz % ns ns ns ns
50
ns ns
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 44 - JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
Notes on OCTLIU Timing:
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps. 2. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 3. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 4. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 5. Maximum output propagation delays are measured with a 100 pF load on the SBI DROP Bus outputs (except DACTIVE) and a 50 pF load on DACTIVE and all other outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
18
ORDERING AND THERMAL INFORMATION Table 59 - Ordering Information Part No. Description
PM4318-BI
288-pin Tape Super Ball Grid Array (TSBGA)
Table 60 - OCTLIU Theta Jc PART NO. CASE TEMPERATURE Theta Jc
PM4318-BI
-40C to +85C
1.0 C/W
Table 61 - OCTLIU Junction Temperature
PM4318-BI
Maximum Junction Temperature for Long Term Reliability
110 C
Table 62 - OCTLIU Theta Ja vs. Airflow
Forced Air (Linear Feet per Minute) Part No. Case Temperature Theta J-A at 2.5 Watts Conv 100 200 300 400 500
PM4318-BI
-40C to 85C
Dense Board
1 2
32.8 13.7
30.1 12.0
28.3 10.8
27.2 10.0
26.7 9.4
26.5 9.0
JEDEC Board
1. - Dense Board is defined as a 3S3P board and consists of a 3x3 array of PM4318-BI devices located as close to each other as board design rules allow. All PM4318-BI devices are assumed to be dissipating maximum power. Theta J-A listed is for the device in the middle of the array. 2. - JEDEC Board Theta J-A is the measured value for a single thermal device in the same package on a 2S2P board following EIA/JESD 51-3.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
232
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
19
MECHANICAL INFORMATION
D1,M D
A B
eee M fff M
aaa 2X
C CAB C b
A1 BALL CORNER
A1 BALL PAD CORNER
22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB
A1 BALL INDICATOR A S
A
E
E1,N
e
aaa 2X
C
6.
S e
A A1
TOP VIEW
bbb
BOTTOM VIEW
C 0.075 MIN
A2
SEATING PLANE
C
ddd
C
d
ccc
C
SIDE VIEW
NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSION aaa DENOTES PACKAGE BODY PROFILE. 3) DIMENSION bbb DENOTES PARALLEL. 4) DIMENSION ccc DENOTES FLATNESS. 5) DIMENSION ddd DENOTES COPLANARITY. 6) DIAMETER OF SOLDER MASK OPENING IS 0.550 MM (SMD).
A-A SECTION VIEW
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
233
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
234
PRELIMINARY DATASHEET PMC- 2001578 ISSUE 3
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2001578 (p3) Issue date: April 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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