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| LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier DESCRIPTION The LF2250 is a high-speed matrix multiplier consisting of an array of nine 12 x 10-bit multipliers. Internal summing adders are also included to provide the configurations needed to implement matrix multiplications, cascadable FIR filters, and pixel convolvers. The 3 x 3 matrix multiplier (triple dot product) configuration of the LF2250 allows users to easily perform threedimensional perspective translations or video format conversions at real-time video rates. By using the LF2250 in this configuration, conversions can be made from the RGB (color component) format to the YIQ (quadrature encoded chrominance) or YUV (color difference) formats and vice versa (YIQ or YUV to RGB). In addition to color space conversions, the LF2250 offers a range of selectable configurations designed for filtering applications. When configured as a 9-tap FIR filter, the LF2250 automatically selects the necessary internal bus structure and inserts the appropriate data path delay elements. In addition, a 16-bit cascade input port allows for the creation of larger filters without a reduction in throughput. Real-time video image filtering using the convolver modes of the LF2250 can provide edge detection, texture enhancement, and detail smoothing. Both pixel convolver configurations, 3 x 3 and 4 x 2, deliver high-speed data manipulation in a single chip solution. By using the 16-bit cascade input port to cascade two devices, cubic convolutions (4 x 4-pixel) can be easily accommodated with no decrease in throughput rates. All inputs and outputs, as well as all control lines, are registered on the rising edge of clock. The LF2250 operates at clock rates up to 50 MHz over the full commercial temperature and supply voltage ranges. FEATURES u 50 MHz Data and Computation Rate u Nine Multiplier Array with 12-bit Data and 10-bit Coefficient Inputs u Separate 16-bit Cascade Input and Output Ports u On-board Coefficient Storage u Four User-Selectable Filtering and Transformation Functions: * 3 x 3 Matrix Multiplier * Cascadable 9-Tap FIR Filter * Cascadable 3 x 3 Convolver * Cascadable 4 x 2 Convolver u Replaces TRW/Raytheon/ Fairchild TMC2250 u 120-pin PQFP LF2250 BLOCK DIAGRAM CLK MODE1-0 CWE1-0 2 2 12 DATA OUTPUTS CASCADE PORTS PIN NAME { { X11-0 Y11-8 Y7-4 Y3-0 Z11-0 { XC11-0 YC11-8 Y7-4 CASIN15-4 CASIN3-0 DATA INPUTS { { A11-0 B11-0 C11-0 12 12 12 4 4 4 12 CASOUT3-0 CASOUT15-4 YC3-0 ZC11-0 KA9-0 KB9-0 KC9-0 10 10 10 COEFFICIENT INPUTS 9-MULTIPLIER ARRAY Video Imaging Products 1 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier BIT WEIGHTING The internal sum of products of the LF2250 can grow to 23 bits. However, in order to keep the output format of the matrix multiply mode (Mode 00) identical to the input format, the X, Y, and Z outputs are truncated to 12-bit integer words. In the filter modes (Modes 01, 10, 11), the cascade output is always half-LSB rounded to 16 bits (12 integer bits and 4 fractional bits). The user may half-LSB round the output to any size less than 16 bits by simply forcing a "1" into the bit position of the cascade input immediately below the desired LSB. For example, if half-LSB rounding to 12 bits is desired, then a "1" must be forced into the CASIN3 bit position (CASOUT4 would then be the LSB). In all four modes, the user may adjust the bit weighting, by applying an identical scaling correction factor to both the input and output data streams. If the coefficients are rescaled, then the relative weightings of the cascade-in and cascade-out ports will differ accordingly. Figure 1 illustrates the input and output bit weightings for all four modes. DATA OVERFLOW Because the LF2250's matched input and output data formats accommodate unity gain (0 dB), input conditions that could lead to numeric overflow may exist. To ensure that no overflow conditions occur, the user must be aware of the maximum input data and coefficient word sizes allowable for each specific algorithm being performed. SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK -- Master Clock The rising edge of CLK strobes all enabled registers. All timing specifications are referenced to the rising edge of CLK. Inputs A11-0, B11-0, C11-0 -- Data Inputs A, B, and C are the 12-bit registered data input ports. Data presented to these ports is latched into the multiplier input registers for the current operating mode (Table 1). In the filter modes (Modes 01, 10, 11), the rising edge of CLK internally right-shifts new data to the next filter tap. KA9-0, KB9-0, KC9-0 -- Coefficient Inputs KA, KB, and KC are the 10-bit registered coefficient input ports. Data presented to these ports is latched into the corresponding internal coefficient register set defined by CWE1-0 (Table 4) on the next rising edge of CLK. Table 3 shows which coefficient registers are available for each coefficient input port. TABLE 1. MODE SELECTION MODE1-0 00 01 10 11 OPERATING MODE 3 x 3 Matrix Multiplier 9-Tap FIR Filter 3 x 3 Convolver 4 x 2 Convolver OPERATING MODES The LF2250 can realize four different user-selectable digital filtering architectures as determined by the state of the mode (MODE1-0) inputs. Upon selection of the desired function, the LF2250 automatically chooses the appropriate internal data paths and input/output bus structure. Table 1 details the modes of operation. DATA FORMATTING The coefficient input ports (KA, KB, KC) are 10-bit fractional two's complement format regardless of the operating mode. The data input ports (A, B, C) are 12-bit integer two's complement format regardless of the operating mode. In the matrix multiplier mode (Mode 00), the data output ports (X, Y, Z) are 12-bit integer two's complement format. In the FIR filter and convolver modes (Modes 01, 10, 11), the X, Y, and Z ports are configured as the cascade-in (CASIN15-0) and cascade-out (CASOUT15-0) ports. These ports assume 16-bit (12-bit integer, 4-bit fractional) two's complement data on both the inputs and outputs. Table 2 shows the data port formatting for each of the four operating modes. TABLE 2. MODE1-0 00 01 10 11 DATA PORT FORMATTING PIN NAMES A11-0 A11-0 A11-0 A11-0 A11-0 B11-0 B11-0 A11-0 B11-0 B11-0 C11-0 C11-0 NC C11-0 NC KA9-0 KA9-0 KA9-0 KA9-0 KA9-0 KB9-0 KB9-0 KB9-0 KB9-0 KB9-0 KC9-0 KC9-0 KC9-0 KC9-0 KC9-0 XC11-0 X11-0 CASIN15-4 CASIN15-4 CASIN15-4 YC11-8 Y11-8 CASIN3-0 CASIN3-0 CASIN3-0 Y7-4 Y7-4 NC NC NC YC3-0 Y3-0 CASOUT3-0 CASOUT3-0 CASOUT3-0 ZC11-0 Z11-0 CASOUT15-4 CASOUT15-4 CASOUT15-4 Video Imaging Products 2 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier CASOUT15-0 -- Cascade Output In the filter modes (Modes 01, 10, 11), the 12-bit Z port and four bits of the Y port are internally reconfigured as the 16-bit registered cascade output port. NOTE: The X, Y, and Z ports are automatically reconfigured by the LF2250 as the cascade-in and cascade-out ports as required for each operating mode. Because both the X and Z ports are used for the cascade ports, all X port pins and all Z port pins are labelled as XC and ZC, respectively. All Y port pins that are used for the cascade ports are labelled as YC. Those Y port pins which are not used for the cascade ports are labelled as Y. Controls Internal Sum (All Modes) MODE1-0 -- Mode Select The registered mode select inputs determine the operating mode of the LF2250 (Table 1) for data being input on the next clock cycle. When switching between modes, the internal pipeline latencies of the device must be observed. After switching operating modes, the user must allow enough clock cycles to pass to flush the internal registers before valid data will appear on the outputs. CWE1-0 -- Coefficient Write Enable The registered coefficient write enable inputs determine which internal coefficient register set to update (Table 4) on the next clock cycle. FIGURE 1A. INPUT FORMATS Data Input (All Modes) 11 10 9 8 7 -211 210 29 28 27 (Sign) 6543210 26 25 24 23 22 21 20 Coefficient Input (All Modes) 9876543210 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 (Sign) Cascade Input (Modes 01, 10, 11) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -211 210 29 28 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 (Sign) 20 19 18 17 -211 210 29 28 (Sign) 3210 2-6 2-7 2-8 2-9 FIGURE 1B. OUTPUT FORMATS Result (Mode 00) 11 10 9 8 7 -211 210 29 28 27 (Sign) 6543210 26 25 24 23 22 21 20 Cascade Out (Modes 01, 10, 11) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -211 210 29 28 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 (Sign) CASIN15-0 -- Cascade Input In the filter modes (Modes 01, 10, 11), the 12-bit X port and four bits of the Y port are internally reconfigured as the 16-bit registered cascade input port. Data presented to this port will be added to the internal sum of products. Outputs X11-0, Y11-0, Z11-0 -- Data Outputs X, Y, and Z are the 12-bit registered output ports for the matrix multiply mode (Mode 00). These ports are automatically reconfigured for the filter modes (Modes 01, 10, 11) as the cascade-in and cascade-out ports. TABLE 3. KA KB KC COEFFICIENT INPUTS REG. AVAILABLE KA1, KA2, KA3 KB1, KB2, KB3 KC1, KC2, KC3 INPUT PORT Video Imaging Products 3 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier (comprising of the summation of the multiplications of the last nine data inputs with their related coefficients) becomes available (Table 5). The CASIN term is also added to each new output. The internal bus structure and pipeline delays allow new input data to be added every cycle while maintaining the structure of the filtering operation. This addition of new data every cycle produces the effect of the convolution window moving to the next pixel column. 4 x 2-Pixel Convolver -- Mode 11 Using the A and B ports, input data is loaded and multiplied by the onboard coefficients. These products are then summed with the CASIN data and rounded to create the 16-bit output. The cascade ports allow multiple devices to be used together for use with larger kernels. As with Mode 10, each cycle results in a 16-bit output created from the products and summations performed. TABLE 4. CWE1-0 00 01 10 11 COEFF. REG. UPDATE COEFFICIENT SET Hold All Registers KA1, KB1, KC1 KA2, KB2, KC2 KA3, KB3, KC3 DETAILS OF OPERATION 3 x 3 Matrix Multiplier -- Mode 00 In this mode, all three input ports (A, B, C) and all three output ports (X, Y, Z) are utilized to implement a 3 x 3 matrix multiplication (triple dot product). Each rounded 12-bit output is the sum of all three input words multiplied by the appropriate coefficients (Table 5). The pipeline latency for this mode is five clock cycles. Therefore, the sum of products will be output five clock cycles after the input data has been latched. New output data is subsequently available every clock cycle thereafter. 9-Tap FIR Filter -- Mode 01 This mode utilizes the 12-bit A and B data input ports as well as the 16-bit CASIN port. The input data should be presented to the A and B ports simultaneously. The resulting 9sample response, which is half-LSB rounded to 16 bits, begins after five clock cycles and ends after 13 clock cycles (Table 5). The pipeline latency from the input of an impulse response to the center of the output response is nine clock cycles. The latency from the CASIN port to the CASOUT port is four clock cycles. New output data is available every clock cycle. 3 x 3-Pixel Convolver -- Mode 10 When configured in this mode, line delayed data is loaded through the A, B, and C input ports. During each cycle, a new rounded 16-bit output TABLE 5. LATENCY EQUATIONS 3 x 3 Matrix Multiplier -- Mode 00 X(n+4) = A(n)KA1(n) + B(n)KB1(n) Y(n+4) = A(n)KA2(n) + B(n)KB2(n) Z(n+4) = A(n)KA3(n) + B(n)KB3(n) + C(n)KC1(n) + C(n)KC2(n) + C(n)KC3(n) 9-Tap FIR Filter -- Mode 01 CASOUT(n+12) = A(n+8)KA3(n+8) + A(n+7)KA2(n+7) + A(n+6)KA1(n+6) + B(n+5)KB3(n+8) + B(n+4)KB2(n+7) + B(n+3)KB1(n+6) + B(n+2)KC3(n+8) + B(n+1)KC2(n+7) + B(n)KC1(n+6) + CASIN(n+9) 3 x 3-Pixel Convolver -- Mode 10 CASOUT(n+6) = A(n+2)KA3(n+2) + A(n+1)KA2(n+1) + A(n)KA1(n) + B(n+2)KB3(n+2) + B(n+1)KB2(n+1) + B(n)KB1(n) + C(n+2)KC3(n+2) + C(n+1)KC2(n+1) + C(n)KC1(n) + CASIN(n+3) 4 x 2-Pixel Convolver -- Mode 11 CASOUT(n+7) = A(n+3)KA3(n+3) + A(n+2)KA2(n+2) + A(n+1)KA1(n+1) + A(n)KC3(n+3) + B(n+3)KB3(n+3) + B(n+2)KB2(n+2) + B(n+1)KB1(n+1) + B(n)KC1(n+1) + CASIN(n+4) Video Imaging Products 4 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier FIGURE 2. 3 X 3 MATRIX MULTIPLIER -- MODE 00 A 12 KA1 KA 10 KA2 KA3 21 21 21 B 12 KB1 KB 10 KB2 KB3 21 21 21 C 12 KC1 KC 10 KC2 KC3 21 21 21 12 (MSB) 12 (MSB) 12 (MSB) X Y Z Video Imaging Products 5 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier FIGURE 3. 9-TAP FIR FILTER -- MODE 01 A 12 KA1 KA 10 KA2 KA3 21 21 21 B 12 4 KB1 KB 10 KB2 KB3 3 21 21 21 KC1 KC 10 KC2 KC3 21 21 21 CASIN 16 16 5 21 21 100002 (HALF-LSB ROUNDING) 16 (MSB) NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS CASOUT Video Imaging Products 6 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier FIGURE 4. 3 X 3-PIXEL CONVOLVER -- MODE 10 A 12 KA1 KA 10 KA2 KA3 21 21 21 B 12 KB1 KB 10 KB2 KB3 21 21 21 C 12 KC1 KC 10 KC2 KC3 21 21 21 CASIN 16 16 5 21 21 100002 (HALF-LSB ROUNDING) 16 (MSB) CASOUT Video Imaging Products 7 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier FIGURE 5. A 12 4 X 2-PIXEL CONVOLVER -- MODE 11 3 KA1 KA 10 KA2 KA3 21 21 21 B 12 KB1 KB 10 KB2 KB3 21 21 21 0 KC1 KC 10 KC2 KC3 21 21 21 CASIN 16 16 5 21 21 100002 (HALF-LSB ROUNDING) 16 (MSB) NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS CASOUT Video Imaging Products 8 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ............................................................................... -0.5 V to VCC + 0.5 V Signal applied to high impedance output ...................................................................... -0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 4.75 V VCC 5.25 V 4.50 V VCC 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition Vcc = Min., IOH = -2.0 mA Vcc = Min., IOL = 4.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 10 40 160 12 10 10 V V V A A mA mA pF pF Ground VIN VCC (Note 12) (Note 12) (Notes 5, 6) (Note 7) TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz Video Imaging Products 9 08/16/2000-LDS.2250-L 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE 3212109876543210987654321098765432 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 32121098765432109876543210987654321 1 32121098765432109876543210987654321 Min 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 Min DEVICES INCORPORATED Symbol Symbol MILITARY OPERATING RANGE (-55C to +125C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) tD tH tS tPWH tPWL tCYC tD tH tS tPWH tPWL tCYC Parameter Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time Parameter Output Delay Input Hold Time Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time 10 10 15 33 0 8 33* Max 18 12 x 10-bit Matrix Multiplier Min 10 15 33 12 10 10 25 Video Imaging Products 2 0 6 LF2250- 25 33* Max Max 25 16 LF2250- Min Min 10 10 25 20 2 9 8 0 6 6 08/16/2000-LDS.2250-L 25* 20 LF2250 Max Max 15 20 LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier 3 X 3 MATRIX MULTIPLIER -- MODE 00 2 tPWH 10 11 SWITCHING WAVEFORMS: 1 CLK tS CWE1-0 01 3 4 tPWL 00 5 6 7 8 tH KA, KB, KC Kx1 Kx2 Kx3 A, B, C 0 0 1.0 0 0 0 MODE1-0 00 tD X11-0 KA1 + KB1 + KC1 Y11-0 KA2 + KB2 + KC2 Z11-0 KA3 + KB3 + KC3 SWITCHING WAVEFORMS: 9-TAP FIR FILTER -- MODE 01 1 CLK tS CWE1-0 01 2 tPWH 10 11 3 tPWL 12 13 14 15 16 17 tH KA, KB, KC Kx1 Kx2 Kx3 A, B 0 0 1.0 0 0 0 0 0 MODE1-0 01 CASIN15-0 Q13 tD CASOUT15-0 KB1 KC3 KC2 KC1 Q13 Video Imaging Products 11 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier SWITCHING WAVEFORMS: 3 X 3-PIXEL CONVOLVER -- MODE 10 1 CLK tS CWE1-0 01 2 tPWH 10 11 3 tPWL 6 7 8 9 10 11 tH KA, KB, KC Kx1 Kx2 Kx3 A, B, C 0 0 1.0 0 0 0 0 0 0 MODE1-0 10 CASIN15-0 Q7 tD CASOUT15-0 KA3 + KB3 + KC3 KA2 + KB2 + KC2 KA1 + KB1 + KC1 Q7 SWITCHING WAVEFORMS: 4 X 2-PIXEL CONVOLVER -- MODE 11 1 CLK tS CWE1-0 01 2 tPWH 10 11 3 tPWL 6 7 8 9 10 11 tH KA, KB, KC Kx1 Kx2 Kx3 A, B 0 0 1.0 0 0 0 0 0 0 MODE1-0 11 CASIN15-0 Q8 tD CASOUT15-0 KA3 + KB3 KA2 + KB3 KA1 + KB1 KC1 + KC3 Q8 Video Imaging Products 12 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot and overshoot. measures are recommended: Input levels below ground or above VCC will be clamped beginning at -0.6 V and a. A 0.1 F ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of -0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary b. Ground and VCC supply planes from those designated but operation is must be brought directly to the DUT guaranteed as specified. socket or contactor fingers. 5. Supply current for a given application can be accurately approximated by: NCV2 F c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.0V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point N = total number of device outputs of view of the external system driving C = capacitive load per output the chip. Setup time, for example, is V = supply voltage specified as a minimum since the exterF = clock frequency nal system must supply at least that 6. Tested with all outputs changing ev- much time to meet the worst-case reery cycle and no load, at a 20 MHz clock quirements of all parts. Responses from the internal circuitry are specified rate. from the point of view of the device. 7. Tested with all inputs within 0.1 V of Output delay, for example, is specified VCC or Ground, no load. as a maximum since worst-case opera8. These parameters are guaranteed tion of any device always provides data within that time. but not 100% tested. where 4 Video Imaging Products 13 08/16/2000-LDS.2250-L LF2250 DEVICES INCORPORATED 12 x 10-bit Matrix Multiplier ORDERING INFORMATION XC7 XC8 VCC XC9 XC10 XC11 GND MODE0 MODE1 C11 C10 C9 C8 C7 GND C6 C5 C4 VCC C3 C2 C1 C0 B11 B10 B9 B8 B7 B6 B5 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 XC6 XC5 XC4 XC3 XC2 XC1 XC0 GND YC11 YC10 YC9 VCC YC8 Y7 Y6 GND Y5 Y4 YC0 VCC YC1 YC2 YC3 GND ZC0 ZC1 ZC2 ZC3 ZC4 ZC5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View B4 B3 CLK B2 B1 B0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND CWE0 CWE1 KA9 KA8 KA7 KA6 KA5 KA4 KA3 KA2 KA1 Speed 0C to +70C -- COMMERCIAL SCREENING 0C to +70C -- COMMERCIAL SCREENING 25 ns 20 ns LF2250QC25 LF2250QC20 -55C to +125C-- COMMERCIAL SCREENING -40C to +85C -- COMMERCIAL SCREENING -55C to +125C -- MIL-STD-883 COMPLIANT -55C to +125C -- MIL-STD-883 COMPLIANT ZC6 ZC7 ZC8 GND ZC9 ZC10 ZC11 KC0 KC1 KC2 KC3 GND KC4 KC5 KC6 VCC KC7 KC8 KC9 KB0 KB1 KB2 KB3 KB4 KB5 KB6 KB7 KB8 KB9 KA0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Plastic Quad Flatpack (Q1) Video Imaging Products 14 08/16/2000-LDS.2250-L 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 DEVICES INCORPORATED Speed -55C to +125C -- MIL-STD-883 COMPLIANT -55C to +125C -- COMMERCIAL SCREENING ORDERING INFORMATION 120-pin 0C to +70C -- COMMERCIAL SCREENING M G N H D C K E B A F L J YC11 XC0 YC3 YC1 YC9 YC10 GND XC1 XC4 XC7 ZC5 ZC2 ZC1 Y4 Y5 Y7 1 YC2 GND YC0 YC8 XC2 XC5 XC9 XC10 MODE0 C11 ZC8 ZC10 KC1 ZC7 ZC4 ZC0 Y6 2 GND XC3 XC6 XC8 XC11 MODE1 C9 VCC VCC ZC3 ZC9 ZC11 KC2 ZC6 GND KC0 GND VCC 3 VCC GND C10 GND VCC 4 Ceramic Pin Grid Array (G4) Discontinued Package Top View Through Package (i.e., Component Side Pinout) KC3 5 KEY 15 KC4 KC5 C8 6 KC7 KC6 C6 C7 7 KC8 KC9 KB0 C4 C5 8 KB1 KB2 KB4 C0 C2 C3 9 KB3 KB5 KB8 B11 10 C1 B8 12 x 10-bit Matrix Multiplier GND CLK KB6 KB9 KA1 KA4 KA8 CWE1 CWE0 A11 B10 11 Video Imaging Products A3 A7 B5 B9 KB7 KA2 KA5 KA7 12 A0 A2 A6 A9 B0 B3 B6 B7 KA0 KA3 KA6 KA9 A10 13 A1 A4 A5 A8 B1 B2 B4 08/16/2000-LDS.2250-L LF2250 |
Price & Availability of LF2250
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